INFO:2026-10-22T06:34:48Z:root:pulling... From github.com:llvm/llvm-project * branch main -> FETCH_HEAD f3b29c37148a..fb3ef8699477 main -> origin/main Switched to branch 'main' Your branch is behind 'origin/main' by 1 commit, and can be fast-forwarded. (use "git pull" to update your local branch) HEAD is now at fb3ef8699477 [LoongArch] Implement `computeKnownBitsForTargetNode()` cases for `V{ALL,ANY}_{,NON}ZERO` (#230799) INFO:2026-10-22T06:34:54Z:root:syncing... Deleted branch merge (was 7477657119c6). Switched to a new branch 'merge' branch 'merge' set up to track 'origin/main'. [merge b4cf4d00f204] [gn build] Port ea4c43d796c4 1 file changed, 1 insertion(+) [gn build] Port ea4c43d796c4 -- https://github.com/llvm/llvm-project/commit/ea4c43d796c4 INFO:2026-10-22T06:34:56Z:root:building ninja: Entering directory `out/gn' [0/1] Regenerating ninja files [1/331] COPY ../../libcxxabi/include/__cxxabi_config.h include/c++/v1/__cxxabi_config.h [2/331] COPY ../../libcxxabi/include/cxxabi.h include/c++/v1/cxxabi.h [3/331] ACTION //libcxx/include:copy_headers(//llvm/utils/gn/build/toolchain:unix) [4/331] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchISelLowering.o [5/331] AR lib/libLLVMLoongArchCodeGen.a [6/331] LINK obj/llvm/unittests/Target/LoongArch/LoongArchTests [7/331] LINK ./bin/llvm-cxxmap [8/331] LINK obj/llvm/unittests/CGData/CodeGenDataTests [9/331] LINK ./bin/llvm-cxxdump [10/331] LINK obj/llvm/unittests/DebugInfo/GSYM/DebugInfoGSYMTests [11/331] LINK ./bin/llvm-dwp [12/331] LINK obj/llvm/unittests/ExecutionEngine/JITLink/JITLinkTests [13/331] LINK ./bin/llvm-xray [14/331] LINK ./bin/llvm-ar [15/331] LINK ./bin/llvm-rtdyld [16/331] LINK ./bin/llvm-lipo [17/331] ACTION //llvm/tools/llvm-ar:llvm-ranlib(//llvm/utils/gn/build/toolchain:unix) [18/331] ACTION //llvm/tools/llvm-ar:llvm-dlltool(//llvm/utils/gn/build/toolchain:unix) [19/331] LINK ./bin/llvm-libtool-darwin [20/331] ACTION //llvm/tools/llvm-ar:llvm-lib(//llvm/utils/gn/build/toolchain:unix) [21/331] LINK ./bin/llvm-ml [22/331] LINK obj/llvm/unittests/Passes/PassBuilderBindings/PassesBindingsTests [23/331] LINK ./bin/llvm-mc [24/331] LINK obj/llvm/unittests/MC/MCTests [25/331] ACTION //llvm/tools/llvm-ml:llvm-ml64(//llvm/utils/gn/build/toolchain:unix) [26/331] LINK obj/bolt/unittests/Passes/PassTests [27/331] LINK ./bin/llvm-jitlink [28/331] LINK obj/bolt/unittests/Profile/ProfileTests [29/331] LINK ./bin/llvm-bolt-heatmap [30/331] LINK ./bin/llvm-exegesis [31/331] LINK ./bin/llvm-bolt [32/331] ACTION //bolt/tools/driver:perf2bolt(//llvm/utils/gn/build/toolchain:unix) [33/331] LINK ./bin/llvm-lto2 [34/331] SOLINK ./lib/libLTO.so [35/331] LINK ./bin/llvm-c-test [36/331] ACTION //bolt/tools/driver:llvm-boltdiff(//llvm/utils/gn/build/toolchain:unix) [37/331] LINK obj/llvm/unittests/CodeGen/CodeGenTests [38/331] LINK ./bin/opt [39/331] LINK ./bin/dsymutil [40/331] LINK obj/llvm/unittests/MIR/MIRTests [41/331] LINK obj/llvm/unittests/DebugInfo/LogicalView/DebugInfoLogicalViewTests [42/331] LINK ./bin/llvm-split [43/331] LINK obj/bolt/unittests/Core/CoreTests [44/331] LINK ./bin/llvm-gsymutil [45/331] LINK obj/llvm/unittests/Target/TargetMachineCTests [46/331] LINK ./bin/llvm-isel-fuzzer [47/331] LINK ./bin/llvm-opt-fuzzer [48/331] LINK ./bin/llvm-ir2vec [49/331] LINK obj/llvm/unittests/MI/MITests [50/331] LINK ./bin/llvm-dwarfutil [51/331] LINK ./bin/llvm-reduce [52/331] LINK obj/llvm/unittests/DebugInfo/DWARF/DebugInfoDWARFTests [53/331] LINK obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests [54/331] LINK ./bin/clang-scan-deps [55/331] LINK ./bin/lld [56/331] LINK obj/clang/unittests/CrossTU/CrossTUTests [57/331] LINK ./bin/clang-nvlink-wrapper [58/331] LINK obj/clang/unittests/Tooling/Syntax/SyntaxTests [59/331] LINK ./bin/llvm-lto [60/331] LINK obj/lld/unittests/AsLibAll/LLDAsLibAllTests [61/331] LINK ./bin/llc [62/331] LINK obj/lld/unittests/AsLibELF/LLDAsLibELFTests [63/331] ACTION //lld/tools/lld:wasm-ld(//llvm/utils/gn/build/toolchain:unix) [64/331] LINK ./bin/clang-sycl-linker [65/331] ACTION //lld/tools/lld:ld.lld(//llvm/utils/gn/build/toolchain:unix) [66/331] ACTION //lld/tools/lld:lld-link(//llvm/utils/gn/build/toolchain:unix) [67/331] ACTION //lld/tools/lld:ld64.lld(//llvm/utils/gn/build/toolchain:unix) [68/331] LINK ./bin/clang-linker-wrapper [69/331] LINK obj/clang/unittests/Interpreter/ExceptionTests/ClangReplInterpreterExceptionTests [70/331] LINK obj/clang/unittests/Driver/ClangDriverTests [71/331] SOLINK ./lib/libclang.so [72/331] LINK ./bin/clang-check [73/331] LINK obj/clang/unittests/libclang/libclangTests [74/331] LINK obj/clang/unittests/Interpreter/ClangReplInterpreterTests [75/331] LINK obj/clang/unittests/Tooling/ToolingTests [76/331] LINK obj/clang/unittests/libclang/CrashTests/libclangCrashTests [77/331] LINK ./bin/clang-repl [78/331] LINK ./bin/lldb-test [79/331] LINK ./bin/lldb-dap [80/331] LINK ./bin/lldb [81/331] LINK ./bin/clang [82/331] ACTION //clang/tools/driver:clang-cl(//llvm/utils/gn/build/toolchain:unix) [83/331] ACTION //clang/tools/driver:clang-cpp(//llvm/utils/gn/build/toolchain:unix) [84/331] ACTION //clang/tools/driver:clangxx(//llvm/utils/gn/build/toolchain:unix) [85/331] ACTION //compiler-rt/test/hwasan:lit_site_cfg(//llvm/utils/gn/build/toolchain:stage2_unix) [86/331] ACTION //compiler-rt/test/builtins:builtins_mode_cfg(//llvm/utils/gn/build/toolchain:stage2_unix) [87/331] ACTION //compiler-rt/test:lit_common_configured(//llvm/utils/gn/build/toolchain:stage2_unix) [88/331] ACTION //compiler-rt/test/asan:lit_site_cfg(//llvm/utils/gn/build/toolchain:stage2_unix) [89/331] ACTION //compiler-rt/test/lsan:asan_mode_cfg(//llvm/utils/gn/build/toolchain:stage2_unix) [90/331] ACTION //llvm/include/llvm/Config:TargetExegesis.def(//llvm/utils/gn/build/toolchain:stage2_unix) [91/331] ACTION //llvm/include/llvm/Support:write_extension_def(//llvm/utils/gn/build/toolchain:stage2_unix) [92/331] ACTION //llvm/include/llvm/Config:Disassemblers.def(//llvm/utils/gn/build/toolchain:stage2_unix) [93/331] ACTION //llvm/include/llvm/Config:AsmParsers.def(//llvm/utils/gn/build/toolchain:stage2_unix) [94/331] ACTION //llvm/include/llvm/Config:llvm-config(//llvm/utils/gn/build/toolchain:stage2_unix) [95/287] ACTION //llvm/include/llvm/Config:TargetMCAs.def(//llvm/utils/gn/build/toolchain:stage2_unix) [96/287] ACTION //llvm/include/llvm/Config:AsmPrinters.def(//llvm/utils/gn/build/toolchain:stage2_unix) [97/287] ACTION //llvm/include/llvm/Config:Targets.def(//llvm/utils/gn/build/toolchain:stage2_unix) [98/287] ACTION //llvm/include/llvm/Config:abi-breaking(//llvm/utils/gn/build/toolchain:stage2_unix) [99/143] ACTION //llvm/include/llvm/Config:Targets(//llvm/utils/gn/build/toolchain:stage2_unix) [100/143] ACTION //llvm/include/llvm/Support:write_vcsrevision(//llvm/utils/gn/build/toolchain:stage2_unix) [101/143] ACTION //llvm/include/llvm/Config:config(//llvm/utils/gn/build/toolchain:stage2_unix) [102/111] ACTION //compiler-rt/lib/ubsan:ubsan_static_cxx_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix) [103/111] ACTION //compiler-rt/lib/ubsan:ubsan_static_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix) [104/111] ACTION //compiler-rt/lib/ubsan:version_script(//llvm/utils/gn/build/toolchain:stage2_unix) [105/111] ACTION //compiler-rt/lib/hwasan:version_script(//llvm/utils/gn/build/toolchain:stage2_unix) [106/111] ACTION //libcxx/src:cxx_symlink(//llvm/utils/gn/build/toolchain:stage2_unix) [107/111] ACTION //libcxx/src:cxx_linker_script(//llvm/utils/gn/build/toolchain:stage2_unix) [108/111] ACTION //compiler-rt/lib/ubsan:ubsan_loop_detect_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix) [109/111] LINK ./bin/c-index-test [110/111] SOLINK lib/clang/24/lib/linux/libclang_rt.hwasan_aliases-x86_64.so [111/111] SOLINK lib/clang/24/lib/linux/libclang_rt.ubsan_standalone-x86_64.so INFO:2026-10-22T06:35:23Z:root:analyze skipping analyze because previous build was not green INFO:2026-10-22T06:35:23Z:root:testing INFO:2026-10-22T06:35:23Z:root:test check-clang ninja: Entering directory `out/gn' [0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix) llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld -- Testing: 27910 tests, 64 workers -- Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (1 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056314cef9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056314cef6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056314cefa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58d2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056314ce8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056314ce8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056314ce748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056314cb23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056314cb23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056314cb23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (2 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c0f219eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c0f216e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c0f21a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdae6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdae6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdae6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdae6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c0f1afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c0f1afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c0f1948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c0ee43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c0ee43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdae6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdae6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdae6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c0ee43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (3 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr # | ... # `---data was truncated (10240/27541) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9c245beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9c2458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9c245c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cf3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cf3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cf3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cf3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9c23f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9c23f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9c23d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9c2085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9c2085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cf3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cf3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cf3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9c2085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (4 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648210e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648210dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648210e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c92049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c92049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c92031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564821078bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564821078a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056482105d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564820d0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564820d0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c92032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c920330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564820d0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (5 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.rdffr() # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr_z( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call @llvm.aarch64.sve.rdffr.z( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr.z() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000557b439a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b439a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b439a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94acd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94acd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94acd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94acced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b4393ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b4393ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b439238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b435d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b435d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94acceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94accef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94accef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b435d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (6 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560984f23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560984f20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560984f2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b09e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b09ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b09e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b09e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560984eb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560984eb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560984e9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560984b4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560984b4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b09e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b09e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b09e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560984b4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (7 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d714f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d714f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d714f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94ad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94ad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94ad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94ad831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d7148ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d7148ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d714738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d71122e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d71122b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94ad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94ad8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94ad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d71122a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (8 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = add <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fadd <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = add <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fadd <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055823e1b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055823e1b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055823e1b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2ee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2ee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2ee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2ee51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055823e14dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055823e14da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055823e1328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055823dde1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055823dde1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2ee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2ee51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2ee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055823dde1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (9 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf2bc09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf2bc06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf2bc0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e7a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e7a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e7a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e7a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf2bb9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf2bb9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf2bb848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf2b833e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf2b833b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e7a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e7a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e7a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf2b833a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (10 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555811dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555811d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555811dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44c1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44c12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44c1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44c1231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555581172bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555581172a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555811578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555580e06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555580e06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44c1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44c12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44c12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555580e06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (11 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(< # | ... # `---data was truncated (10240/11404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7ae6ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7ae6fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7ae70062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e31c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e31ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e31c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e31c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7ae695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7ae695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7ae67a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7ae329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7ae329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e31c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e31c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e31c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7ae329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (12 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055597e5a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055597e5a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055597e5a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafa721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafa72725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafa721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafa7203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055597e53ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055597e53ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055597e5238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055597e1d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055597e1d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fafa7204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafa72050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafa72050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055597e1d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (13 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (14 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cdcbddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cdcbdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cdcbde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60c6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60c68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60c6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60c6831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cdcb73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cdcb73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cdcb588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cdc807e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cdc807b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60c6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60c68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60c68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cdc807a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (15 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e994c0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e994c0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e994c1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b56a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b56aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b56a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b56a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e994ba5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e994ba5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e994b8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e994839e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e994839b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b56a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b56a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b56a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e994839a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (16 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608baa5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608baa58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608baa5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6343733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f634378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6343733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f634371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608ba9f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608ba9f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608ba9d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608ba685e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608ba685b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f634371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f634371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f634371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608ba685a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (17 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (18 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddcb9c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ddcb9bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ddcb9c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a5e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a5e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a5e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a5e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddcb956bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ddcb956a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ddcb93b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ddcb5eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ddcb5eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a5e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a5e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a5e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddcb5eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (19 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfirst_b( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pfirst.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pfirst.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d6ae0d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6ae0d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6ae0d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2387249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23872a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2387249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2387231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6ae06ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6ae06ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6ae0538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6add02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6add02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2387232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23872330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23872330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6add02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (20 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557260eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557260e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557260eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cf0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cf038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cf0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cf031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555726080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555726080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557260658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555725d14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555725d14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3cf031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cf031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cf031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555725d14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (21 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eca60deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561eca60ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561eca60e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1aef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1aef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1aef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1aeeed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eca5a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561eca5a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561eca5888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561eca237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561eca237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1aeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1aeeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1aeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561eca237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (22 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f734539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f734536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f73453a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bfde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bfdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bfde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bfde31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7344cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7344cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7344b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f734163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f734163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bfde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bfde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bfde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f734163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (23 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055598a6b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055598a6aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055598a6b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9984733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f998478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9984733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f998471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055598a647bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055598a647a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055598a62c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055598a2dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055598a2dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f998471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f998471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f998471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055598a2dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (24 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstrid # | ... # `---data was truncated (10240/28111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055babdbcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055babdbc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055babdbcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c0b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c0b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c0b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c0b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055babdb62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055babdb62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055babdb478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055babd7f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055babd7f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c0b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c0b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c0b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055babd7f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm64_vcreate.c (25 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind optnone # | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 { # | entry: # | %a1.addr = alloca i64, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <2 x float>, align 8 # | store i64 %a1, ptr %a1.addr, align 8 # | %0 = load i64, ptr %a1.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <2 x float>, ptr %__promote, align 8 # | store <2 x float> %1, ptr %__ret, align 8 # | %2 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %2, ptr %tmp, align 8 # | %3 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %3 # | } # | # | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612dcf39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612dcf36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612dcf3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfd4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfd4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfd4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfd4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612dcecfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612dcecfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612dceb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612dcb63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612dcb63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfd4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfd4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfd4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612dcb63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (26 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562317faeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562317fabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562317faf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85bfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562317f44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562317f44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562317f298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562317bd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562317bd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562317bd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm_acle_swp.c (27 of 27910) ******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7m-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret i32 %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648897d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648897d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648897d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81fce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81fcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81fce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81fce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056488976dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056488976da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648897528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564889401e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564889401b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81fce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81fce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81fce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564889401a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (28 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %x.addr, align 8 # | %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> # | ret <8 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | %p.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | store <8 x i8> %p, ptr %p.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %p.addr, align 8 # | %mask = and <8 x i8> %1, splat (i8 7) # | %shuf_idx = extractelement <8 x i8> %mask, i64 0 # | %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <8 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <8 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <8 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <8 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <8 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <8 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <8 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | ret <8 x i8> %shuf_ins21 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %x.addr, align 16 # | %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> # | ret <16 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %p.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store <16 x i8> %p, ptr %p.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %p.addr, align 16 # | %mask = and <16 x i8> %1, splat (i8 15) # | %shuf_idx = extractelement <16 x i8> %mask, i64 0 # | %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <16 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <16 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <16 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <16 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <16 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <16 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <16 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | %shuf_idx22 = extractelement <16 x i8> %mask, i64 8 # | %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22 # | %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8 # | %shuf_idx25 = extractelement <16 x i8> %mask, i64 9 # | %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25 # | %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9 # | %shuf_idx28 = extractelement <16 x i8> %mask, i64 10 # | %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28 # | %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10 # | %shuf_idx31 = extractelement <16 x i8> %mask, i64 11 # | %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31 # | %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11 # | %shuf_idx34 = extractelement <16 x i8> %mask, i64 12 # | %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34 # | %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12 # | %shuf_idx37 = extractelement <16 x i8> %mask, i64 13 # | %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37 # | %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13 # | %shuf_idx40 = extractelement <16 x i8> %mask, i64 14 # | %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40 # | %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14 # | %shuf_idx43 = extractelement <16 x i8> %mask, i64 15 # | %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43 # | %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15 # | ret <16 x i8> %shuf_ins45 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1fe7c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1fe7c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1fe7c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5729533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f572958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5729533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f572951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1fe75cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1fe75ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1fe7418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1fe3f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1fe3f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f572951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f572951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f572951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1fe3f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (29 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_l # | ... # `---data was truncated (10240/13585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593140f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593140eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593140f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f198f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f198f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f198f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f198f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559314087bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559314087a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055931406c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559313d1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559313d1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f198f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f198f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f198f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559313d1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (30 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (31 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (32 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/70979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f25f84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f25f81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f25f8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90e9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90e958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90e9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90e951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f25f1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f25f1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f25eff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f25baee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f25baeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90e951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90e951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90e951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f25baea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (33 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566fc117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566fc114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566fc11862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff247933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff24798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff247933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff24791b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566fc0adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566fc0ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566fc0928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566fbd41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566fbd41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff24791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff24791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff24791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566fbd41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (34 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd # | ... # `---data was truncated (10240/215044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056383827aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563838277e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056383827b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0673d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0673d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0673d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0673d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563838210bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563838210a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638381f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563837ea4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563837ea4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0673d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0673d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0673d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563837ea4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (35 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i) # | %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8> # | store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i) # | %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i) # | %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8> # | store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i) # | %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i) # | %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8> # | store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i) # | %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i) # | %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8> # | store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i) # | %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double> # | %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i) # | %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8> # | store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i) # | %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f64.i = bitcast <8 x i8> %1 # | ... # `---data was truncated (10240/18543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f6f292eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6f292be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6f292f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda78f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda78f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda78f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda78f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6f28c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6f28c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6f28a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6f2558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6f2558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda78f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda78f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda78f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6f2558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (36 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4a552aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4a5527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4a552b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ea2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ea2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ea2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ea2eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4a54c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4a54c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4a54a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4a5154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4a5154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ea2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ea2eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ea2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4a5154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (37 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clo_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639a40b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639a40b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639a40b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56a9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56a90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56a9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56a9031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639a404abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639a404aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639a402f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639a3cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639a3cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56a9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56a90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56a90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639a3cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (38 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dbed1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560dbed1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560dbed2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6bd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dbecb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560dbecb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560dbec9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560dbe949e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560dbe949b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dbe949a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (39 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8f16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr # | ... # `---data was truncated (10240/12880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f4ec715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4ec712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4ec71662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcab5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcab50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcab5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcab5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4ec6abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4ec6aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4ec6908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4ec33fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4ec33fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcab5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcab50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcab50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4ec33fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (40 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561d51c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561d51bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561d51c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc01bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc01bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc01bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc01bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561d5156bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005561d5156a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561d513b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561d4deae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561d4deab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc01bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc01bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc01bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561d4deaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (41 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f90c92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f90c8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f90c9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f073b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f073b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f073b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f073b403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f90c28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f90c28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f90c0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f908bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f908bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f073b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f073b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f073b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f908bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (42 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d533beaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d533be7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d533beb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5b2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5b2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5b2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5b2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d533b80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d533b80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d533b658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d533814e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d533814b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5b2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5b2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5b2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d533814a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (43 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (44 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fe9fcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fe9fc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fe9fcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60fad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60fad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60fad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60fad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fe9f60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fe9f60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fe9f458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558fe9bf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558fe9bf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60fad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60fad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60fad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fe9bf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (45 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function # | ... # `---data was truncated (10240/66322) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c3adf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c3adf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c3adf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc000b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc000b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc000b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc000b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c3ad8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c3ad8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c3ad718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c3aa20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c3aa20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc000b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc000b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc000b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c3aa20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (46 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612b003beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612b0038e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612b003c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03cf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612affd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612affd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612affb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612afc65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612afc65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612afc65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (47 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %sr # | ... # `---data was truncated (10240/288111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0a7275eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0a7272e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0a727662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e16533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e1658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e16533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e1651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0a720bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0a720ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0a71f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0a6e9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0a6e9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e1651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e1651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e1651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0a6e9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (48 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (49 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c35089deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c35089ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c35089e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafd5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafd518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafd5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafd511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c350833bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c350833a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3508188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3504c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3504c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fafd511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafd511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafd511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3504c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (50 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (51 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/14493) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf71d95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf71d92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf71d9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f137d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f137d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f137d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f137d803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf71d2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf71d2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf71d108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf719bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf719bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f137d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f137d8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f137d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf719bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (52 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cdebf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563cdebf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563cdebf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa760b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa760b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa760b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa760b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cdeb8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563cdeb8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563cdeb718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563cde820e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563cde820b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa760b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa760b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa760b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cde820a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (53 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584caab1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584caaaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584caab262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb9ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb9ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb9ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb9ca03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584caa47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584caa47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584caa2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584ca6dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584ca6dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb9ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb9ca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb9ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584ca6dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (54 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (55 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 nou # | ... # `---data was truncated (10240/78890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfa2f30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfa2f2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfa2f3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd84e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd84e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd84e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd84e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfa2ec6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfa2ec6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfa2eab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfa2b5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfa2b5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd84e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd84e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd84e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfa2b5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (56 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6a9167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6a9164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6a916862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4740f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4740f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4740f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4740f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6a90fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6a90fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6a90e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6a8d91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6a8d91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4740f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4740f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4740f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6a8d91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (57 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560404d79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560404d76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560404d7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4c0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4c0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4c0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4c0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560404d0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560404d0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560404cf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604049a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604049a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4c0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4c0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4c0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604049a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (58 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d5f8b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d5f8b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d5f8b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9096533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f909658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9096533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f909651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d5f84bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d5f84ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d5f8308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d5f4dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d5f4dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f909651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f909651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f909651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d5f4dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (59 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a53a8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a53a87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a53a8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76b3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76b34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76b3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76b3431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a53a20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a53a20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a53a058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a536b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a536b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76b3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76b34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76b34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a536b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (60 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"SmallDataLi # | ... # `---data was truncated (10240/10285) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd956ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd956cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd956cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fab831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd95664bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd95664a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd956498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd952f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd952f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fab8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd952f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (61 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_bf16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 t # | ... # `---data was truncated (10240/168193) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x00005566a7041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566a703ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566a704262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fbdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fbdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fbdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fbdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566a6fd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566a6fd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566a6fbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566a6c6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566a6c6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5fbdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fbdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fbdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566a6c6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (62 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a5c02beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a5c028e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a5c02c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5698a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5698aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5698a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5698a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a5bfc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a5bfc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a5bfa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a5bc55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a5bc55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5698a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5698a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5698a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a5bc55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (63 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/424049) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a98af9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a98af97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a98af9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3234105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f323415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3234105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32340ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a98af30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a98af30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a98af158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a98abc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a98abc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32340eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32340ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32340ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a98abc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (64 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555c3d43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555c3d40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555c3d4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a01049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a010a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a01049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a01031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555c3cd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555c3cd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555c3cbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555c396de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555c396db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a01032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a010330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a010330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555c396da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (65 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvtl_f32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fb0bfb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb0bfafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb0bfb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe40c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe40ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe40c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe40c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb0bf48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb0bf48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb0bf2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb0bbdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb0bbdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe40c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe40c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe40c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb0bbdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (66 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f6d81beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f6d818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f6d81c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa802333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa80238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa802333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa80231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f6d7b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f6d7b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f6d7968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f6d445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f6d445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa80231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa80231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa80231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f6d445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (67 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ea48d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ea48d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ea48da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6464733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f646478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6464733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f646471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ea486fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ea486fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ea48548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ea4503e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ea4503b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f646471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f646471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f646471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ea4503a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (68 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (69 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x # | ... # `---data was truncated (10240/29267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3a97a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3a979ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3a97a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa32aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa32aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa32aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa32aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3a9737bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3a9737a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3a971c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3a93cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3a93cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa32aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa32aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa32aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3a93cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (70 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | # | ... # `---data was truncated (10240/15969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3ea0c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3ea0c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3ea0c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51cfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51cfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51cfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51cfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3ea05cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3ea05ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3ea0418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3e9cf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3e9cf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51cfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51cfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51cfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3e9cf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (71 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , al # | ... # `---data was truncated (10240/92370) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c162dd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c162dd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c162dda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2978705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f297875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2978705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29786ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c162d6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c162d6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c162d548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c162a03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c162a03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29786eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29786ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29786ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c162a03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (72 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564877c7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564877c7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564877c7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4154b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4154b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4154b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4154b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564877c13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564877c13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564877bf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648778a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648778a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4154b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4154b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4154b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648778a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (73 of 27910) ******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default,default' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.wrapper = type { %struct.task } # | %struct.task = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" } # | %"struct.std::coroutine_handle.0" = type { ptr } # | %"struct.task::promise_type" = type { i8 } # | %"struct.std::suspend_always" = type { i8 } # | # | $_ZN4task12promise_type17get_return_objectEv = comdat any # | # | $_ZN4task12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN4task12promise_type11return_voidEv = comdat any # | # | $_ZN4task12promise_type13final_suspendEv = comdat any # | # | $_ZN7wrapperC1EO4task = comdat any # | # | $_ZN4taskD1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZN7wrapperC2EO4task = comdat any # | # | $_ZN4taskC1EOS_ = comdat any # | # | $_ZN4taskC2EOS_ = comdat any # | # | $_ZNSt16coroutine_handleIvEaSEDn = comdat any # | # | $_ZN4taskD2Ev = comdat any # | # | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any # | # | ; Function Attrs: mustprogress nounwind presplitcoroutine # | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %gro.active = alloca i1, align 1 # | %__promise = alloca %"struct.task::promise_type", align 1 # | %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6 # | %ref.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %ref.tmp2 = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1 # | store ptr %agg.result, ptr %result.ptr, align 8 # | %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null) # | %1 = call i1 @llvm.coro.alloc(token %0) # | br i1 %1, label %coro.alloc, label %coro.init # | # | coro.alloc: ; preds = %entry # | %2 = call i64 @llvm.coro.size.i64() # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14 # | br label %coro.init # | # | coro.init: ; preds = %coro.alloc, %entry # | %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ] # | %4 = call ptr @llvm.coro.begin(token %0, ptr %3) # | store i1 false, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %__promise) #9 # | call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9 # | call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | store i1 true, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9 # | call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br i1 %call1, label %init.ready, label %init.suspend # | # | init.suspend: ; preds = %coro.init # | %5 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9 # | %6 = call i8 @llvm.coro.suspend(token %5, i1 false) # | switch i8 %6, label %pre.gvo.conv [ # | i8 0, label %init.ready # | i8 1, label %init.cleanup # | ] # | # | init.cleanup: ; preds = %init.suspend # | br label %cleanup # | # | init.ready: ; preds = %init.suspend, %coro.init # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br label %cleanup # | # | cleanup: ; preds = %init.ready, %init.cleanup # | %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9 # | switch i32 %cleanup.dest.slot.0, label %unreachable [ # | i32 0, label %cleanup.cont # | i32 2, label %coro.cleanup # | ] # | # | cleanup.cont: ; preds = %cleanup # | call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | br label %coro.final # | # | coro.final: ; preds = %cleanup.cont # | call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9 # | call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br i1 %call4, label %final.ready, label %final.suspend # | # | final.suspend: ; preds = %coro.final # | %7 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9 # | %8 = call i8 @llvm.coro.suspend(token %7, i1 true) # | switch i8 %8, label %pre.gvo.conv [ # | i8 0, label %final.ready # | i8 1, label %final.cleanup # | ] # | # | final.cleanup: ; preds = %final.suspend # | br label %cleanup5 # | # | final.ready: ; preds = %final.suspend, %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br label %cleanup5 # | # | cleanup5: ; preds = %final.ready, %final.cleanup # | %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9 # | switch i32 %cleanup.dest.slot.1, label %unreachable [ # | i32 0, label %pre.gvo.conv # | i32 2, label %coro.cleanup # | ] # | # | pre.gvo.conv: ; preds = %cleanup5, %final.suspend, %init.suspend # | %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ] # | %InRamp = call i1 @llvm.coro.is_in_ramp() # | br i1 %InRamp, label %gro.conv, label %after.gro.conv # | # | gro.conv: ; preds = %pre.gvo.conv # | call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9 # | %cleanup.is_active = load i1, ptr %gro.active, align 1 # | br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done # | # | cleanup.action: ; preds = %gro.conv # | call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9 # | br label %cleanup.done # | # | cleanup.done: ; preds = %cleanup.action, %gro.conv # | br label %after.gro.conv # | # | after.gro.conv: ; preds = %cleanup.done, %pre.gvo.conv # | br i1 %9, label %cleanup.cont7, label %coro.ret # | # | cleanup.cont7: ; preds = %after.gro.conv # | br label %coro.cleanup # | # | coro.cleanup: ; preds = %cleanup.cont7, %cleanup5, %cleanup # | call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9 # | call void @llvm.lifetime.end.p0(ptr %__promise) #9 # | %10 = call ptr @llvm.coro.free(token %0, ptr %4) # | %11 = icmp ne ptr %10, null # | br i1 %11, label %coro.free, label %after.coro.free # | # | coro.free: ; preds = %coro.cleanup # | %12 = call i64 @llvm.coro.size.i64() # | call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9 # | br label %after.coro.free # | # | after.coro.free: ; preds = %coro.cleanup, %coro.free # | call void @llvm.coro.dead(ptr %4) # | br label %coro.ret # | # | coro.ret: ; preds = %after.coro.free, %after.gro.conv # | call void @llvm.coro.end(ptr null, i1 false, token none) # | ret void # | # | unreachable: ; preds = %cleanup5, %cleanup # | unreachable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1 # | # | ; Function Attrs: nounwind memory(none) # | declare i1 @llvm.coro.alloc(token) #2 # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #3 # | # | ; Function Attrs: nounwind memory(none) # | declare i64 @llvm.coro.size.i64() #2 # | # | ; Function Attrs: nounwind memory(argmem: readwrite) # | declare ptr @llvm.coro.begin(token, ptr writeonly) #4 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5 # | # | ; Function Attrs: mustprogress nounwind # | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %this.addr = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | store ptr %agg.result, ptr %result.ptr, align 8 # | store ptr %this, ptr %this.addr, align 8, !tbaa !7 # | %this1 = load ptr, ptr %this.addr, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"s # | ... # `---data was truncated (10240/31146) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default,default' -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default,default -S # | #0 0x0000561a5bacfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a5bacce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a5bad062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8713c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8713c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8713c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8713c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a5ba65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a5ba65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a5ba4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a5b6f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a5b6f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8713c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8713c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8713c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a5b6f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (74 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (75 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595c4689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595c4686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595c468a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f290a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f290a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f290a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f290a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595c461fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595c461fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595c46048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595c42b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595c42b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f290a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f290a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f290a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595c42b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (76 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557d1e516eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d1e513e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d1e51762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f408a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f408a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f408a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f408a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d1e4acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d1e4aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d1e4918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d1e140e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d1e140b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f408a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f408a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f408a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d1e140a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (77 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055967be7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055967be79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055967be7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf06d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf06d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf06d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf06d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055967be12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055967be12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055967bdf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055967baa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055967baa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf06d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf06d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf06d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055967baa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (78 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (79 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (80 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64( poison # | ... # `---data was truncated (10240/18569) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dc199beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dc1998e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dc199c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc356333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc35638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc356333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc35631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dc1931bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dc1931a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dc19168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dc15c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dc15c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc35631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc35631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc35631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dc15c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (81 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %v # | ... # `---data was truncated (10240/11349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557aaf83eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557aaf83be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557aaf83f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c86431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aaf7d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557aaf7d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557aaf7b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557aaf468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557aaf468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aaf468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (82 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558443c3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558443c3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558443c3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7936d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7936d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7936d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7936d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558443bd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558443bd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558443bb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558443867e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558443867b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7936d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7936d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7936d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558443867a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (83 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4a6ddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4a6dd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4a6ddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc123e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc123e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc123e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc123e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4a6d72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4a6d72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4a6d578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4a6a06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4a6a06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc123e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc123e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc123e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4a6a06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (84 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv # | ... # `---data was truncated (10240/165238) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af43e31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af43e2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af43e3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8de0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8de0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8de0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8de0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af43dc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af43dc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af43dac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af43a5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af43a5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8de0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8de0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8de0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af43a5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (85 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574e1b62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574e1b5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574e1b6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00cf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574e1af8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574e1af8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574e1add8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574e178ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574e178cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f00cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574e178ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (86 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.a # | ... # `---data was truncated (10240/28771) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558221025eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558221022e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055822102662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f305f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f305f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f305f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f305f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558220fbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558220fbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558220fa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558220c4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558220c4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f305f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f305f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f305f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558220c4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (87 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563ee50deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563ee50ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563ee50e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eca431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563ee4a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563ee4a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563ee4888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563ee137e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563ee137b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9eca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eca4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563ee137a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (88 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (89 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a59ef81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a59ef7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a59ef8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc20449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc20449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc20431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a59ef17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a59ef17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a59eefc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a59ebabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a59ebabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc20432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc204330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a59ebaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (90 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2c1c37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2c1c34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2c1c3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5ff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5ff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5ff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5ff51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2c1bcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2c1bcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2c1bb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2c1861e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2c1861b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5ff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5ff51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5ff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2c1861a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (91 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr % # | ... # `---data was truncated (10240/11173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559d92e47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d92e44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d92e4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faad0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faad078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faad0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faad071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d92dddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d92ddda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d92dc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d92a71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d92a71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faad071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faad071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faad071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d92a71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (92 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562e1ca1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e1ca19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e1ca1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b21c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b21c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b21c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b21c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e1c9b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e1c9b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e1c9978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e1c646e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e1c646b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b21c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b21c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b21c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e1c646a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (93 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055845a49feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055845a49ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055845a4a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9d7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9d7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9d7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9d7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055845a435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055845a435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055845a41a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055845a0c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055845a0c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9d7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9d7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9d7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055845a0c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (94 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005625eb022eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625eb01fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625eb02362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf8051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625eafb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625eafb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625eaf9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625eac4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625eac4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf8051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625eac4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (95 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb2b882eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb2b87fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb2b88362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc53db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc53db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc53db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc53db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb2b818bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb2b818a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb2b7fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb2b4ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb2b4acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc53db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc53db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc53db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb2b4aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (96 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 3 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 2 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_374 = alloca <4 x bfloat>, align 8 # | %__s0_374 = alloca <4 x bfloat>, align 8 # | %__s2_374 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.add # | ... # `---data was truncated (10240/18871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d6dd22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d6dd1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d6dd2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a92649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a92649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a92631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d6dcb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d6dcb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d6dc9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d6d94ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d6d94cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a92632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a926330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d6d94ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (97 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633ff74eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633ff74be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633ff74f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bcdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bcdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bcdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bcdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633ff6e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633ff6e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633ff6c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633ff378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633ff378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bcdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bcdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bcdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633ff378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (98 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ea3352deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea3352ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea3352e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e61049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e610a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e61049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e61031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea334c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea334c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea334a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea33157e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea33157b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e61032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e610330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e610330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea33157a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (99 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598154e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598154e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598154e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8bc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055981547abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055981547aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055981545f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055981510ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055981510eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055981510ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (100 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005639e839eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639e839be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639e839f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b80d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b80d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b80d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b80d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639e8334bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639e8334a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639e83198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639e7fc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639e7fc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b80d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b80d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b80d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639e7fc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a61eaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a61ea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a61ead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe89f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe89f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe89f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe89f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a61e42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a61e42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a61e278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a61ad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a61ad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe89f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe89f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe89f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a61ad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (102 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = # | ... # `---data was truncated (10240/15126) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563ea8f47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ea8f44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ea8f4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefc4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ea8eddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ea8edda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ea8ec28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ea8b71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ea8b71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fefc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefc4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ea8b71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (104 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/53158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c238e5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c238e59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c238e5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4b4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c238df2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c238df2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c238dd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c238a86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c238a86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4b4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c238a86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e17e10feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e17e10ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e17e11062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56eff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56eff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56eff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56eff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e17e0a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e17e0a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e17e08a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e17dd39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e17dd39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56eff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56eff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56eff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e17dd39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (106 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/16804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c5984f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5984f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5984f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea99449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea994a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea99449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea99431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c59848cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c59848ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5984718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c598120e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c598120b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea99432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea994330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea994330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c598120a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/134736) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c911f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c911efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c911f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64a3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64a30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64a3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64a3031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c91188bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c91188a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c9116d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c90e1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c90e1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f64a3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64a30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64a30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c90e1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/load.c (108 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %0, align 2 # | store <8 x half> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %2, ptr %__ret, align 16 # | %3 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %3, ptr %tmp, align 16 # | %4 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x float>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %0, align 4 # | store <4 x float> %1, ptr %ref.tmp, align 16 # | %2 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %2, ptr %__ret, align 16 # | %3 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %3, ptr %tmp, align 16 # | %4 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <2 x double>, ptr %0, align 8 # | store <2 x double> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %2, ptr %__ret, align 16 # | %3 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %3, ptr %tmp, align 16 # | %4 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load <2 x i64>, ptr %0, align 8 # | store <2 x i64> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %2, ptr %__ret, align 16 # | %3 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %3, ptr %tmp, align 16 # | %4 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store ptr %a # | ... # `---data was truncated (10240/415795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x0000562de20d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562de20d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562de20d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7609933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f760998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7609933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f760991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562de206bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562de206ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562de20508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562de1cffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562de1cffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f760991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f760991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f760991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562de1cffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1d97a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1d97a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1d97a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd20fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd20fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd20fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd20fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1d973dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1d973da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1d97228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1d93d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1d93d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd20fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd20fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd20fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1d93d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (110 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056316b72ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056316b729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056316b72d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9d2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056316b6c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056316b6c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056316b6a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056316b356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056316b356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056316b356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %not = xor i64 %0, -1 # | %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ca34aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ca34abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ca34af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f98333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f9838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f98333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f9831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ca3444bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ca3444a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ca34298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ca30d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ca30d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f9831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f9831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f9831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ca30d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store % # | ... # `---data was truncated (10240/13308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578ef5d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578ef5d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578ef5da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f472a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f472a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f472a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f472a431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578ef56fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578ef56fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578ef5548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578ef203e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578ef203b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f472a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f472a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f472a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578ef203a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056348dc82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056348dc7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056348dc8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91b6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91b678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91b6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91b671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056348dc18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056348dc18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056348dbfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056348d8ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056348d8acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91b671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91b671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91b671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056348d8aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056035f876eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056035f873e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056035f87762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadd8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadd838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadd8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadd831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056035f80cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056035f80ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056035f7f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056035f4a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056035f4a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadd831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadd831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadd831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056035f4a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f52e1b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f52e1b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f52e1ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdaed41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdaed4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdaed41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdaed403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f52e14fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f52e14fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f52e1348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f52dde3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f52dde3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdaed404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdaed4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdaed4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f52dde3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/26748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055619ee9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055619ee9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055619ee9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99e451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055619ee33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055619ee33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055619ee188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055619eac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055619eac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99e451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055619eac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dfc9d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555dfc9d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555dfc9da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2065f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2065f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2065f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2065f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dfc96fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555dfc96fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555dfc9548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dfc603e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dfc603b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2065f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2065f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2065f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dfc603a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639b637eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639b637be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639b637f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9018733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f901878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9018733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f901871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639b6314bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639b6314a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639b62f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639b5fa8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639b5fa8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f901871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f901871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f901871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639b5fa8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/64341) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c457deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c457dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c457df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2aa5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2aa58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2aa5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2aa5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c45774bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c45774a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c457598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c45408e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c45408b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2aa5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2aa58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2aa58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c45408a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i6 # | ... # `---data was truncated (10240/11946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc69089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc69086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc6908a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73ef533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73ef58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73ef533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73ef51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc6901fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc6901fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc690048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc68cb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc68cb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73ef51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73ef51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73ef51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc68cb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (123 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c501e8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c501e87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c501e8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc90d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc90d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc90d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc90d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c501e20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c501e20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c501e058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c501ab4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c501ab4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc90d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc90d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc90d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c501ab4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d66118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d66115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d6611962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f59e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f59ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f59e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f59e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d660aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d660aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d660938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d65d42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d65d42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f59e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f59e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f59e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d65d42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7afcc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7afcc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7afcc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f981cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f981cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f981cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f981caed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7afc5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7afc5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7afc408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7af8efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7af8efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f981caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f981caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f981caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7af8efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (126 of 27910) ******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7s-apple-darwin" # | # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, ptr %__p0.addr.i1, align 8 # | store <8 x i8> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %8, ptr %__ret.i3, align 8 # | %9 = load <8 x i8>, ptr %__ret.i3, align 8 # | %add.i = add <8 x i8> %3, %9 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x i16>, align 8 # | %__p1.addr.i2 = alloca <4 x i16>, align 8 # | %__ret.i3 = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %5 = load <4 x i16>, ptr %__p2.addr.i, align 8 # | store <4 x i16> %4, ptr %__p0.addr.i1, align 8 # | store <4 x i16> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16> # | %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16> # | %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i) # | %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %8, ptr %__ret.i3, align 8 # | %9 = load <4 x i16>, ptr %__ret.i3, align 8 # | %add.i = add <4 x i16> %3, %9 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %10 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <2 x i32>, align 8 # | %__p1.addr.i2 = alloca <2 x i32>, align 8 # | %__ret.i3 = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x i32>, ptr %__p2.addr.i, align 8 # | store <2 x i32> %4, ptr %__p0.addr.i1, align 8 # | store <2 x i32> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32> # | %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32> # | %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i) # | %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %8, ptr %__ret.i3, align 8 # | %9 = load <2 x i32>, ptr %__ret.i3, align 8 # | %add.i = add <2 x i32> %3, %9 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %10 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, pt # | ... # `---data was truncated (10240/2159854) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fe365aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe365abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe365af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86a021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86a02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86a021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86a0203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe36544bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe36544a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe365298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe361d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe361d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86a0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86a02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86a02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe361d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055831cfaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055831cfabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055831cfaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbba049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbba0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbba049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbba031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055831cf44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055831cf44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055831cf298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055831cbd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055831cbd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbba032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbba0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbba0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055831cbd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6fd7f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6fd7f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6fd7f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4430d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4430d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4430d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4430d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6fd78abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6fd78aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6fd76f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6fd41ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6fd41eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4430d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4430d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4430d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6fd41ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, al # | ... # `---data was truncated (10240/30013) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d15ac83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d15ac80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d15ac8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56dc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56dc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56dc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56dc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d15ac19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d15ac19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d15abfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d15a8ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d15a8adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56dc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56dc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56dc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d15a8ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (130 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000565117b55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565117b52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565117b5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70eb81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70eb8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70eb81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70eb803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565117aebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565117aeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565117ad08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056511777fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056511777fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70eb804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70eb8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70eb8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056511777fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, pt # | ... # `---data was truncated (10240/71947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558d1ff5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558d1ff2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558d1ff662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6bce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6bcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6bce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6bce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558d1f8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558d1f8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558d1f708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558d1c1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558d1c1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6bce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6bce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6bce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558d1c1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab5c103eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab5c100e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab5c10462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bf5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bf578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bf5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bf571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab5c099bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab5c099a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab5c07e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab5bd2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab5bd2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bf571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bf571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bf571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab5bd2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/34581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ca6d65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ca6d62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ca6d6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d1c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d1c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d1c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d1c6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ca6cfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ca6cfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ca6ce08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ca698fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ca698fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d1c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d1c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d1c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ca698fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (134 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560321de1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560321ddee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560321de262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04b5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04b52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04b5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04b5231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560321d77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560321d77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560321d5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560321a0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560321a0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04b5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04b52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04b52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560321a0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"Sma # | ... # `---data was truncated (10240/10293) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eceac28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eceac25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eceac2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52f8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eceabbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eceabbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eceaba38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ecea852e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ecea852b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ecea852a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (136 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb49b0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb49b07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb49b0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e65733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e6578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e65733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e6571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb49aa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb49aa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb49a858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb49734e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb49734b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e6571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e6571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e6571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb49734a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558327293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558327290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055832729462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbbb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbbb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbbb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbbb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558327229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558327229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055832720e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558326ebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558326ebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbbb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbbb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbbb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558326ebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/20090) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bebbdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564bebbdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564bebbdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf11849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf118a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf11849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf11831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bebb74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564bebb74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564bebb598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564beb808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564beb808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf11832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf118330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf118330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564beb808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (140 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005607369f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607369eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607369f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f5de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f5dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f5de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f5de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560736987bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560736987a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056073696c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056073661be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056073661bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f5de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f5de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f5de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056073661ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (141 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__ret.i, align 8 # | %2 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__ret.i, align 8 # | %2 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__ret.i, align 8 # | %2 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__ret.i, align 16 # | %2 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__ret.i, align 16 # | %2 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__ret.i, align 16 # | %2 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 { # | entry: # | # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055a07e9f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a07e9f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a07e9f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f545fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f545fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f545fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f545fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a07e98dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a07e98da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a07e9728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a07e621e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a07e621b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f545fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f545fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f545fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a07e621a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d81ac4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d81ac1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d81ac562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e4161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e416725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e4161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e41603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d81a5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d81a5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d81a3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d816eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d816eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e41604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e416050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e416050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d816eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (143 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d746950eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d74694de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d74695162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d8e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d8e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d8e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d8e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7468e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7468e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7468cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d74657ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d74657ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d8e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d8e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d8e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d74657aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e702c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e702bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e702c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba49f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba49f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba49f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba49f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e70257bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e70257a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e7023c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e6feebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e6feebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba49f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba49f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba49f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e6feeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, a # | ... # `---data was truncated (10240/71115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560b295aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560b2957e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560b295b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4324449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4324449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4324431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560b28f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560b28f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560b28d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560b2584e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560b2584b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4324432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560b2584a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575d25b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575d25b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575d25b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21e1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21e1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21e1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21e1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575d254dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575d254da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575d25328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575d21e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575d21e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21e1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21e1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21e1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575d21e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f0fd6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f0fd67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f0fd6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3282f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3282f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3282f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3282f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f0fd00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f0fd00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f0fce58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f0f994e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f0f994b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3282f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3282f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3282f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f0f994a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e953c12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e953c0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e953c1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f421f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f421f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f421f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f421f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e953ba8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e953ba8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e953b8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e95383ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e95383cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f421f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f421f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f421f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e95383ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f43b86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f43b83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f43b8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe236733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe23678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe236733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe23671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f43b1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f43b1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f43b018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f437b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f437b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe23671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe23671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe23671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f437b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (150 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b6a9305eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6a9302e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6a930662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8005705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f800575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8005705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80056ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6a929bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6a929ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6a92808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6a8f2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6a8f2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80056eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80056ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80056ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6a8f2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec76a7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec76a7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec76a7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94f7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94f72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94f7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94f7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec76a14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec76a14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec769f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec766a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec766a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94f7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94f72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94f72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec766a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (152 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s16_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv2i64( %5, %6, %7, %8, i32 16) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv2i64(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/33461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055dab9926eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dab9923e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dab992762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5e8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5e82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5e8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5e8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dab98bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dab98bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dab98a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dab9550e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dab9550b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5e8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5e82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5e82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dab9550a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9c1ba1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9c1b9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9c1ba262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f109eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f109eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f109eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f109eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9c1b37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9c1b37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9c1b1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9c17cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9c17cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f109eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f109eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f109eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9c17cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557268bb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557268bb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557268bb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2628533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f262858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2628533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f262851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557268b4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557268b4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557268b328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572687e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572687e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f262851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f262851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f262851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572687e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (155 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <1 x double>, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> # | store <1 x double> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/20383) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2196c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2196c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2196ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadd1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadd1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadd1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadd1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d21965fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d21965fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2196448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2192f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2192f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadd1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadd1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadd1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2192f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620ce5a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620ce5a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620ce5a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3e6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3e60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3e6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3e6031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620ce53abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620ce53aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620ce51f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620ce1cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620ce1ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3e6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3e60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3e60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620ce1cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfa # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a443507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a443504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a44350862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08ca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08ca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08ca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08ca631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a44349dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a44349da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4434828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a443131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a443131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08ca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08ca6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08ca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a443131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3 # | ... # `---data was truncated (10240/14330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e450289eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e450286e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e45028a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea52705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea5275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea52705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea526ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e45021fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e45021fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4502048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e44feb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e44feb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea526eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea526ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea526ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e44feb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574610c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574610c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574610ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20c5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20c56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20c5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20c5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055746105fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055746105fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574610448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557460cf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557460cf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f20c5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20c56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20c56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557460cf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (160 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # | #0 0x000055aba42b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aba42ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aba42b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce77533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce7758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce77533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce7751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aba4246bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aba4246a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aba422b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aba3edae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aba3edab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce7751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce7751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce7751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aba3edaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559226eb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559226eb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559226eb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa33da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa33daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa33da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa33da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559226e4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559226e4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559226e308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559226adfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559226adfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa33da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa33da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa33da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559226adfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align # | ... # `---data was truncated (10240/29111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2024f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2024f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2024f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a15333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a1538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a15333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a1531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a202489bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a202489a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a20246e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a20211de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a20211db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a1531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a1531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a1531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a20211da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (163 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | call void @llvm.aarch64.sve.st4.nxv16i8.p0( %7, %8, %9, %10, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %4) # | call void @llvm.aarch64.sve.st4.nxv8i16.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %4) # | call void @llvm.aarch64.sve.st4.nxv4i32.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %da # | ... # `---data was truncated (10240/73307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005607e1c88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607e1c85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607e1c8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ece049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ece0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ece049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ece031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607e1c1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607e1c1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607e1c038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607e18b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607e18b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ece032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ece0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ece0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607e18b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c57908eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c57908be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c57908f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff09049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff09049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff09031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c579024bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c579024a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5790098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c578cb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c578cb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff09032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff090330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c578cb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055721d065eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055721d062e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055721d06662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6635f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6635f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6635f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6635f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055721cffbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055721cffba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055721cfe08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055721cc8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055721cc8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6635f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6635f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6635f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055721cc8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d99d434eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d99d431e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d99d43562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5528649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55286a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5528649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5528631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d99d3cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d99d3caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d99d3af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d99d05ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d99d05eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5528632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55286330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55286330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d99d05ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a307ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615a3079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615a307d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff61d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff61d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff61d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff61d431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a3012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615a3012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615a2ff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615a2ca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615a2ca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff61d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff61d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff61d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a2ca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc5f9cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc5f9c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc5f9cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b0cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b0cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b0cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b0ceed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc5f961bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc5f961a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc5f9468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc5f5f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc5f5f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b0ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b0ceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b0ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc5f5f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (169 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (170 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3) # | store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3) # | store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x2_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x2_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [2 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4) # | store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x2_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x2_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [2 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4) # | store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x3_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x3_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [3 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <8 x i8>, ptr %arrayidx4.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5) # | store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x3_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x3_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [3 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <16 x i8>, ptr %arrayidx4.i, align 16 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5) # | store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x4_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x4_t, align 8 # | %b.a # | ... # `---data was truncated (10240/125901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aac2571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aac256ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aac257262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1c9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1c9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1c9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1c9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aac2507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aac2507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aac24ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aac219be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aac219bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1c9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1c9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1c9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aac219ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (171 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s8_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s16_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s32_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s64_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svclamp_single_s8_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (174 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(, , ptr # | ... # `---data was truncated (10240/26796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fb5be72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb5be6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb5be7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f446d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f446d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f446d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f446d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb5be08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb5be08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb5bded8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb5ba9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb5ba9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f446d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f446d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f446d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb5ba9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b53070eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b5306de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b5307162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f120fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f120fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f120fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f120fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b53006bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b53006a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b52feb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b52c9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b52c9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f120fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f120fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f120fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b52c9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (176 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (177 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 { # | entry: # | ret target("aarch64.svcount") zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000565422aaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565422aabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565422aaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3203133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f320318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3203133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f320311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565422a44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565422a44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565422a298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654226d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654226d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f320311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f320311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f320311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654226d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (178 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %cmp = icmp eq <8 x i8> %2, %3 # | %sext = sext <8 x i1> %cmp to <8 x i8> # | store <8 x i8> %sext, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i32> # | store <16 x i32> %sext, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %cmp = icmp eq <8 x i64> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i64> # | store <8 x i64> %sext, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x # | ... # `---data was truncated (10240/78785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000563e7b81aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e7b817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e7b81b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc7631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e7b7b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e7b7b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e7b7958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e7b444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e7b444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bc7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e7b444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (179 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557e452d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e452d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e452d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff547a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff547aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff547a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff547a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e4526cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e4526ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e452518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e44f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e44f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff547a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff547a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff547a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e44f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (180 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cb7ea0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb7ea0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb7ea0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1435533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f143558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1435533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f143551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb7e9a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb7e9a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb7e9888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb7e637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb7e637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f143551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f143551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f143551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb7e637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (181 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ad1e51feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad1e51ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad1e52062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1500f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1500f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1500f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1500f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad1e4b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad1e4b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad1e49a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad1e149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad1e149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1500f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1500f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1500f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad1e149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (182 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e389741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e38973ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e38974262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd816a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd816aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd816a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd816a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3896d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3896d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3896bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e38936be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e38936bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd816a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd816a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd816a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e38936ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (183 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563af1b38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563af1b35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563af1b3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadeb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadeb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadeb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadeb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563af1acebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563af1acea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563af1ab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563af1762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563af1762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadeb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadeb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadeb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563af1762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (184 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s64( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (185 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563b24310eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b2430de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b2431162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe266849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe266849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe266831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b242a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b242a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b2428b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b23f3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b23f3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe266832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2668330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b23f3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (186 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005647de87aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647de877e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647de87b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde8eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde8eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde8eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde8eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647de810bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647de810a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647de7f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647de4a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647de4a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde8eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde8eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde8eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647de4a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (187 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1 # | store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %5, ptr %__ret, align 16 # | %6 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %6, ptr %tmp, align 16 # | %7 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0 # | store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %5, ptr %__ret, align 8 # | %6 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %6, ptr %tmp, align 8 # | %7 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca # | ... # `---data was truncated (10240/14230) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563fe2624eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fe2621e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fe262562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d2f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fe25babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fe25baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fe259f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fe224ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fe224eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fe224ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (189 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c489c0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c489c0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c489c0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6efca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6efca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6efca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6efca03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c489ba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c489ba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c489b898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c489838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c489838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6efca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6efca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6efca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c489838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (190 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2f64( zeroi # | ... # `---data was truncated (10240/32102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557b9b6cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b9b6c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b9b6cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0ab133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0ab18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0ab133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0ab11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b9b661bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b9b661a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b9b6468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b9b2f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b9b2f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0ab11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0ab11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0ab11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b9b2f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (191 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c323a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c323a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c323a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae83e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae83e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae83e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae83e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c32399ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c32399ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3239838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c323632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c323632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae83e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae83e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae83e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c323632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (192 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005588ac2cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588ac2cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588ac2ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f722e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f722e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722e231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588ac263bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588ac263a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588ac2488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588abef7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588abef7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f722e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588abef7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564662125eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564662122e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056466212662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ae4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ae438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ae4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ae431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646620bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646620bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646620a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564661d4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564661d4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ae431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ae431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ae431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564661d4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/addv.c (194 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svaddv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.faddv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.faddv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svaddv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.faddv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.faddv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svaddv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.faddv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.faddv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | a # | ... # `---data was truncated (10240/10826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x00005592c35fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592c35f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592c35fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe640333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe64038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe640333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe64031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c3592bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592c3592a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592c35778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592c3226e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592c3226b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe64031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe64031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe64031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c3226a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (195 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s16_s16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u16_u16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (196 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (197 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560167061eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056016705ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056016706262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd0221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd022725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd0221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd02203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560166ff7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560166ff7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560166fdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560166c8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560166c8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd02204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd022050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd022050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560166c8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (198 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = ashr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = lshr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = ashr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = lshr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %shl = shl <16 x i32> %0, %1 # | store <16 x i32> %shl, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 imma # | ... # `---data was truncated (10240/51475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005569d7727eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569d7724e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569d772862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d6f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d6f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d6f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d6f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569d76bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569d76bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569d76a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569d7351e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569d7351b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d6f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d6f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d6f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569d7351a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (199 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cf92ac6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf92ac3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf92ac762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f733ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f733ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f733ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f733aced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf92a5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf92a5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf92a418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf926f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf926f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f733aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f733acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f733acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf926f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (200 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056240e518eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056240e515e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056240e51962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83b3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83b3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83b3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83b3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056240e4aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056240e4aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056240e4938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056240e142e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056240e142b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83b3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83b3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83b3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056240e142a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (201 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, %val.coerce0, %val.coerce1, %val.coerce2, %val.coerce3) #0 { # | entry: # | %val = alloca { , , , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %val.coerce0, 0 # | %1 = insertvalue { , , , } %0, %val.coerce1, 1 # | %2 = insertvalue { , , , } %1, %val.coerce2, 2 # | %3 = insertvalue { , , , } %2, %val.coerce3, 3 # | store { , , , } %3, ptr %val, align 16 # | %val1 = load { , , , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , , , } %val1, ptr %val.addr, align 16 # | %4 = load i32, ptr %base.addr, align 4 # | %5 = load { , , , }, ptr %val.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/len.c (202 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vscale.i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005627fcd78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627fcd75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627fcd7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa042333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa04238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa042333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa04231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627fcd0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627fcd0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627fccf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627fc9a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627fc9a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa04231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa04231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa04231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627fc9a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (203 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (204 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_mf8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_bf16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (205 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056212d808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056212d805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056212d80962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf3221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf322725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf3221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf32203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056212d79ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056212d79ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056212d7838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056212d432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056212d432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf32204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf322050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf322050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056212d432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (206 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563452d4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563452d4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563452d4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed70f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed70f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed70f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed70f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563452ce4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563452ce4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563452cc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563452978e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563452978b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed70f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed70f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed70f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563452978a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (207 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %2, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | # | ... # `---data was truncated (10240/178306) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559a72a12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a72a0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a72a1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98a2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98a22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98a2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98a2231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a729a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a729a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a7298d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a7263ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a7263cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98a2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98a22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98a22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a7263ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (208 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a8f4ae7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8f4ae4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8f4ae862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0563b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0563b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0563b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0563aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8f4a7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8f4a7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8f4a628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8f4711e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8f4711b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0563aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0563aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0563aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8f4711a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (209 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562766118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562766115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056276611962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7524333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f752438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7524333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f752431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627660aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627660aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627660938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562765d42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562765d42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f752431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f752431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f752431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562765d42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbcf1b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbcf1afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbcf1b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6af705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6af75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6af705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6af6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbcf148bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbcf148a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbcf12d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbceddce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbceddcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6af6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6af6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6af6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbceddca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align # | ... # `---data was truncated (10240/43617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6325eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6325ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6325ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb68133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb6818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb68133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb6811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e632584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e632584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6325698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e632218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e632218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb6811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb6811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb6811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e632218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (212 of 27910) ******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z9cond_boolu10__SVBool_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ult %0, %1 # | %2 = load , ptr %a.addr, align 2 # | %3 = load , ptr %b.addr, align 2 # | %vector_select = select %cmp, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_i8u10__SVInt8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_u8u11__SVUint8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i16u11__SVInt16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u16u12__SVUint16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i32u11__SVInt32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u32u12__SVUint32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i64u11__SVInt64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u64u12__SVUint64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f16u13__SVFloat16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f32u13__SVFloat32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (213 of 27910) ******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> # | ret <8 x float> %shufp # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> # | ret <2 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> # | ret <4 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> # | ret <8 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <4 x double> %b, ptr %b.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <4 x double>, ptr %b.addr, align 32 # | %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> # | ret <4 x double> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> # | ret <8 x float> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <4 x i64>, align 32 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <4 x i64> %b, ptr %b.addr, align 32 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <4 x i64>, ptr %b.addr, align 32 # | %3 = bitcast <4 x i64> %2 to <8 x i32> # | %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> # | %4 = bitcast <8 x i32> %vperm to <4 x i64> # | ret <4 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3 # | store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16 # | %7 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__d.i = alloca double, align 8 # | %.compoundliteral.i = alloca <4 x double>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load double, ptr %1, align 1 # | store double %2, ptr %__d.i, align 8 # | %3 = load double, ptr %__d.i, align 8 # | %vecinit.i = insertelement <4 x double> poison, double %3, i32 0 # | %4 = load double, ptr %__d.i, align 8 # | %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1 # | %5 = load double, ptr %__d.i, align 8 # | %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2 # | %6 = load double, ptr %__d.i, align 8 # | %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3 # | store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32 # | %7 = load <4 x double>, ptr %.compoundliteral.i, align 32 # | ret <4 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <8 x float>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <8 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3 # | %7 = load float, ptr %__f.i, align 4 # | %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4 # | %8 = load float, ptr %__f.i, align 4 # | %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5 # | %9 = load float, ptr %__f.i, align 4 # | %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6 # | %10 = load float, ptr %__f.i, align 4 # | %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7 # | store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32 # | %11 = load <8 x float>, ptr %.compoundliteral.i, align 32 # | ret <8 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <4 x float>, align 16 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> # | %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> # | ret <8 x float> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <2 x double>, align 16 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> # | %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> # | ret <4 x double> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <2 x i64>, align 16 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <2 x i64>, ptr # | ... # `---data was truncated (10240/21933) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f707bf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f707bf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f707bfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff580f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff580f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff580f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff580eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f707b8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f707b8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f707b748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f707823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f707823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff580eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff580eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff580eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f707823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %vs2, bflo # | ... # `---data was truncated (10240/43940) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3dd636eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3dd633e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3dd63762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8310933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f831098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8310933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f831091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3dd5ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3dd5cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3dd5b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3dd260e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3dd260b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f831091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f831091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f831091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3dd260a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (215 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (216 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559712967eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559712964e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055971296862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51ef533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51ef58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51ef533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51ef51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597128fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597128fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597128e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559712591e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559712591b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51ef51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51ef51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51ef51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559712591a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (217 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { < # | ... # `---data was truncated (10240/50499) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c41b8c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c41b8c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c41b8c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc92933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc9298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc92933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc9291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c41b85ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c41b85ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c41b8438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c41b4f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c41b4f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc9291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc9291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc9291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c41b4f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (218 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562a32060eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a3205de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a3206162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86b941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86b94725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86b941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86b9403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a31ff6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a31ff6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a31fdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a31c8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a31c8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86b9404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86b94050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86b94050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a31c8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (219 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562a1fc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a1fc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a1fc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f0ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f0caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f0ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f0ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a1fbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a1fbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a1fbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a1f883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a1f883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f0ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f0ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f0ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a1f883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (220 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005560bce86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560bce83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560bce8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78d3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78d3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78d3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78d3eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560bce1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560bce1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560bce018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560bcab0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560bcab0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78d3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78d3eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78d3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560bcab0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (221 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055de8879deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de8879ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de8879e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56f5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56f555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56f5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56f54ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de88733bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de88733a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de887188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de883c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de883c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56f54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56f54ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56f54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de883c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (222 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za16_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za32_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dad6535eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dad6532e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dad653662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38a4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dad64cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dad64cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dad64b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dad615fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dad615fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dad615fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (223 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558f317eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f317e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f317eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cfc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cfc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cfc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cfc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f31780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f31780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f317658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f31414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f31414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cfc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cfc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cfc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f31414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (224 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (225 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056317555eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056317555be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056317555f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b9af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631754f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631754f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631754d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563175188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563175188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563175188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (226 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (227 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005612b4cd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612b4ccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612b4cd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61e8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61e8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61e8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61e8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612b4c68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612b4c68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612b4c4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612b48fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612b48fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61e8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61e8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61e8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612b48fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (228 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbo # | ... # `---data was truncated (10240/21216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560035261eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056003525ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056003526262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5834b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5834b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5834b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5834b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600351f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600351f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600351dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560034e8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560034e8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5834b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5834b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5834b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560034e8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (229 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splat # | ... # `---data was truncated (10240/24132) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556203c42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556203c3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556203c4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5da6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5da6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5da6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5da6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556203bd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556203bd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556203bbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055620386ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055620386cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5da6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5da6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5da6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055620386ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (230 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (231 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564eeceffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eecefce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eecf0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2417249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2417249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2417231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eece95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eece95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eece7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564eecb29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564eecb29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2417232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24172330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eecb29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (232 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558e010bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e010b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e010bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f820a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f820a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f820a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f820a831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e01051bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e01051a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e010368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e00ce5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e00ce5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f820a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f820a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f820a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e00ce5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (233 of 27910) ******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13) # | ret <2 x double> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundlit # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c5783eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c5783be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c5783f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9b4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c577d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c577d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c577b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c57468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c57468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c57468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (235 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_mf8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_bf16() #0 { # | entry: # | ret undef # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056367fd0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056367fd07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056367fd0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0792049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0792049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0792031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056367fca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056367fca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056367fc858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056367f934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056367f934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0792032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07920330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056367f934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu( %ma # | ... # `---data was truncated (10240/619127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e62ea3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e62ea0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e62ea462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74eb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e62e39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e62e39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e62e1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e62acde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e62acdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74eb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e62acda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (237 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (238 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d05d408eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d05d405e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d05d40962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa7c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa7c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa7c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa7c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d05d39ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d05d39ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d05d3838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d05d032e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d05d032b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa7c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa7c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa7c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d05d032a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (239 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564b5e9a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b5e99ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b5e9a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f7f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f7f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f7f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f7f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b5e937bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b5e937a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b5e91c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b5e5cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b5e5cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f7f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f7f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f7f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b5e5cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (240 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (241 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_72 = alloca <4 x i16>, align 8 # | %__s0_72 = alloca <4 x i16>, align 8 # | %__s1_72 = alloca <4 x i16>, align 8 # | %__s2_72 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_72, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_72, align 8 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_72, align 8 # | %3 = load <4 x i16>, ptr %__s0_72, align 8 # | %4 = load <4 x i16>, ptr %__s1_72, align 8 # | %5 = load <4 x i16>, ptr %__s2_72, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_72, align 8 # | %11 = load <4 x i16>, ptr %__ret_72, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_62 = alloca <8 x i16>, align 16 # | %__s0_62 = alloca <8 x i16>, align 16 # | %__s1_62 = alloca <8 x i16>, align 16 # | %__s2_62 = alloca <4 x i16>, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_62, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_62, align 16 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_62, align 8 # | %3 = load <8 x i16>, ptr %__s0_62, align 16 # | %4 = load <8 x i16>, ptr %__s1_62, align 16 # | %5 = load <4 x i16>, ptr %__s2_62, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | %mul = mul <8 x i16> %4, %10 # | %add = add <8 x i16> %3, %mul # | store <8 x i16> %add, ptr %__ret_62, align 16 # | %11 = load <8 x i16>, ptr %__ret_62, align 16 # | store <8 x i16> %11, ptr %tmp1, align 16 # | %12 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_70 = alloca <2 x i32>, align 8 # | %__s0_70 = alloca <2 x i32>, align 8 # | %__s1_70 = alloca <2 x i32>, align 8 # | %__s2_70 = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_70, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_70, align 8 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_70, align 8 # | %3 = load <2 x i32>, ptr %__s0_70, align 8 # | %4 = load <2 x i32>, ptr %__s1_70, align 8 # | %5 = load <2 x i32>, ptr %__s2_70, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | %mul = mul <2 x i32> %4, %10 # | %add = add <2 x i32> %3, %mul # | store <2 x i32> %add, ptr %__ret_70, align 8 # | %11 = load <2 x i32>, ptr %__ret_70, align 8 # | store <2 x i32> %11, ptr %tmp1, align 8 # | %12 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_60 = alloca <4 x i32>, align 16 # | %__s0_60 = alloca <4 x i32>, align 16 # | %__s1_60 = alloca <4 x i32>, align 16 # | %__s2_60 = alloca <2 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_60, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1_60, align 16 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_60, align 8 # | %3 = load <4 x i32>, ptr %__s0_60, align 16 # | %4 = load <4 x i32>, ptr %__s1_60, align 16 # | %5 = load <2 x i32>, ptr %__s2_60, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> # | store <4 x i32> %lane, ptr %ref.tmp, align 16 # | %8 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %8, ptr %__ret, align 16 # | %9 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %9, ptr %tmp, align 16 # | %10 = load <4 x i32>, ptr %tmp, align 16 # | %mul = mul <4 x i32> %4, %10 # | %add = add <4 x i32> %3, %mul # | store <4 x i32> %add, ptr %__ret_60, align 16 # | %11 = load <4 x i32>, ptr %__ret_60, align 16 # | store <4 x i32> %11, ptr %tmp1, align 16 # | %12 = load <4 x i32>, ptr %tmp1, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_482 = alloca <4 x i16>, align 8 # | %__s0_482 = alloca <4 x i16>, align 8 # | %__s1_482 = alloca <4 x i16>, align 8 # | %__s2_482 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_482, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_482, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_482, align 16 # | %3 = load <4 x i16>, ptr %__s0_482, align 8 # | %4 = load <4 x i16>, ptr %__s1_482, align 8 # | %5 = load <8 x i16>, ptr %__s2_482, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_482, align 8 # | %11 = load <4 x i16>, ptr %__ret_482, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_472 = alloca <8 x i16>, align 16 # | %__s0_472 = alloca <8 x i16>, align 16 # | %__s1_472 = alloca <8 # | ... # `---data was truncated (10240/857511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000560b80f1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b80f18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b80f1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e4ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e4baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e4ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e4ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b80eb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b80eb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b80e968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b80b45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b80b45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e4ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e4ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e4ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b80b45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (242 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_ra # | ... # `---data was truncated (10240/35066) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x000055e62f409eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e62f406e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e62f40a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f28f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f28f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f28f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f28eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e62f39fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e62f39fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e62f3848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e62f033e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e62f033b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f28eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f28eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f28eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62f033a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (243 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvt.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvtn.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt1_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16( %0) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt2_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr # | ... # `---data was truncated (10240/17058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b9ea184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9ea181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9ea18562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a5df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9ea11abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9ea11aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9ea0ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9e9daee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9e9daeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9e9daea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (244 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_bf16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptra # | ... # `---data was truncated (10240/10361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056539f5b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056539f5b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056539f5b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1119649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11196a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1119649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1119631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056539f54dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056539f54da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056539f5328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056539f1e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056539f1e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1119632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11196330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11196330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056539f1e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (245 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vdot1.i = bitcast <8 x i8> %4 to <4 x half> # | %vdot2.i = bitcast <8 x i8> %5 to <4 x half> # | %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i) # | store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vdot1.i = bitcast <16 x i8> %4 to <8 x half> # | %vdot2.i = bitcast <16 x i8> %5 to <8 x half> # | %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i) # | store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane) # | store <4 x float> %vdot2, ptr %ref.tmp, align 16 # | %7 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %7, ptr %__ret, align 16 # | %8 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %8, ptr %tmp, align 16 # | %9 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aa # | ... # `---data was truncated (10240/11256) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000562d86112eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d8610fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d8611362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33f7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33f7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33f7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33f7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d860a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d860a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d8608d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d85d3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d85d3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33f7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33f7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33f7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d85d3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (246 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005589e4f8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589e4f87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589e4f8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfeee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfeeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfeee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfeee31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589e4f20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005589e4f20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589e4f058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589e4bb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589e4bb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfeee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfeee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfeee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589e4bb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dc8d11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564dc8d0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564dc8d1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e56449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e56449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e56431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dc8ca7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dc8ca7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dc8c8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564dc893be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564dc893bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e56432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e564330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dc893ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (248 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (249 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 3, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 4, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559b4b7c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b4b7c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b4b7c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f063ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f063eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f063ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f063ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b4b75abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b4b75aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b4b73f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b4b3eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b4b3eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f063ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f063ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f063ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b4b3eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (250 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559f28899eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f28896e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f2889a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe485b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe485b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe485b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe485aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f2882fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f2882fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f288148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f284c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f284c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe485aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe485aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe485aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f284c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (251 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560cb777feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cb777ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cb778062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f041cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f041cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f041cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f041cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cb7715bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560cb7715a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560cb76fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560cb73a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560cb73a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f041cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f041cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f041cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cb73a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (252 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055f14b9f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f14b9ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f14b9f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d27b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d27b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d27b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d27b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f14b986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f14b986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f14b96b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f14b61ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f14b61ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d27b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d27b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d27b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f14b61aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (253 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a7f7ee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7f7edee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7f7ee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7523133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f752318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7523133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f752311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7f7e77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7f7e77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7f7e5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7f7b0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7f7b0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f752311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f752311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f752311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7f7b0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (254 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i) # | store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i) # | store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005587d266eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587d266be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587d266f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f80449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f80449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f80431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587d2604bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587d2604a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587d25e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587d2298e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587d2298b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f80432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f804330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587d2298a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (255 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_bf16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d38de59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d38de56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d38de5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6617849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6617849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6617831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d38ddefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d38ddefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d38ddd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d38da83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d38da83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6617832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d38da83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (256 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f16( %pg, %op1, half noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560b8bbc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b8bbc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b8bbc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa31ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa31ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa31ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa31ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b8bb5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b8bb5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b8bb418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b8b7f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b8b7f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa31ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa31ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa31ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b8b7f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (257 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, %6, %7, %8, %9, %10, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 # | ... # `---data was truncated (10240/39820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000559bf987deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bf987ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bf987e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa7c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa7c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa7c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa7c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bf9813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bf9813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bf97f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bf94a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bf94a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa7c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa7c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa7c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bf94a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (258 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm. # | ... # `---data was truncated (10240/14102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055806d2fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055806d2f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055806d2fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdde9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdde995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdde9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdde98ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055806d291bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055806d291a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055806d2768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055806cf25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055806cf25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdde98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdde98ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdde98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055806cf25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (259 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056219566eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056219566be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056219566f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb161a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb161aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb161a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb161a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562195604bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562195604a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621955e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562195298e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562195298b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb161a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb161a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb161a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562195298a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (260 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ce996a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce996a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce996a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd343133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd34318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd343133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd34311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce99639bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce99639a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce9961e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce992cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce992cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd34311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd34311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd34311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce992cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (261 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dd2a0a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd2a09fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd2a0a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9784333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f978438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9784333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f978431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd2a038bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd2a038a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd2a01d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd29ccce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd29cccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f978431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f978431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f978431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd29ccca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f # | ... # `---data was truncated (10240/165246) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a32fc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a32fbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a32fc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb1ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb1eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb1ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb1ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a32f58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a32f58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a32f3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a32bece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a32becb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb1ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb1ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb1ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a32beca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/store.c (263 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | store <4 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <2 x float> # | store <2 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | store <1 x double> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %val.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %val, ptr %val.addr, align 8 # | %0 = load <8 x i8>, ptr %val.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | store <4 x i16> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store <1 x i64> %val, ptr %val.addr, align 8 # | %0 = load <1 x i64>, ptr %val.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %ptr.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | store <1 x i64> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | store <8 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x float>, align 16 # | %__s1 = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <4 x float> # | store <4 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr # | ... # `---data was truncated (10240/446007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000056070b149eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056070b146e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056070b14a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ea0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ea078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ea0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ea071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056070b0dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056070b0dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056070b0c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056070ad73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056070ad73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ea071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ea071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ea071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056070ad73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (264 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s8_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (265 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056480ad4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056480ad4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056480ad4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcabc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcabc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcabc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcabc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056480ace4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056480ace4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056480acc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056480a978e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056480a978b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcabc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcabc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcabc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056480a978a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (266 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005592082a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592082a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592082a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d80733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d8078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d80733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d8071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055920823cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055920823ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592082218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559207ed0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559207ed0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d8071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d8071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d8071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559207ed0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (267 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svzero_zt() #0 { # | entry: # | call void @llvm.aarch64.sme.zero.zt(i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c9a0e06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9a0e03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9a0e0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73c5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73c5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73c5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73c5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9a0d9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9a0d9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9a0d818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9a0a30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9a0a30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73c5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73c5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73c5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9a0a30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (268 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/64727) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c74c8a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c74c8a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c74c8a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f899c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f899c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f899c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f899c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c74c83dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c74c83da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c74c8228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c74c4d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c74c4d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f899c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f899c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f899c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c74c4d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (269 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556e75b0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e75b09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e75b0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f455ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f455ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f455ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f455ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e75aa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e75aa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e75a878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e75736e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e75736b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f455ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f455ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f455ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e75736a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (270 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (271 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/77120) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b6ef03feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6ef03ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6ef04062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f088b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f088b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f088b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f088b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6eefd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6eefd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6eefba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6eec69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6eec69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f088b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f088b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f088b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6eec69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (272 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpklo.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpklo.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a440ad2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a440acfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a440ad362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf89305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf8935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf89305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf892ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a440a68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a440a68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a440a4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4406fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4406fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf892eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf892ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf892ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4406fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (273 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cnot.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cnot.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (274 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <8 x i16> %2, %3 # | store <8 x i16> %mul.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <4 x i32> %2, %3 # | store <4 x i32> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | s # | ... # `---data was truncated (10240/798827) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ca061b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca061b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca061b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff80a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff80a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff80a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff80a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca0614dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca0614da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca061328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca05de1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca05de1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff80a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff80a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff80a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca05de1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (275 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ed0071feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed0071ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed0072062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f039b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f039b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f039b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f039b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed006b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed006b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed0069a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed00349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed00349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f039b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f039b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f039b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed00349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (276 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (277 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i) # | store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i) # | store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i) # | store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i) # | store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i) # | store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i) # | store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/162735) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563a0db92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a0db8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a0db9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f11c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f11ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f11c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f11c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a0db28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a0db28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a0db0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a0d7bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a0d7bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f11c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f11c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f11c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a0d7bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557663953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557663950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055766395462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fceba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fceba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fceba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fceba431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576638e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576638e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576638ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055766357de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055766357db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fceba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fceba4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fceba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055766357da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (279 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.smmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smmla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_u32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.ummla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ummla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usmmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usmmla.nxv4i32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fc7dcb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc7dcb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc7dcb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04c3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04c398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04c3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04c391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc7dc49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc7dc49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc7dc2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc7d8dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc7d8ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04c391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04c391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04c391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc7d8dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (280 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005587b59b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587b59afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587b59b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc00e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc00e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc00e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc00e631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587b5948bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587b5948a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587b592d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587b55dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587b55dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc00e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc00e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc00e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587b55dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (282 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.neg.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ca00659eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca00656e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca0065a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf73a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca005efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca005efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca005d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca00283e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca00283b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf73a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca00283a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (283 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_s8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn1.coerce3, 3 # | store { , , , } %3, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %4 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zn2.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zn2.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zn2.coerce3, 3 # | store { , , , } %7, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %9 = load { , , , }, ptr %zn1.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zn2.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | %19 = call { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret { , , , } %19 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_u8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %zn3.addr = alloca { , , , }, align 16 # | %zn4.addr = alloca { , , , }, align 16 # | %2 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %3 = insertvalue { , , , } %2, %zn1.coerce1, 1 # | %4 = insertvalue { , , , } %3, %zn1.coerce2, 2 # | %5 = insertvalue { , , , } %4, %zn1.coerce3, 3 # | store { , , , } %5, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %6 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %7 = insertvalue { , , , } %6, %zn2.coerce1, 1 # | %8 = insertvalue { , , , } %7, %zn2.coerce2, 2 # | %9 = insertvalue { , , , } %8, %zn2.coerce3, 3 # | store { , , , } %9, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | %zn3 = load { , , , }, ptr %0, align 16 # | %zn4 = load { , , , }, ptr %1, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | store { , , , } %zn3, ptr %zn3.addr, align 16 # | store { , , , } %zn4, ptr %zn4.addr, align 16 # | %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %11 = load { , , , }, ptr %zn1.addr, align 16 # | %12 = extractvalue { , , , } %11, 0 # | %13 = extractvalue { , , , } %11, 1 # | %14 = extractvalue { , , , } %11, 2 # | %15 = extractvalue { , , , } %11, 3 # | %16 = load { , , , }, ptr %zn2.addr, align 16 # | %17 = extractvalue { , , , } %16, 0 # | %18 = extractvalue { , , , } %16, 1 # | %19 = extractvalue { , , , } %16, 2 # | %20 = extractvalue { , , , } %16, 3 # | %21 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (284 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a033505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a033502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a03350662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd13849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd138a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd13849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd13831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a03349bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a03349ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0334808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a03312fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a03312fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd13832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd138330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd138330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a03312fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (285 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f0c534feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0c534ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0c535062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee64449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee64449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee64431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0c52e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0c52e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0c52ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0c4f79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0c4f79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee64432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee644330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0c4f79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (286 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, al # | ... # `---data was truncated (10240/12168) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558491670eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055849166de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055849167162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd485449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd485449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd485431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558491606bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558491606a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584915eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055849129ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055849129ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd485432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4854330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055849129aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (287 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orn.c (288 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.orn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005643fa8abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643fa8a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643fa8ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0515d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0515d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0515d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0515d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643fa841bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643fa841a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643fa8268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643fa4d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643fa4d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0515d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0515d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0515d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643fa4d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (289 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call # | ... # `---data was truncated (10240/48703) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005566a8d48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566a8d45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566a8d4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd2be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd2bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd2be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd2be31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566a8cdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566a8cdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566a8cc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566a8972e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566a8972b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd2be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd2be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd2be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566a8972a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (290 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | e # | ... # `---data was truncated (10240/32866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000557a0108aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a01087e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a0108b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4215049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4215049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4215031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a01020bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a01020a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a010058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a00cb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a00cb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4215032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42150330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a00cb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (291 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s64( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d75b527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d75b524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d75b52862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f12933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f1298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f12933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f1291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d75b4bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d75b4bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d75b4a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d75b151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d75b151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f1291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f1291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f1291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d75b151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/68247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593a8d1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593a8d1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593a8d1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7de849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7de8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7de849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7de831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593a8cb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593a8cb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593a8c988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593a8947e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593a8947b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7de832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7de8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7de8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593a8947a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (295 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dd5592eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd5592be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd5592f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa80d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa80d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa80d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa80d003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd558c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd558c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd558a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd55558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd55558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa80d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa80d0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa80d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd55558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (296 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f48b390eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f48b38de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f48b39162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff35e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff35e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff35e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff35e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48b326bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f48b326a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f48b30b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f48afbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f48afbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff35e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff35e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff35e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f48afbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (297 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.uabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (298 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dacbb70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dacbb6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dacbb7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f191b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f191b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f191b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f191b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dacbb06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dacbb06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dacbaeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dacb79ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dacb79ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f191b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f191b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f191b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dacb79aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (299 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlasta_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lasta.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lasta.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlasta_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lasta.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lasta.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlasta_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lasta.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lasta.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlasta_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d96f72eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d96f72be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d96f72f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58fc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58fc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58fc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58fc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d96f6c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d96f6c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d96f6a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d96f358e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d96f358b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58fc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58fc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58fc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d96f358a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (300 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_f16_f16( # | ... # `---data was truncated (10240/27272) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559d3224feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d3224ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d3225062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0089b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0089b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0089b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0089b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d321e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d321e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d321ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d31e79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d31e79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0089b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0089b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0089b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d31e79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (301 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret # | ... # `---data was truncated (10240/58597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056007e445eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056007e442e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056007e44662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3941305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f394135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3941305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39412ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056007e3dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056007e3dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056007e3c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056007e06fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056007e06fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39412eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39412ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39412ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056007e06fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (302 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brkb.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkb.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055efff417eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055efff414e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055efff41862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3c0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3c0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3c0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3c0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efff3adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055efff3ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055efff3928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055efff041e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055efff041b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3c0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3c0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3c0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efff041a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/poly64.c (303 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %cmp.i = icmp eq <1 x i64> %2, %3 # | %sext.i = sext <1 x i1> %cmp.i to <1 x i64> # | store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %cmp.i = icmp eq <2 x i64> %2, %3 # | %sext.i = sext <2 x i1> %cmp.i to <2 x i64> # | store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %6 = and <1 x i64> %4, %5 # | %7 = icmp ne <1 x i64> %6, zeroinitializer # | %vtst.i = sext <1 x i1> %7 to <1 x i64> # | store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8 # | %8 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %8, ptr %__ret.i, align 8 # | %9 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %6 = and <2 x i64> %4, %5 # | %7 = icmp ne <2 x i64> %6, zeroinitializer # | %vtst.i = sext <2 x i1> %7 to <2 x i64> # | store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16 # | %8 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %8, ptr %__ret.i, align 16 # | %9 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_913 = alloca <1 x i64>, align 8 # | %__s0_913 = alloca <1 x i64>, align 8 # | %__s2_913 = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp3 = alloca <1 x i64>, align 8 # | %tmp4 = alloca <1 x i64>, align 8 # | %tmp5 = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0_913, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_913, align 8 # | %2 = load <1 x i64>, ptr %__s2_913, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <1 x i64>, ptr %__s0_913, align 8 # | store <1 x i64> %7, ptr %__s1, align 8 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <1 x i64>, ptr %__s1, align 8 # | %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0 # | store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <1 x i64>, ptr %ref.tmp3, align 8 # | store <1 x i64> %10, ptr %__ret, align 8 # | %11 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %11, ptr %tmp4, align 8 # | %12 = load <1 x i64>, ptr %tmp4, align 8 # | store <1 x i64> %12, ptr %__ret_913, align 8 # | %13 = load <1 x i64>, ptr %__ret_913, align 8 # | store <1 x i64> %13, ptr %tmp5, align 8 # | %14 = load <1 x i64>, ptr %tmp5, align 8 # | ret <1 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_909 = alloca <2 x i64>, align 16 # | %__s0_909 = alloca <2 x i64>, align 16 # | %__s2_909 = alloca <1 x i64>, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_909, align 16 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_909, align 8 # | %2 = load <1 x i64>, ptr %__s2_909, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <2 x i64>, ptr %__s0_909, align 16 # | store <2 x i64> %7, ptr %__s1, align 16 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <2 x i64>, ptr %__s1, align 16 # | %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1 # | store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <2 x i64>, ptr %ref.tmp3, align 16 # | store <2 x i64> %10, ptr %__ret, align 16 # | %11 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %11, ptr %tmp4, align 16 # | %12 = load <2 x i64>, ptr %tmp4, align 16 # | store <2 x i64> %12, ptr %__ret_909, align 16 # | %13 = load <2 x i64>, ptr %__ret_909, align 16 # | store <2 x i64> %13, ptr %tmp5, align 16 # | %14 = load <2 x i64>, ptr %tmp5, align 16 # | ret <2 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret_915 = alloca <2 x i64>, align 16 # | %__s0_915 = alloca <2 x i64>, align 16 # | %__s2_915 = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_915, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s2_915, align 16 # | %2 = load <2 x i64>, ptr %__s2_915, align 16 # | store <2 x i64> %2, ptr %__s02, align 16 # | %3 = load <2 x i64>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <2 x i64> %3, i32 1 # | store i64 %vgetq_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = # | ... # `---data was truncated (10240/22456) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056483d49beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056483d498e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056483d49c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b50533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b5058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b50533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b5051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056483d431bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056483d431a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056483d4168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056483d0c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056483d0c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b5051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b5051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b5051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056483d0c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (304 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u8_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s8_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s16_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u32_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s32_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u64_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f16_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_bf16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f32_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u64( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s64( %v) #2 { # | entry: # | % # | ... # `---data was truncated (10240/13584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561be4978eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561be4975e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561be497962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fd9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fd998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fd9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fd991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561be490ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561be490ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561be48f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561be45a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561be45a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4fd991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fd991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fd991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561be45a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (305 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_rsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %1, i64 0 # | %splat.splat = shufflevector %splat.splatinsert, poison, zeroinitializer # | %shl = shl %0, %splat.splat # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_lsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %0, i64 0 # | %splat.splat # | ... # `---data was truncated (10240/32491) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055da660a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da660a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da660a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c2e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c2e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c2e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c2e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da6603cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da6603ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da660218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da65cd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da65cd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c2e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c2e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c2e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da65cd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (306 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_b( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ab817a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab8179ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab817a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab81737bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab81737a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab8171c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab813cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab813cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab813cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (307 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | d # | ... # `---data was truncated (10240/75038) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bd6167deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd6167ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd6167e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4a5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4a578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4a5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4a571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd61613bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd61613a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd615f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd612a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd612a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4a571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4a571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4a571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd612a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (308 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (309 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta # | ... # `---data was truncated (10240/10820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e1fe9fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1fe9f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1fe9fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a9d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a9d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a9d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a9d8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1fe992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1fe992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1fe9778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1fe626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1fe626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a9d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a9d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a9d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1fe626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (310 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056222b9aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056222b9a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056222b9ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4371f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4371f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4371f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4371f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056222b940bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056222b940a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056222b9258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056222b5d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056222b5d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4371f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4371f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4371f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056222b5d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (311 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | # | ... # `---data was truncated (10240/11488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c7860f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7860f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7860f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cf1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cf1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cf1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cf1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c78608ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c78608ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7860738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c785d22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c785d22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1cf1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cf1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cf1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c785d22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (312 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i # | ... # `---data was truncated (10240/120468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a6ccf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a6ccede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a6ccf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a6cc86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a6cc86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a6cc6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a6c91ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a6c91ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ff371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a6c91aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (313 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_f16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (314 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_571 = alloca float, align 4 # | %__s0_571 = alloca float, align 4 # | %__s1_571 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_571, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_571, align 8 # | %2 = load float, ptr %__s0_571, align 4 # | %3 = load <2 x float>, ptr %__s1_571, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_571, align 4 # | %8 = load float, ptr %__ret_571, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret_570 = alloca double, align 8 # | %__s0_570 = alloca double, align 8 # | %__s1_570 = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_570, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_570, align 8 # | %2 = load double, ptr %__s0_570, align 8 # | %3 = load <1 x double>, ptr %__s1_570, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %4, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_570, align 8 # | %8 = load double, ptr %__ret_570, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_577 = alloca float, align 4 # | %__s0_577 = alloca float, align 4 # | %__s1_577 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_577, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_577, align 16 # | %2 = load float, ptr %__s0_577, align 4 # | %3 = load <4 x float>, ptr %__s1_577, align 16 # | store <4 x float> %3, ptr %__s0, align 16 # | %4 = load <4 x float>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <4 x float> %4, i32 3 # | store float %vgetq_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_577, align 4 # | %8 = load float, ptr %__ret_577, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret_575 = alloca double, align 8 # | %__s0_575 = alloca double, align 8 # | %__s1_575 = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_575, align 8 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1_575, align 16 # | %2 = load double, ptr %__s0_575, align 8 # | %3 = load <2 x double>, ptr %__s1_575, align 16 # | store <2 x double> %3, ptr %__s0, align 16 # | %4 = load <2 x double>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <2 x double> %4, i32 1 # | store double %vgetq_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_575, align 8 # | %8 = load double, ptr %__ret_575, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca double, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <1 x double>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store double %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x double>, ptr %__p0.addr.i, align 8 # | %3 = load double, ptr %__p1.addr.i, align 8 # | %4 = bitcast <1 x double> %2 to double # | %5 = fmul double %4, %3 # | store double %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %6, ptr %__ret.i, align 8 # | %7 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_626 = alloca float, align 4 # | %__s0_626 = alloca float, align 4 # | %__s1_626 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_626, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_626, align 8 # | %2 = load float, ptr %__s0_626, align 4 # | %3 = load <2 x float>, ptr %__s1_626, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | store float %2, ptr %__p0.addr.i, align 4 # | store float %7, ptr %__p1.addr.i, align 4 # | %8 = load float, ptr %__p0.addr.i, align 4 # | %9 = load float, ptr %__p1.addr.i, align 4 # | %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9) # | store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4 # | %10 = load float, ptr %ref.tmp.i, align 4 # | store float %10, ptr %__ret.i, align 4 # | %11 = load float, ptr %__ret.i, align 4 # | store float %11, ptr %__ret_626, align 4 # | %12 = load float, ptr %__ret_626, align 4 # | store float %12, ptr %tmp1, align 4 # | %13 = load float, ptr %tmp1, align 4 # | ret float %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_636 = alloca float, align 4 # | %__s0_636 = alloca float, align 4 # | %__s1_636 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_636, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_636, align 16 # | %2 = load float, ptr %__s0_636, align 4 # | %3 = load <4 x float>, ptr %__s1_636, align 16 # | store <4 x float> %3, ptr % # | ... # `---data was truncated (10240/74804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556a4d3a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a4d3a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4d3a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9dd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4d33bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4d33ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a4d3208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a4cfcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a4cfcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a4cfcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3978a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b39789de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3978a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27e8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b397836bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b397836a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b39781b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3974cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3974cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27e8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3974caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (316 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (317 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1) # | store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1) # | store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca double, align 8 # | %ref.tmp.i = alloca double, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1) # | store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8 # | %2 = load double, ptr %ref.tmp.i, align 8 # | store double %2, ptr %__ret.i, align 8 # | %3 = load double, ptr %__ret.i, align 8 # | ret double %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16> # | %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3) # | store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32> # | %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9) # | store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %2, ptr %__ret, align 8 # | %3 = load <4 x i16>, p # | ... # `---data was truncated (10240/770739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005635bd2ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635bd2fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635bd30062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7890333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f789038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7890333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f789031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635bd295bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635bd295a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635bd27a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635bcf29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635bcf29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f789031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f789031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f789031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635bcf29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (318 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/427567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561614f66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561614f63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561614f6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf10933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf1098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf10933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf1091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561614efcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561614efca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561614ee18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561614b90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561614b90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf1091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf1091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf1091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561614b90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (319 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 16 # | %__s0_827 = alloca <4 x i32>, align 16 # | %__s1_827 = alloca <16 x i8>, align 16 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp2 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_827, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1_827, align 16 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 16 # | %4 = load <16 x i8>, ptr %__s1_827, align 16 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__ # | ... # `---data was truncated (10240/29862) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x00005567013a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055670139ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567013a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec5af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556701337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556701337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055670131c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556700fcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556700fcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556700fcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (320 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.not.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.not.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (321 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | ... # `---data was truncated (10240/170489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632b1687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632b1684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632b168862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f850a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f850a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f850a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f850a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632b161dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632b161da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632b16028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632b12b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632b12b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f850a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f850a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f850a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632b12b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (323 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb.lane(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt.lane(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c7ef4cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7ef4cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7ef4ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6136a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6136a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6136a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6136a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7ef463bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7ef463a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7ef4488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7ef0f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7ef0f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6136a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6136a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6136a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7ef0f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (324 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv8f16(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_1( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_2( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 180) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_3( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 270) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv4f32( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv4f32(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv2f64( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv2f64(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (325 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558220099eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558220096e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055822009a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f284c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f284c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f284c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f284c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055822002fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055822002fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582200148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055821fcc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055821fcc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f284c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f284c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f284c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055821fcc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (326 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005563e5d53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563e5d50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563e5d5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1329105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f132915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1329105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13290ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563e5ce9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563e5ce9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563e5cce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563e597de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563e597db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13290eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13290ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13290ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563e597da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (327 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559615a3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559615a3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559615a4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faafdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faafdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faafdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faafdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596159d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596159d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596159ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559615669e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559615669b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faafdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faafdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faafdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559615669a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (328 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055870d697eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055870d694e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055870d69862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f516c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f516c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f516c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f516c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055870d62dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055870d62da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055870d6128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055870d2c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055870d2c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f516c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f516c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f516c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055870d2c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (329 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055f511f1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f511f1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f511f1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c9df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c9df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c9df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c9df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f511eb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f511eb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f511e998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f511b48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f511b48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c9df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c9df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c9df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f511b48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/recps.c (330 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000557ecdc0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ecdc07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ecdc0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9f121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9f12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9f121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9f1203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ecdba0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ecdba0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ecdb858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ecd834e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ecd834b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9f1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9f12050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9f12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ecd834a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ab10aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ab10abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ab10af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8014049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8014049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8014031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ab1044bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ab1044a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ab10298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ab0cd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ab0cd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8014032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80140330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ab0cd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (332 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005598e6f44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598e6f41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598e6f4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94d4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94d4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94d4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94d4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598e6edabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598e6edaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598e6ebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598e6b6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598e6b6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94d4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94d4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94d4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598e6b6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (333 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055996ad32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055996ad2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055996ad3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3065f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3065f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3065f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3065f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055996acc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055996acc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055996acad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055996a95ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055996a95cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3065f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3065f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3065f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055996a95ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (334 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f64( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560761e00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560761dfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560761e0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7708b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7708b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7708b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7708b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560761d96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560761d96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560761d7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560761a2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560761a2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7708b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7708b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7708b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560761a2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (335 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d19a7a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d19a7a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d19a7aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a81f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a81f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a81f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a81f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d19a73fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d19a73fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d19a7248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d19a3d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d19a3d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a81f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a81f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a81f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d19a3d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %isneg.i = icmp slt i32 %1, 0 # | %not.i = xor i32 %1, -1 # | %2 = select i1 %isneg.i, i32 %not.i, i32 %1 # | %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false) # | %4 = sub nuw i32 %3, 1 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rev_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %2 = call i32 @llvm.bitreverse.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rd.addr.i, align 4 # | %4 = load i32, ptr %__rs1.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rs1.addr.i, align 4 # | %4 = load i32, ptr %__rd.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false) # | ret i32 %elt.abs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function At # | ... # `---data was truncated (10240/1228637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055d328889eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d328886e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d32888a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b42f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b42f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b42f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b42f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d32881fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d32881fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3288048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3284b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3284b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b42f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b42f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b42f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3284b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (338 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558737824eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558737821e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055873782562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19aab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19aab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19aab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19aab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587377babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587377baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055873779f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055873744ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055873744eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19aab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19aab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19aab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055873744ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (339 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560ecd1f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ecd1efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ecd1f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb60649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb60649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb60631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ecd188bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ecd188a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ecd16d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ecce1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ecce1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb60632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb606330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ecce1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (340 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca < # | ... # `---data was truncated (10240/107144) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055c42bae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c42bae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c42bae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd357333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd35738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd357333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd35731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c42ba79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c42ba79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c42ba5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c42b70de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c42b70db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd35731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd35731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd35731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c42b70da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (341 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 5) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 5) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 18) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 3) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 11) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 7) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 4) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 19) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 7) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 15) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 31) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = lshr <16 x i8> %0, splat (i8 1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = lshr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = lshr <4 x i32> %0, splat (i32 10) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | ret <16 x i8> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | ret <4 x i32> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinlin # | ... # `---data was truncated (10240/66359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffc4a0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ffc4a0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ffc4a0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a2a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a2a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a2a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a2a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffc49a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ffc49a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ffc49898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ffc4638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ffc4638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a2a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a2a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a2a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffc4638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (342 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562685fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562685fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562685fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94e7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94e798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94e7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94e791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562685f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562685f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562685f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562685c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562685c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94e791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94e791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94e791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562685c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (343 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_x( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtnt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_m( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558e99f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e99f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e99f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2f8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2f84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2f8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2f8431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e99f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e99f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e99f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e99bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e99bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2f8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2f84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2f84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e99bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (344 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581faf10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581faf0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581faf1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa591f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa591f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa591f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa591f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581faea6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581faea6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581fae8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581fab3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581fab3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa591f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa591f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa591f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581fab3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (345 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_b() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_b() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560db9a9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560db9a98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560db9a9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa580e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa580ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa580e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa580e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560db9a31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560db9a31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560db9a168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560db96c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560db96c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa580e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa580e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa580e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560db96c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/18691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056423fe7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056423fe78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056423fe7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ec9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ec96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ec9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ec9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056423fe11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056423fe11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056423fdf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056423faa5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056423faa5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ec9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ec96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ec96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056423faa5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (347 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_s64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(, , , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_u64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(, , ptr, ) #4 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_u64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055789a22beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055789a228e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055789a22c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65d6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65d6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65d6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65d6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055789a1c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055789a1c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055789a1a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557899e55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557899e55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65d6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65d6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65d6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557899e55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (349 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055771789aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557717897e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055771789b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86c9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86c90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86c9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86c9031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557717830bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557717830a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577178158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577174c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577174c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86c9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86c90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86c90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577174c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (350 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056360ca80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056360ca7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056360ca8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd76933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd7698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd76933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd7691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056360ca16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056360ca16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056360c9fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056360c6aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056360c6aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd7691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd7691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd7691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056360c6aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (351 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb6fb55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb6fb52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb6fb5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c14305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c1435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c14305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c142ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb6faebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb6faeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb6fad08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb6f77fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb6f77fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c142eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c142ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c142ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb6f77fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ed36ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ed36e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ed36ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4663449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4663449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4663431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ed3681bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ed3681a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ed36668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ed3315e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ed3315b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4663432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46634330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ed3315a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/nand.c (353 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnand_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nand.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nand.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005568275eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568275e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568275ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84dbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84dbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84dbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84dbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556827582bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556827582a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568275678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556827216e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556827216b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84dbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84dbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84dbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556827216a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (354 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b83b670eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b83b66de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b83b67162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd40b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd40b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd40b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd40b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b83b606bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b83b606a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b83b5eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b83b29ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b83b29ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd40b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd40b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd40b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b83b29aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (355 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556452183eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556452180e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055645218462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe089733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe08978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe089733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe08971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556452119bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556452119a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564520fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556451dade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556451dadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe08971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe08971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe08971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556451dada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (356 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0) # | ret { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (357 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9400f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9400f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9400fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4531f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4531f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4531f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4531eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c94008fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c94008fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9400748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c93fd23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c93fd23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4531eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4531eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4531eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c93fd23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (358 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005646aad8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646aad87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646aad8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a95f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a95f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a95f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a95f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646aad20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646aad20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646aad058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646aa9b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646aa9b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a95f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a95f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a95f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646aa9b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (359 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055cff71faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cff71f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cff71fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35f5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35f538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35f5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35f531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff7190bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cff7190a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cff71758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cff6e24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cff6e24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35f531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35f531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35f531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff6e24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (360 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055705891beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557058918e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055705891c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b4241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b424725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b4241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b42403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570588b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570588b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570588968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557058545e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557058545b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b42404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b424050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b424050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557058545a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (361 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 4) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 5) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4f32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2f64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8bf16( %0, %1, i32 6) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, # | ... # `---data was truncated (10240/11061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005573030d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005573030d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005573030d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae90733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae9078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae90733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae9071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055730306dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055730306da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573030528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557302d01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557302d01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae9071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae9071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae9071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557302d01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (363 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_u8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_s8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fefe483eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fefe480e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fefe48462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f820ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f820ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f820ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f820ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fefe419bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fefe419a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fefe3fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fefe0ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fefe0adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f820ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f820ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f820ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fefe0ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (364 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562448dcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562448dcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562448dce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c45049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c450a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c45049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c45031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562448d63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562448d63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562448d488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624489f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624489f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c45032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c450330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c450330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624489f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (365 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | call void @llvm.aarch64.sve.st3.nxv16i8.p0( %6, %7, %8, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %3) # | call void @llvm.aarch64.sve.st3.nxv8i16.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %3) # | call void @llvm.aarch64.sve.st3.nxv4i32.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %3) # | call void @llvm.aarch64.sve.st3.nxv2i64.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = al # | ... # `---data was truncated (10240/58378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cb34d05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb34d02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb34d0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f915eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f915eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f915eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f915eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb34c9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb34c9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb34c808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb3492fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb3492fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f915eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f915eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f915eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb3492fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612cdb31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612cdb2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612cdb3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bc2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bc22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bc2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bc2231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612cdac7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612cdac7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612cdaac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612cd75be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612cd75bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bc2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bc22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bc22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612cd75ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (367 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | ... # `---data was truncated (10240/34217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c66d690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c66d68de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c66d69162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaa1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaa14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaa1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaa1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c66d626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c66d626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c66d60b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c66d2bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c66d2bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaa1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaa14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaa14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c66d2baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (368 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f6e4caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f6e4c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f6e4cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1114733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f111478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1114733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f111471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f6e460bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f6e460a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f6e4458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f6e0f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f6e0f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f111471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f111471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f111471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f6e0f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cac28b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cac28b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cac28b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f963aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f963aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f963aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f963aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cac2849bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cac2849a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cac282e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cac24dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cac24ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f963aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f963aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f963aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cac24dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm64-crc32.c (370 of 27910) ******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32x(i32, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3a404beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3a4048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3a404c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcc2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcc26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcc2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcc2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3a3fe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3a3fe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3a3fc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3a3c75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3a3c75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcc2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcc26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcc26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3a3c75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (371 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = and <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = and <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = and <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = and <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ef4fcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ef4fcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ef4fce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc105249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc105249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc105231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ef4f63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ef4f63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ef4f488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ef4bf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ef4bf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc105232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1052330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ef4bf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (372 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv4f32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv2f64(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005573c4c43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005573c4c40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005573c4c4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4a6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4a658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4a6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4a651b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573c4bd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005573c4bd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573c4bbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005573c486de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005573c486db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4a651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4a651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4a651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573c486da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (373 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bf969ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bf9699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bf969d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0670e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0670ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0670e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0670e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bf9632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bf9632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bf96178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bf92c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bf92c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0670e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0670e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0670e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bf92c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (374 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %p0.addr = alloca <8 x half>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <8 x half> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <8 x half>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559a7705ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a77059e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a7705d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeec11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a76ff2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a76ff2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a76fd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a76c86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a76c86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feeec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeec11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a76c86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (375 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (376 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , # | ... # `---data was truncated (10240/93119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fbb1320eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbb131de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbb132162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7894533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f789458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7894533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f789451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbb12b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbb12b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbb129b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbb0f4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbb0f4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f789451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f789451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f789451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbb0f4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (377 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005633bd7eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633bd7e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633bd7eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03cd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03cd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03cd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03cd831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633bd780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633bd780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633bd7658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633bd414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633bd414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03cd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03cd8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03cd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633bd414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (378 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_f64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr # | ... # `---data was truncated (10240/12466) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056286dd7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056286dd77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056286dd7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dcb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dcb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dcb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dcb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056286dd10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056286dd10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056286dcf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056286d9a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056286d9a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dcb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dcb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dcb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056286d9a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (379 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ca58a19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca58a16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca58a1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff765733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff76578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff765733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff76571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca589afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca589afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca589948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca58643e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca58643b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff76571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff76571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff76571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca58643a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (380 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055936f548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055936f545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055936f54962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f473b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f473b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f473b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f473b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055936f4debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055936f4dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055936f4c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055936f172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055936f172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f473b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f473b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f473b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055936f172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (381 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.i32f16( %0, %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (382 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.rbit.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.rbit.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-endianness.c (383 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-arm-none-eabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 2 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 3 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 1 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # | #0 0x0000555834268eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555834265e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055583426962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa29f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa29f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa29f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa29f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558341febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558341fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558341e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555833e92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555833e92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa29f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa29f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa29f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555833e92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (384 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b80fcabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b80fca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b80fcac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec14505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec1455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec14505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec144ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b80fc41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b80fc41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b80fc268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b80f8d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b80f8d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec144eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec144ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec144ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b80f8d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/112825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562eded9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562eded9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ededa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23f1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23f178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23f1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23f171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562eded35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562eded35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562eded1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ede9c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ede9c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23f171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23f171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23f171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ede9c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (386 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f16_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f32_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f64_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f16_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %op2.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f32_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr # | ... # `---data was truncated (10240/37349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b1fd44beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1fd448e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1fd44c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9de9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9de998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9de9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9de991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1fd3e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1fd3e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1fd3c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1fd075e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1fd075b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9de991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9de991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9de991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1fd075a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055633f658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055633f655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055633f65962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bd1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bd158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bd1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bd151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055633f5eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055633f5eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055633f5d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055633f282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055633f282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bd151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bd151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bd151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055633f282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (388 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005580875caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580875c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580875cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7366333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f736638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7366333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f736631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558087560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558087560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580875458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580871f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580871f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f736631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f736631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f736631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580871f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (389 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6f70a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6f70a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6f70aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccc3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccc36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccc3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccc3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6f703fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6f703fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6f70248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6f6cd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6f6cd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccc3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccc36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccc36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6f6cd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/dup.c (390 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f16(half noundef %op) #0 { # | entry: # | %op.addr = alloca half, align 2 # | store half %op, ptr %op.addr, align 2 # | %0 = load half, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8f16(half %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8f16(half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f32(float noundef %op) #0 { # | entry: # | %op.addr = alloca float, align 4 # | store float %op, ptr %op.addr, align 4 # | %0 = load float, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4f32(float %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4f32(float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f64(double noundef %op) #0 { # | entry: # | %op.addr = alloca double, align 8 # | store double %op, ptr %op.addr, align 8 # | %0 = load double, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2f64(double %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2f64(double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b8(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | ret %.splat # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b16(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b32(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b64(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_bf16(bfloat noundef %op) #0 { # | entry: # | %op.addr = alloca bfloat, align 2 # | store bfloat %op, ptr %op.addr, align 2 # | %0 = load bfloat, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8_z( %pg, i8 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i8, align 1 # | store %pg, ptr %pg.addr, align 2 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i8, ptr %op.addr, align 1 # | %2 = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.nxv16i8(, , i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16_z( %pg, i16 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i16, ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (391 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055abfd0f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abfd0ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abfd0f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f005bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f005bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f005bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f005bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abfd086bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abfd086a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abfd06b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abfcd1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abfcd1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f005bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f005bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f005bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abfcd1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (392 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055aa2064deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa2064ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa2064e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc9da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc9daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc9da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc9da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa205e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa205e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa205c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa20277e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa20277b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc9da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc9da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc9da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa20277a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (393 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrun_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrun.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005562f1cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562f1cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562f1cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bcd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bcd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bcd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bcd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562f1c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562f1c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562f1c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562f1906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562f1906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7bcd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bcd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bcd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562f1906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (394 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f2bc9a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2bc99de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2bc9a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8245249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82452a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8245249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8245231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2bc936bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2bc936a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2bc91b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2bc5cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2bc5cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8245232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82452330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82452330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2bc5caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (395 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a0685ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a06859e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a0685d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41d3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41d3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41d3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41d3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a067f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a067f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a067d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a06486e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a06486b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41d3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41d3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41d3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a06486a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (397 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d049656eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d049653e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d04965762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f8d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f8d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f8d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f8d4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0495ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0495eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0495d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d049280e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d049280b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f8d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f8d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f8d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d049280a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (399 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpb_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpb.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpb.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ee8491feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee8491ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee8492062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3216d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3216d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3216d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3216d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee848b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee848b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee8489a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee84549e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee84549b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3216d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3216d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3216d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee84549a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (400 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056148e5baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056148e5b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056148e5bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1197533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f119758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1197533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f119751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056148e550bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056148e550a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056148e5358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056148e1e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056148e1e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f119751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f119751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f119751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056148e1e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (401 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e703997eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e703994e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e70399862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7084849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70848a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7084849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7084831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e70392dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e70392da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7039128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7035c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7035c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7084832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70848330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70848330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7035c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (402 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556359ef7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556359ef4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556359ef862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1de441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1de44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1de441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1de4403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556359e8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556359e8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556359e728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556359b21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556359b21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1de4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1de44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1de44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556359b21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (403 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/63749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005596e2477eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596e2474e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596e247862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d7ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596e240dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596e240da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596e23f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596e20a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596e20a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596e20a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (404 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005605d6fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605d6fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605d6fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7b7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605d6f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605d6f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605d6f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605d6c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605d6c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7b7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605d6c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (405 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.abs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d823f53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d823f50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d823f5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16ee105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16ee15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16ee105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16ee0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d823ee9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d823ee9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d823ece8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d823b7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d823b7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16ee0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16ee0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16ee0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d823b7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (406 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055561698ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555616989e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055561698d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26bf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26bf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26bf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26bf031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555616922bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555616922a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556169078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556165b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556165b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f26bf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26bf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26bf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556165b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a4f6e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a4f6e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a4f6e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69f4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69f42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69f4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69f4231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a4f679bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a4f679a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a4f65e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a4f30de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a4f30db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69f4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69f42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69f42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a4f30da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (408 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmaxnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560010ea2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560010e9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560010ea362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cb8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cb838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cb8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cb831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560010e38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560010e38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560010e1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560010acce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560010accb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cb831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cb831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cb831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560010acca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a344785eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a344782e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a34478662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b48f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b48f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b48f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b48f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a34471bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a34471ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3447008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3443afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3443afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b48f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b48f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b48f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3443afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (410 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/33353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055acbda5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acbda59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acbda5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05d931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acbd9f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acbd9f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acbd9d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acbd686e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acbd686b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05d931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acbd686a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orv.c (411 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.orv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.orv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.orv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.orv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055b6ad0baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6ad0b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6ad0bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74b8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74b84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74b8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74b8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6ad050bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6ad050a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6ad0358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6acce4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6acce4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74b8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74b84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74b84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6acce4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (412 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtn.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvtn.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvtn.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_loc # | ... # `---data was truncated (10240/17734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056127432aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561274327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056127432b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d52133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d5218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d52133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d5211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612742c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612742c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612742a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561273f54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561273f54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d5211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d5211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d5211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561273f54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (413 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005637154fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637154f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637154fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3661e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3661e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3661e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3661e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563715492bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563715492a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637154778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563715126e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563715126b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3661e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3661e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3661e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563715126a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (414 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9d711eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9d711be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9d711f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37f7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37f758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37f7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37f751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9d70b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9d70b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9d70998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9d6d48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9d6d48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37f751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37f751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37f751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9d6d48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (415 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555b82f21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b82f1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b82f2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa4db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa4db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa4db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa4db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b82eb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b82eb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b82e9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b82b4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b82b4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa4db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa4db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa4db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b82b4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (416 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | d # | ... # `---data was truncated (10240/14679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fa92c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa92c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa92c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a74649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a746a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a74649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a74631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa92c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa92c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa92c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa928b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa928b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a74632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a746330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a746330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa928b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (417 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (418 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652b1a03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652b1a00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652b1a0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32bd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32bd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32bd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32bd831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652b1999bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652b1999a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652b197e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652b162de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652b162db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32bd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32bd8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32bd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652b162da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8f16.nxv4f16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16f16.nxv4f16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16f16.nxv4f16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16f16.nxv4f16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32f16.nxv4f16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32f16.nxv4f16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32f16.nxv4f16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32f16.nxv4f16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32f16.nxv4f16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32f16.nxv4f16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32f16.nxv4f16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16f16.nxv8f16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32f16.nxv8f16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32f16.nxv8f16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32f16.nxv8f16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m4_f16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32f16.nxv16f16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f32m1_f32m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 4 # | %v1.addr = alloca , align 4 # | store %v0, ptr %v0.addr, align 4 # | store %v1, ptr %v1.addr, align 4 # | %0 = load , ptr %v0.addr, align 4 # | %1 = load , ptr %v1.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( poison, %0, i64 0) # | %3 = call @llvm. # | ... # `---data was truncated (10240/593252) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7ac8c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7ac8c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7ac8c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc392e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc392ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc392e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc392e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7ac85cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7ac85ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7ac8418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7ac4f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7ac4f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc392e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc392e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc392e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7ac4f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (420 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc55f1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc55f1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc55f1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c07305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c0735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c07305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c072ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc55eb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc55eb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc55e988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc55b47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc55b47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c072eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c072ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c072ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc55b47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (421 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005645f99dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645f99d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645f99dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3e5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3e58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3e5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3e5831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645f9971bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005645f9971a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645f99568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645f9605e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645f9605b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3e5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3e58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3e58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645f9605a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (422 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056283dc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056283dc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056283dc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e21505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e2155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e21505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e214ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056283dbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056283dbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056283dbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056283d883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056283d883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e214eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e214ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e214ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056283d883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (423 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , a # | ... # `---data was truncated (10240/98149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c4b851eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c4b84ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c4b85262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cb7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cb758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cb7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cb751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c4b7e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c4b7e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c4b7cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c4b47be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c4b47bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1cb751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cb751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cb751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c4b47ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564385421eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056438541ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056438542262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b7a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643853b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643853b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056438539c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056438504be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056438504bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056438504ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (425 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, # | ... # `---data was truncated (10240/159327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556e10724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e10721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e1072562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa8cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa8cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa8cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa8caed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e106babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e106baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e1069f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e1034ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e1034eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa8caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa8caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa8caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e1034ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (426 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005564d6566eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564d6563e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564d656762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfb8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfb80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfb8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfb8031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564d64fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564d64fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564d64e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564d6190e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564d6190b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfb8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfb80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfb80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564d6190a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (427 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_u8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s16_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e326beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646e3268e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646e326c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf77b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf77b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf77b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf77b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e3201bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646e3201a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646e31e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646e2e95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646e2e95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf77b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf77b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf77b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e2e95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (429 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5c6f62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5c6f5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5c6f6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa318a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa318aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa318a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa318a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5c6ef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5c6ef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5c6edd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5c6b8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5c6b8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa318a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa318a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa318a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5c6b8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (430 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @foo() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @bar() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @baz(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @quux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %call = call target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %0) # | ret target("riscv.vector.tuple", , 2) %call # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055933b57beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055933b578e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055933b57c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb509333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb50938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb509333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb50931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055933b511bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055933b511a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055933b4f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055933b1a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055933b1a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb50931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb50931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb50931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055933b1a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603421feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603421fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603421ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5659849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5659849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5659831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560342194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560342194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603421798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560341e28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560341e28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5659832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56598330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560341e28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (432 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 0 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f65d291eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f65d28ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f65d29262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad7f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad7f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad7f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad7f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65d227bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f65d227a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f65d20c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f65cebbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f65cebbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad7f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad7f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad7f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65cebba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (433 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005639ed066eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639ed063e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639ed06762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e3d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e3d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e3d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e3d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639ecffcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639ecffca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639ecfe18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639ecc90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639ecc90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e3d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e3d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e3d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639ecc90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (434 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564479194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564479191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056447919562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5589d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5589d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5589d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5589d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056447912abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056447912aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056447910f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564478dbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564478dbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5589d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5589d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5589d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564478dbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (435 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (436 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (437 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcfc2cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcfc2c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcfc2cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb22ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb22ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb22ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb22ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcfc261bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcfc261a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcfc2468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcfbef5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcfbef5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb22ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb22ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb22ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcfbef5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbd0c60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbd0c5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbd0c6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd90de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd90dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd90de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd90de31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbd0bf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbd0bf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbd0bdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbd088ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbd088ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd90de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd90de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd90de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbd088aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (441 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b00563eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b00560e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b0056462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11b281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11b28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11b281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11b2803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b004f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b004f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b004de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b0018de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b0018db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f11b2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11b28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11b28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b0018da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (442 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565242113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565242110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056524211462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafe9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafe918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafe9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafe911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652420a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652420a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056524208e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565241d3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565241d3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fafe911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafe911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafe911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565241d3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f239b69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f239b66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f239b6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa749d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa749d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa749d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa749d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f239affbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f239affa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f239ae48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f239793e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f239793b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa749d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa749d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa749d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f239793a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (445 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_3_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555cf38c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cf38c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cf38c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d7bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d7bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d7bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d7bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cf385abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cf385aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cf383f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cf34eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cf34eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d7bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d7bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d7bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cf34eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (446 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x half>, align 16 # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca <32 x half>, align 16 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %b.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store <32 x half> %b, ptr %b.addr, align 16 # | %0 = load <32 x ha # | ... # `---data was truncated (10240/161192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000563830f5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563830f59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563830f5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda51733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda5178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda51733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda5171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563830ef2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563830ef2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563830ed78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563830b86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563830b86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda5171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda5171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda5171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563830b86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (447 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (448 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055f518198eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f518195e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f51819962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb6cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb6cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb6cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb6cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f51812ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f51812ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5181138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f517dc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f517dc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb6cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb6cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb6cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f517dc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (450 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv16i8(, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8i16(, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4i32(, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f16( %op1, half noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8f16( %0, half %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8f16(, half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f32( %op1, float noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4f32( %0, float %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4f32(, float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f64( %op1, double noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load double, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2f64( %0, double %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2f64(, double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_bf16( %op1, bfloat noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8bf16( %0, bfloat %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8bf16(, bfloat) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556fd797eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fd797be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fd797f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ff4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ff48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ff4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ff4831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fd7914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fd7914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fd78f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fd75a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fd75a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ff4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ff48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ff48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fd75a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (451 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596bea3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596bea37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596bea3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4501449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45014a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4501449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4501431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596be9d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596be9d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596be9b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596be664e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596be664b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4501432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45014330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45014330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596be664a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = c # | ... # `---data was truncated (10240/41433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a04cf78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a04cf75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a04cf7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd320449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd320449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd320431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a04cf0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a04cf0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a04cef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a04cba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a04cba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd320432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3204330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a04cba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (453 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_0( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_1( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556c5512aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c55127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c5512b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd700c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd700ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd700c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd700c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c550c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c550c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c550a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c54d54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c54d54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd700c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd700c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd700c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c54d54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (454 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb54847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb54844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb5484862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4757b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4757b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4757b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4757b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb547ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb547dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb547c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb54471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb54471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4757b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4757b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4757b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb54471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (455 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c567666eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c567663e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c56766762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bc3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bc3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bc3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bc3eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5675fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5675fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5675e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c567290e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c567290b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bc3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bc3eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bc3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c567290a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (456 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i) # | %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8> # | store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i) # | %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8> # | store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i) # | %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8> # | store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i) # | %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8> # | store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d07c732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d07c72fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d07c73362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f971f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f971f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f971f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f971f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d07c6c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d07c6c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d07c6ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d07c35ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d07c35cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f971f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f971f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f971f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d07c35ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (457 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005627100b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627100ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627100b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f351ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f351aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f351ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f351ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562710046bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562710046a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056271002b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056270fcdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056270fcdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f351ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f351ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f351ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056270fcdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (458 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/11908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d093bb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d093bb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d093bb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5506849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55068a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5506849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5506831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d093b4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d093b4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d093b2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0937dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0937deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5506832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55068330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55068330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0937dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (459 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4c57cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4c57cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4c57d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93f3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93f338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93f3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93f331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4c5765bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4c5765a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4c574a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4c53f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4c53f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93f331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93f331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93f331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4c53f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (460 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 # | ... # `---data was truncated (10240/32186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596feee5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596feee2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596feee662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff642c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff642ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff642c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff642c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596fee7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596fee7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596fee608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596feb0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596feb0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff642c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff642c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff642c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596feb0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (462 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561aa3b09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561aa3b06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561aa3b0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ea5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ea598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ea5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ea591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561aa3a9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561aa3a9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561aa3a848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561aa3733e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561aa3733b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ea591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ea591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ea591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561aa3733a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (463 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ee35b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ee35b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ee35b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cffe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cffe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cffe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cffe03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ee354cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ee354ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ee35318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ee31e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ee31e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cffe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cffe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cffe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ee31e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (464 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsm # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2ac94deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2ac94ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2ac94e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f559f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f559f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f559f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f559f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2ac8e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2ac8e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2ac8c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2ac577e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2ac577b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f559f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f559f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f559f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2ac577a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (465 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (466 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Fu # | ... # `---data was truncated (10240/68429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f100043eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f100040e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f10004462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffadcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffadcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffadcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffadcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0fffd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0fffd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0fffbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0ffc6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0ffc6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffadcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffadcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffadcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0ffc6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (468 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585ffa1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585ffa18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585ffa1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9568c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9568ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9568c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9568c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585ff9b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585ff9b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585ff9968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585ff645e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585ff645b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9568c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9568c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9568c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585ff645a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (470 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store # | ... # `---data was truncated (10240/17826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005608849bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608849bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608849be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34a831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560884953bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560884953a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608849388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608845e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608845e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34a831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608845e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056207fcbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056207fcb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056207fcbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b34849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b34849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b34831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056207fc50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056207fc50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056207fc358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056207f8e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056207f8e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b34832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b348330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056207f8e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (473 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_bf16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_f16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnb_f8_f32( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtnb.nxv4f32( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_f8_f32( %zd, %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zd.addr = alloca , align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store %zd, ptr %zd.addr, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load , ptr %zd.addr, align 16 # | %3 = load { , }, ptr %zn_zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | %7 = call @llvm.aarch64.sve.fp8.cvtnt.nxv4f32( %2, %4, %5) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055741d6aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055741d6a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055741d6ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc436449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc436449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc436431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055741d640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055741d640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055741d6258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055741d2d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055741d2d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc436432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055741d2d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (474 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac8ce9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac8ce99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac8ce9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbafdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbafdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbafdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbafdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac8ce32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac8ce32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac8ce178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac8cac6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac8cac6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbafdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbafdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbafdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac8cac6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (475 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a0b048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a0b045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a0b04962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f852ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f852aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f852ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f852ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a0afdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a0afdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a0afc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a0ac72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a0ac72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f852ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f852ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f852ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a0ac72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (476 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d6b0bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d6b0b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d6b0bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a28933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a2898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a28933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a2891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d6b051bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d6b051a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d6b0368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d6ace5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d6ace5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a2891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a2891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a2891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d6ace5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (477 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ca3b7faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca3b7f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca3b7fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ab8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ab8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ab8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ab8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca3b790bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca3b790a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca3b7758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca3b424e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca3b424b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ab8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ab8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ab8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca3b424a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0927a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0927a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0927aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2033933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f203398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2033933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f203391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a09273fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a09273fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0927248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0923d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0923d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f203391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f203391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f203391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0923d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (479 of 27910) ******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x half> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x float> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x double> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x bfloat> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bc4873beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc48738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc4873c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f303a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f303a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f303a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f303a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc486d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc486d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc486b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc48365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc48365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f303a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f303a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f303a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc48365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (480 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalb_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f168e8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f168e8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f168e9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7632333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f763238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7632333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f763231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f168e25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f168e25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f168e0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f168ab9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f168ab9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f763231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f763231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f763231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f168ab9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (481 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (482 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564b29e17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b29e14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b29e1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0536a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0536aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0536a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0536a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b29dadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b29dada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b29d928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b29a41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b29a41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0536a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0536a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0536a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b29a41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (483 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (484 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (485 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align # | ... # `---data was truncated (10240/127452) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c42e0d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c42e0d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c42e0d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12e0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12e055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12e0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12e04ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c42e06ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c42e06ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c42e0538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c42dd02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c42dd02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f12e04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12e04ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12e04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c42dd02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (487 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue # | ... # `---data was truncated (10240/21007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561824f15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561824f12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561824f1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9837449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98374a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9837449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9837431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561824eabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561824eaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561824e908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561824b3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561824b3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9837432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98374330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98374330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561824b3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (488 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (489 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e1cce0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1cce09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1cce0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccd2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccd26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccd2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccd2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1ccda2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1ccda2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1ccd878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1cca36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1cca36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccd2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccd26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccd26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1cca36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (490 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i) # | store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i) # | store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i) # | store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i) # | store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i) # | store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i) # | store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i) # | store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i) # | store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vrndns_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vrndn.i = call float @llvm.roundeven.f32(float %1) # | store float %vrndn.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i) # | store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndm.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i) # | store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i) # | store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a # | ... # `---data was truncated (10240/29785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d18ca07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d18ca04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d18ca0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd723705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd723705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7236ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d18c99dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d18c99da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d18c9828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d18c631e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d18c631b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7236eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7236ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7236ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d18c631a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (491 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/75656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000558c2ccb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c2ccb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c2ccb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1418649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14186a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1418649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1418631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c2cc49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c2cc49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c2cc2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c2c8dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c2c8ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1418632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14186330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14186330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c2c8dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (492 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a9b44c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9b44c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9b44c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39d111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9b445abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9b445aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9b443f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9b40eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9b40eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39d111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9b40eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6a3be8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6a3be5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6a3be962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cfd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cfd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cfd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cfd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6a3b7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6a3b7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6a3b638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6a3812e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6a3812b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cfd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cfd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cfd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6a3812a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (494 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pnext.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv8i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv8i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv4i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv4i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv2i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv2i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005637b6128eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637b6125e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637b612962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01b2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637b60bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637b60bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637b60a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637b5d52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637b5d52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01b2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637b5d52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (495 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr.i = alloca bfloat, align 2 # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | store bfloat %0, ptr %bf.addr.i, align 2 # | %1 = load bfloat, ptr %bf.addr.i, align 2 # | %2 = fpext bfloat %1 to float # | ret float %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr.i = alloca float, align 4 # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | store float %0, ptr %sf.addr.i, align 4 # | %1 = load float, ptr %sf.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | ret bfloat %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f36629aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f366297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f36629b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc9cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc9cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc9cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc9cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f366230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f366230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3662158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f365ec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f365ec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc9cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc9cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc9cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f365ec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (496 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <4 x bfloat>, ptr %__promote, align 8 # | store <4 x bfloat> %1, ptr %__ret, align 8 # | %2 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %2, ptr %tmp, align 8 # | %3 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x bfloat>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %low.addr = alloca <4 x bfloat>, align 8 # | %high.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %low, ptr %low.addr, align 8 # | store <4 x bfloat> %high, ptr %high.addr, align 8 # | %0 = load <4 x bfloat>, ptr %low.addr, align 8 # | %1 = load <4 x bfloat>, ptr %high.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <4 x bfloat>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store bfloat %a, ptr %a.addr, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1, align 8 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x bfloat>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | store bfloat %a, ptr %a.addr, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1, align 16 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | ret <8 x bfloat> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b6b897deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6b897ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6b897e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb97e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb97ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb97e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb97e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6b8913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6b8913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6b88f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6b85a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6b85a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb97e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb97e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb97e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6b85a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (497 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | % # | ... # `---data was truncated (10240/74176) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005653c4e9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653c4e9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653c4e9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17ecb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17ecb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17ecb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17ecaed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653c4e34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653c4e34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653c4e198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653c4ac8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653c4ac8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17ecaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17ecaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17ecaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653c4ac8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597015ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597015dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597015de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e73049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e730a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e73049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e73031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559701573bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559701573a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597015588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559701207e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559701207b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e73032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e730330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e730330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559701207a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (499 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556ff8189eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ff8186e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ff818a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b60b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b60b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b60b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b60b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ff811fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ff811fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ff81048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ff7db3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ff7db3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b60b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b60b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b60b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ff7db3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cff1db4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cff1db1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cff1db562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b13733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b1378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b13733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b1371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff1d4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cff1d4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cff1d2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cff19dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cff19deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b1371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b1371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b1371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff19dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (501 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055de4c38feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de4c38ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de4c39062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aa1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aa178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aa1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aa171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de4c325bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de4c325a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de4c30a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de4bfb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de4bfb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0aa171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aa171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aa171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de4bfb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (502 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564d95f8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d95f89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d95f8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd17c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd17c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd17c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd17c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d95f22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d95f22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d95f078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d95bb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d95bb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd17c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd17c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd17c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d95bb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a13a259eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a13a256e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a13a25a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96bbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96bbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96bbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96bbaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a13a1efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a13a1efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a13a1d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a139e83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a139e83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96bbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96bbaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96bbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a139e83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (504 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/101483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d16fc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d16fbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d16fc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb86bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb86bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb86bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb86bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d16f57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d16f57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d16f3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d16bebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d16bebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb86bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb86bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb86bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d16beba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (505 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16() #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055821319aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558213197e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055821319b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06f8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06f815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06f8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06f80ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558213130bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558213130a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582131158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558212dc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558212dc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06f80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06f80ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06f80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558212dc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (506 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596a8188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596a8185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596a818962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f29b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f29b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f29b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f29b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596a811ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596a811ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596a81038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596a7db2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596a7db2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f29b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f29b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f29b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596a7db2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (507 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 0) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_1() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 1) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_2() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 2) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_3() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 3) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_4() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 4) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_5() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 5) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_6() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 6) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_7() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 7) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 8) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_9() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 9) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_10() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_11() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_12() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 12) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_13() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 13) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_14() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 29) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_15() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 30) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 1) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 2) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558d25554eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d25551e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d2555562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8264133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f826418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8264133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f826411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d254eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d254eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d254cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d2517ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d2517eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f826411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f826411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f826411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d2517ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (508 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b3656ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b36569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b3656d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37c6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37c60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37c6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37c6031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b36502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b36502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b364e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b36196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b36196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37c6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37c60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37c60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b36196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (509 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e87b69deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e87b69ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e87b69e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96c041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96c04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96c041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96c0403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e87b633bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e87b633a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e87b6188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e87b2c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e87b2c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96c0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96c04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96c04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e87b2c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (510 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %5 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %5, ptr %__ret, align 8 # | %6 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %6, ptr %tmp, align 8 # | %7 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3 # | %5 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4 # | %6 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5 # | %7 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6 # | %8 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %9 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_39 = alloca <4 x half>, align 8 # | %__s0_39 = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_39, align 8 # | %1 = load <4 x half>, ptr %__s0_39, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_39, align 8 # | %7 = load <4 x half>, ptr %__ret_39, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_20 = alloca <8 x half>, align 16 # | %__s0_20 = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_20, align 8 # | %1 = load <4 x half>, ptr %__s0_20, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_20, align 16 # | %7 = load <8 x half>, ptr %__ret_20, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_432 = alloca <4 x half>, align 8 # | %__s0_432 = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_432, align 16 # | %1 = load <8 x half>, ptr %__s0_432, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_432, align 8 # | %7 = load <4 x half>, ptr %__ret_432, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_408 = alloca <8 x half>, align 16 # | %__s0_408 = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_408, align 16 # | %1 = load <8 x half>, ptr %__s0_408, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_408, align 16 # | %7 = load <8 x half>, ptr %__ret_408, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <4 x half>, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <4 x half> %vec, ptr %vec.addr, align 8 # | %0 = load <4 x half>, ptr %vec.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x half> %1, i32 3 # | store half %vget_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <8 x half>, align 16 # | %__ret = alloca half, align 2 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <8 x half> %vec, ptr %vec.addr, align 16 # | %0 = load <8 x half>, ptr %vec.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x half> %1, i32 7 # | store half %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-s # | ... # `---data was truncated (10240/10414) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561e3e70ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e3e709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e3e70d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9814d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9814d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9814d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9814d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e3e6a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e3e6a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e3e6878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e3e336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e3e336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9814d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9814d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9814d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e3e336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (511 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4b8c3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4b8c39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4b8c3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcf6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcf6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcf6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcf6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4b8bd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4b8bd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4b8bb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4b8866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4b8866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdcf6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcf6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcf6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4b8866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (512 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (513 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x0000556808a36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556808a33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556808a3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1b6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1b678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1b6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1b671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568089ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568089cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568089b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556808660e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556808660b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1b671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1b671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1b671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556808660a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (514 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (515 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055d126d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d126d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d126d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bcba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bcba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bcba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bcba03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d126d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d126d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d126cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1269a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1269a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bcba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bcba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bcba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1269a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (516 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, , , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | ... # `---data was truncated (10240/24605) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a655738eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a655735e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a65573962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe37c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe37c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe37c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe37c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6556cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6556cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6556b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a655362e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a655362b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe37c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe37c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe37c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a655362a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (517 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (518 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (519 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b33ae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b33ae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b33aea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f676f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f676f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f676f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f676f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b33a7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b33a7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b33a648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b33713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b33713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f676f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f676f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f676f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b33713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (520 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (521 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621db600eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621db5fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621db60162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe135533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe13558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe135533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe13551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621db596bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621db596a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621db57b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621db22ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621db22ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe13551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe13551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe13551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621db22aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (522 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a8e047eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a8e044e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a8e04862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe9e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe9e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe9e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe9e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a8dfddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a8dfdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a8dfc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a8dc71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a8dc71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe9e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe9e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe9e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a8dc71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (523 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, % # | ... # `---data was truncated (10240/93831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a576487eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a576484e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a57648862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d84733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d8478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d84733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d8471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a57641dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a57641da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5764028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5760b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5760b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d8471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d8471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d8471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5760b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (524 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm # | ... # `---data was truncated (10240/24404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561cd3f85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cd3f82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cd3f8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc191533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc19158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc191533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc19151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cd3f1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cd3f1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cd3f008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cd3bafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cd3bafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc19151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc19151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc19151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cd3bafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (525 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564ff05efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ff05ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ff05f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f87249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f872a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f87249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f87231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ff0585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ff0585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ff056a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ff0219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ff0219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f87232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f872330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f872330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ff0219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (526 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562dd11e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562dd11dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562dd11e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff5c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff5c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff5c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff5c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dd1177bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562dd1177a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562dd115c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562dd0e0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562dd0e0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff5c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff5c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff5c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dd0e0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (527 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 1) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 3) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 7) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (528 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z_1( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 270) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv2f64(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.ad # | ... # `---data was truncated (10240/12234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bb314eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb314e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb314ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7f8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7f895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7f8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7f88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb31482bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb31482a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb314678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb31116e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb31116b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7f88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7f88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7f88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb31116a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (530 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e941ef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e941eefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e941ef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f983fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f983fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f983fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f983fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e941e88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e941e88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e941e6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e941b1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e941b1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f983fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f983fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f983fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e941b1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (531 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055591228deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055591228ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055591228e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f982b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f982b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f982b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f982b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555912223bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555912223a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559122088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555911eb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555911eb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f982b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f982b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f982b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555911eb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (532 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055646ff65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055646ff62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055646ff6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d7ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d7ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d7ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d7ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055646fefbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055646fefba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055646fee08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055646fb8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055646fb8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d7ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d7ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d7ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055646fb8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (533 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558c3950feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c3950ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c3951062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e5911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c394a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c394a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c3948a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c39139e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c39139b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e5911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c39139a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (534 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f1c06a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1c069ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1c06a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc268a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc268aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc268a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc268a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1c0637bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1c0637a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1c061c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1c02cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1c02cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc268a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc268a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc268a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1c02cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (535 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056309b15beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056309b158e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056309b15c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd1f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd1f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd1f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd1f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056309b0f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056309b0f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056309b0d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056309ad85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056309ad85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd1f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd1f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd1f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056309ad85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (536 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_int16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_uint16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_int32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_uint32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_int64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_uint64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @subscript_float16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @subscript_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @subscript_float64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecins = insertelement %1, float 1.000000e+00, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %2 = load , ptr %a.addr, align 16 # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_read_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecext = extractelement %1, i64 %0 # | %add = fadd float %vecext, 1.000000e+00 # | %2 = load , ptr %a.addr, align 16 # | %vecins = insertelement %2, float %add, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %3 = load , ptr %a.addr, align 16 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055e7f89d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7f89d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7f89d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e99249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e99249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e99231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f896dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7f896da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7f89528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7f8601e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7f8601b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e99232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e992330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f8601a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (537 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6c9ed3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6c9ed0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6c9ed462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dbc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dbc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dbc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dbc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6c9e69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6c9e69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6c9e4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e6c9afde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e6c9afdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dbc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dbc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dbc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6c9afda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (538 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %b # | ... # `---data was truncated (10240/22231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a1b20e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1b20e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1b20e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcd2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcd278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcd2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcd271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1b207dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1b207da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1b20628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1b1d11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1b1d11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcd271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcd271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcd271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1b1d11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (539 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f32( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (540 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local signext i32 @test() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0) # | %conv = trunc i64 %0 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbfb7a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbfb79ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbfb7a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34c4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34c418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34c4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34c411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbfb737bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbfb737a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbfb71c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbfb3cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbfb3cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34c411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34c411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34c411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbfb3cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (541 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (542 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e22c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e22c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e22c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb70f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb70f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb70f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb70f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e22bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e22bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e22ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e22854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e22854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb70f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb70f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb70f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e22854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (543 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c9d2cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c9d2c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c9d2cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe41b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe41b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe41b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe41b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c9d261bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c9d261a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c9d2468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c9cef5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c9cef5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe41b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe41b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe41b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c9cef5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (544 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64 # | ... # `---data was truncated (10240/97248) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ce1debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ce1de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ce1dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6694449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6694449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6694431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ce1d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ce1d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ce1d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ce1a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ce1a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6694432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66944330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ce1a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (545 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569bcc96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569bcc93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569bcc9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf04733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf0478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf04733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf0471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569bcc2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569bcc2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569bcc118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569bc8c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569bc8c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf0471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf0471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf0471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569bc8c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (546 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f229dc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f229dbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f229dc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3a9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3a9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3a9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3a9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f229d56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f229d56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f229d3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2299eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2299eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff3a9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3a9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3a9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2299eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (548 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (549 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056483b384eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056483b381e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056483b38562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81d6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81d6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81d6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81d6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056483b31abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056483b31aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056483b2ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056483afaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056483afaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81d6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81d6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81d6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056483afaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (550 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (551 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e17008deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e17008ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e17008e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57ebf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57ebf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57ebf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57ebeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e170023bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e170023a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1700088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e16fcb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e16fcb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f57ebeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57ebeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57ebeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e16fcb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (552 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574852cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574852c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574852cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74a1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74a1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74a1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74a1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557485261bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557485261a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574852468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557484ef5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557484ef5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74a1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74a1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74a1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557484ef5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (553 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df62952eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df6294fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df6295362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8a5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8a58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8a5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8a5831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df628e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df628e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df628cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df6257ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df6257cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8a5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8a58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8a58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df6257ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (554 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e6f7c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e6f7c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e6f7c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a51933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a5198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a51933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a5191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e6f75cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e6f75ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e6f7418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e6f3f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e6f3f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a5191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a5191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a5191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e6f3f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (555 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vf # | ... # `---data was truncated (10240/117019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609ff006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609ff003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609ff00762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c63a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c63aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c63a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c63a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609fef9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609fef9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609fef818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609fec30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609fec30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c63a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c63a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c63a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609fec30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test # | ... # `---data was truncated (10240/156773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8fb4daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8fb4d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8fb4db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5132133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f513218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5132133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f513211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8fb470bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8fb470a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8fb4558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8fb104e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8fb104b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f513211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f513211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f513211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8fb104a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (557 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (558 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000056042e601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056042e5fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056042e60262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3db8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3db8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3db8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3db8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056042e597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056042e597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056042e57c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056042e22be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056042e22bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3db8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3db8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3db8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056042e22ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (559 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (560 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8b1ab3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8b1ab0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8b1ab462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feece21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feece2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feece21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feece203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8b1a49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8b1a49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8b1a2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8b16dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8b16ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feece204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feece2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feece2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8b16dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (561 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625b61d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625b61d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625b61d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efec8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efec818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efec8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efec811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625b616ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625b616ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625b61538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625b5e02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625b5e02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efec811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efec811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efec811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625b5e02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (562 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056035a54feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056035a54ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056035a55062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9359649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93596a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9359649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9359631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056035a4e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056035a4e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056035a4ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056035a179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056035a179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9359632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93596330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93596330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056035a179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (564 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d737f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d737f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d737f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b08e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b08ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b08e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b08e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d7378abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d7378aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d7376f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d7341ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d7341eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b08e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b08e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b08e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d7341ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (565 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %3, ptr %__ret.i, align 8 # | %4 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %3, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005565a43aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565a43a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565a43ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f214d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f214d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f214d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f214d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565a4340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565a4340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565a43258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565a3fd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565a3fd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f214d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f214d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f214d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565a3fd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (566 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/94149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644470b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644470b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644470b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4001c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4001ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4001c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4001c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056444704cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056444704ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644470318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564446ce0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564446ce0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4001c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4001c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4001c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564446ce0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (567 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005654b32b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654b32b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654b32b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98b7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98b7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98b7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98b7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654b324abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654b324aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654b322f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654b2edee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654b2edeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98b7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98b7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98b7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654b2edea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a359b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a359b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a359b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc04f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc04f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc04f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc04f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a3594dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a3594da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a359328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a355e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a355e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc04f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc04f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc04f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a355e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (569 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d67708feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d67708ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d67709062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee9db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee9db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee9db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee9db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d677025bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d677025a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d67700a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d676cb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d676cb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee9db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee9db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee9db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d676cb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (570 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf0e62feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf0e62ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf0e63062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc01d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc01d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc01d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc01d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf0e5c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf0e5c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf0e5aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf0e259e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf0e259b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc01d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc01d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc01d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf0e259a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (571 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8fbd6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8fbd6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8fbd6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f471f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f471f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f471f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f471f803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8fbd04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8fbd04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8fbce98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8fb998e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8fb998b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f471f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f471f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f471f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8fb998a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (572 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e82aab1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e82aaaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e82aab262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff882733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff88278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff882733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff88271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e82aa47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e82aa47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e82aa2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e82a6dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e82a6dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff88271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff88271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff88271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e82a6dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (573 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7f9617eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7f9614e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7f961862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a0cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a0cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f95adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7f95ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7f95928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7f9241e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7f9241b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a0cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f9241a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561868602eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618685ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056186860362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f028e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f028e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f028e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f028e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561868598bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561868598a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056186857d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056186822ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056186822cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f028e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f028e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f028e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056186822ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (575 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (576 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562941fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562941fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562941fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef0203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562941f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562941f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562941f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562941c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562941c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbef0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562941c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (577 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556904c84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556904c81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556904c8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe125305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe12535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe125305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1252ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556904c1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556904c1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556904bff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569048aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569048aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1252eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1252ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1252ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569048aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (578 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %.splat, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sudot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d4d9423eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4d9420e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4d942462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe969249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9692a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe969249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe969231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4d93b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4d93b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4d939e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4d904de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4d904db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe969232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9692330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9692330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4d904da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (579 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005630780daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630780d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630780db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f865721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86572725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f865721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8657203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563078070bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563078070a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630780558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563077d04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563077d04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8657204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86572050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86572050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563077d04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (580 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620fe544eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620fe541e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620fe54562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c3381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c338725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c3381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c33803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620fe4dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620fe4daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620fe4bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620fe16ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620fe16eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c33804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c338050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c338050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620fe16ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (581 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c676111eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c67610ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c67611262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe999305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe99935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe999305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9992ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6760a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6760a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c67608c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c675d3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c675d3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9992eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9992ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9992ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c675d3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (582 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (583 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1 # | ... # `---data was truncated (10240/26476) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c33c8d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c33c8d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c33c8d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79e1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79e138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79e1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79e131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c33c86ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c33c86ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c33c8538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c33c502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c33c502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f79e131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79e131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79e131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c33c502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (584 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, pt # | ... # `---data was truncated (10240/79679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dedaf95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dedaf92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dedaf9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8a4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8a4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8a4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8a4e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dedaf2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dedaf2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dedaf108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dedabbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dedabbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8a4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8a4e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8a4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dedabbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (585 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <8 x i8>, al # | ... # `---data was truncated (10240/26059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e248322eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e24831fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e24832362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90a6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90a6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90a6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90a6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2482b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2482b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e24829d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e247f4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e247f4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90a6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90a6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90a6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e247f4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (586 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f77c0cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f77c0cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f77c0d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6624933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f662498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6624933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f662491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f77c065bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f77c065a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f77c04a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f77bcf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f77bcf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f662491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f662491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f662491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f77bcf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563018464eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563018461e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056301846562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0df561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0df56725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0df561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0df5603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630183fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630183faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630183df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056301808ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056301808eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0df5604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0df56050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0df56050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056301808ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (590 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfcec84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfcec81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfcec8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd36533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd3658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd36533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd3651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfcec1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfcec1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfcebff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfce8aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfce8aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd3651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd3651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd3651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfce8aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (591 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627c1723eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627c1720e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627c172462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ec9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ec918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ec9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ec911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627c16b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627c16b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627c169e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627c134de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627c134db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ec911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ec911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ec911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627c134da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (592 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 13, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 29, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056138352deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056138352ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056138352e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f49c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f49ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f49c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f49c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613834c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613834c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613834a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561383157e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561383157b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f49c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f49c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f49c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561383157a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (593 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (594 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055986d99eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055986d99be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055986d99f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3903133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f390318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3903133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f390311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055986d934bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055986d934a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055986d9198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055986d5c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055986d5c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f390311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f390311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f390311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055986d5c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (595 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056195db52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056195db4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056195db5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e67849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e67849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e67831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056195dae8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056195dae8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056195dacd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056195d77ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056195d77cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e67832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e678330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056195d77ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (596 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621d1353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621d1350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621d135462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc86e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc86ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc86e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc86e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621d12e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621d12e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621d12ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621d0f7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621d0f7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc86e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc86e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc86e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621d0f7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (597 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583dfea6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583dfea3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583dfea762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2050533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f205058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2050533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f205051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583dfe3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583dfe3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583dfe218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583dfad0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583dfad0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f205051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f205051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f205051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583dfad0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (598 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc76924eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc76921e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc7692562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5444333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f544438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5444333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f544431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc768babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc768baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc7689f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc7654ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc7654eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f544431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f544431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f544431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc7654ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (600 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d085b55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d085b52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d085b5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3493449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34934a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3493449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3493431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d085aebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d085aeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d085ad08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d08577fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d08577fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3493432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34934330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34934330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d08577fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (601 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056541577eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056541577be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056541577f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8887a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8887aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8887a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8887a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565415714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565415714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654156f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654153a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654153a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8887a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8887a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8887a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654153a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (602 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/246606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f026cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f026cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f026d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e78449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e78449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e78431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f02665bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f02665a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f0264a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f022f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f022f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e78432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e784330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f022f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willre # | ... # `---data was truncated (10240/273697) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583c61afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583c61ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583c61b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff43bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff43bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff43bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff43beed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583c6145bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583c6145a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583c612a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583c5dd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583c5dd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff43beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff43beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff43beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583c5dd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557efeff0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557efefede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557efeff162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4c2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4c24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4c2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4c2431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557efef86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557efef86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557efef6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557efec1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557efec1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4c2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4c24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4c24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557efec1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (605 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac14ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bac14fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bac150062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a32e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a32ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a32e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a32e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac1495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bac1495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bac147a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bac1129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bac1129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a32e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a32e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a32e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac1129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (607 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_0( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_1( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ca67375eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca67372e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca6737662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe40ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe40caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe40ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe40ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca6730bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca6730ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca672f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca66f9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca66f9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe40ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe40ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe40ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca66f9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af4334deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af4334ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af4334e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc673449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc673449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc673431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af432e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af432e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af432c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af42f77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af42f77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc673432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6734330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af42f77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc3eb96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc3eb93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc3eb9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f449a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f449a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f449a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f449a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc3eb2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc3eb2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc3eb118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc3e7c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc3e7c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f449a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f449a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f449a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc3e7c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (610 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (611 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (612 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560b959efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b959ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b959f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0930249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09302a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0930249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0930231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b95985bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b95985a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b9596a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b95619e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b95619b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0930232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09302330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09302330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b95619a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (614 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577bbc4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577bbc49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577bbc4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b6cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b6cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b6cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b6cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577bbbe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577bbbe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577bbbc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577bb876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577bb876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b6cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b6cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b6cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577bb876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (615 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056059f528eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056059f525e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056059f52962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ab2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ab24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ab2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ab2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056059f4bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056059f4bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056059f4a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056059f152e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056059f152b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ab2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ab24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ab24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056059f152a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (617 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, a # | ... # `---data was truncated (10240/43486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb4163beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb41638e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb4163c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5847333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f584738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5847333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f584731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb415d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb415d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb415b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb41265e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb41265b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f584731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f584731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f584731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb41265a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a0a759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a0a756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a0a75a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f6c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f6c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f6c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f6c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a0a6efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a0a6efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a0a6d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a0a383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a0a383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f6c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f6c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f6c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a0a383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (620 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (621 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056417b079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056417b076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056417b07a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff67f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff67f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff67f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff67f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056417b00fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056417b00fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056417aff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056417aca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056417aca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff67f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff67f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff67f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056417aca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (622 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfalse_b() #0 { # | entry: # | ret zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000562bae92beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bae928e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bae92c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbde849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbde8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbde849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbde831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bae8c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bae8c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bae8a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bae555e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bae555b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbde832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbde8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbde8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bae555a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f5b318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f5b315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f5b31962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c2f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c2f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c2f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c2f631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f5b2aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f5b2aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f5b2938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f5af42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f5af42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c2f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c2f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c2f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f5af42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (624 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> # | %fmla = bitcast <16 x i8> %4 to <8 x half> # | %fmla1 = bitcast <16 x i8> %3 to <8 x half> # | %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %fmla2, ptr %ref.tmp, align 16 # | %7 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %7, ptr %__ret, align 16 # | %8 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %8, ptr %tmp, align 16 # | %9 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp, align 8 # | %10 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %10, ptr %__ret, align 8 # | %11 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %11, ptr %tmp, align 8 # | %12 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 # | ... # `---data was truncated (10240/13273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005635daacdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635daacae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635daace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99ac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99ac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99ac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99ac831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635daa63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635daa63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635daa488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635da6f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635da6f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99ac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99ac8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99ac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635da6f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (625 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d58b46aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d58b467e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d58b46b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe633f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe633f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe633f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe633f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d58b400bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d58b400a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d58b3e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d58b094e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d58b094b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe633f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe633f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe633f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d58b094a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (626 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a8a376eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a8a373e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a8a37762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5cd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5cd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5cd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5cd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a8a30cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a8a30ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a8a2f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a89fa0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a89fa0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff5cd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5cd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5cd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a89fa0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (627 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca # | ... # `---data was truncated (10240/153805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624e03afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624e03ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624e03b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6d9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6d995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6d9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6d98ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624e0345bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624e0345a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624e032a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624dffd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624dffd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6d98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6d98ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6d98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624dffd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (628 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv8f16(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b2ca54aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2ca547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2ca54b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b93249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b932a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b93249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b93231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2ca4e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2ca4e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2ca4c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2ca174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2ca174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b93232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b932330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b932330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2ca174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (629 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a57b6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a57b6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a57b7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f944f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f944f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f944f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f944f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a57b05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a57b05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a57aea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a57799e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a57799b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f944f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f944f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f944f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a57799a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (630 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr # | ... # `---data was truncated (10240/44315) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005567199e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005567199e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567199e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b6f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b6f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b6f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b6eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055671997ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055671997ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567199638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556719612e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556719612b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9b6eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b6eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b6eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556719612a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align # | ... # `---data was truncated (10240/102872) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055951d3eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055951d3ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055951d3ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ac7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ac7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ac7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ac7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055951d384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055951d384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055951d3698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055951d018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055951d018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ac7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ac7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ac7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055951d018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (632 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/nor.c (633 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnor_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nor.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nor.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000558ba4696eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ba4693e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ba469762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0de7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0de7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0de7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0de7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ba462cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ba462ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ba46118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ba42c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ba42c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0de7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0de7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0de7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ba42c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (634 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560feba76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560feba73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560feba7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e38249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e38249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e38231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560feba0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560feba0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560feb9f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560feb6a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560feb6a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e38232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e382330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560feb6a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (635 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %10) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/22375) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056551e5a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056551e5a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056551e5a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe184705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe18475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe184705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1846ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056551e53bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056551e53ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056551e5208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056551e1cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056551e1cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1846eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1846ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1846ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056551e1cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (637 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %2) # | call void @llvm.aarch64.sve.st2.nxv2i64.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } # | ... # `---data was truncated (10240/45653) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b6be197eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6be194e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6be19862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa28e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa28e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa28e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa28e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6be12dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6be12da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6be1128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6bddc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6bddc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa28e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa28e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa28e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6bddc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (638 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650342d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005650342d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005650342d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3aea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3aea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3aea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3aea231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056503426dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056503426da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650342528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565033f01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565033f01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3aea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3aea2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3aea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565033f01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (639 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.x2.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_x2( %op1, %op2, half noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store half %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load half, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync no # | ... # `---data was truncated (10240/10512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d0d8a7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0d8a7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0d8a8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a09e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a09ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a09e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a09e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0d8a15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0d8a15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0d89fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0d86a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0d86a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a09e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a09e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a09e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0d86a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_ # | ... # `---data was truncated (10240/11895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea0624ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea06249e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea0624d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f157c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f157c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f157c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f157c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea061e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea061e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea061c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea05e76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea05e76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f157c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f157c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f157c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea05e76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (641 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv16i8(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8i16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4i32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8f16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8f16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4f32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4f32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2f64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2f64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 { # | entry: # | %x0.addr = alloca i8, align 1 # | %x1.addr = alloca i8, align 1 # | %x2.addr = alloca i8, align 1 # | %x3.addr = alloca i8, align 1 # | %x4.addr = alloca i8, align 1 # | %x5.addr = alloca i8, align 1 # | %x6.addr = alloca i8, align 1 # | %x7.addr = alloca i8, align 1 # | %x8.addr = alloca i8, align 1 # | %x9.addr = alloca i8, align 1 # | %x10.addr = alloca i8, align 1 # | %x11.addr = alloca i8, align 1 # | %x12.addr = alloca i8, align 1 # | %x13.addr = alloca i8, align 1 # | %x14.addr = alloca i8, align 1 # | %x15.addr = alloca i8, align 1 # | store i8 %x0, ptr %x0.addr, align 1 # | store i8 %x1, ptr %x1.addr, align 1 # | store i8 %x2, ptr %x2.addr, align 1 # | store i8 %x3, ptr %x3.addr, align 1 # | store i8 %x4, ptr %x4.addr, align 1 # | store i8 %x5, ptr %x5.addr, align 1 # | store i8 %x6, ptr %x6.addr, align 1 # | store i8 %x7, ptr %x7.addr, align 1 # | store i8 %x8, ptr %x8.addr, align 1 # | store i8 %x9, ptr %x9.addr, align 1 # | store i8 %x10, ptr %x10.addr, align 1 # | store i8 %x11, ptr %x11.addr, align 1 # | store i8 %x12, ptr %x12.addr, align 1 # | store i8 %x13, ptr %x13.addr, align 1 # | store i8 %x14, ptr %x14.addr, align 1 # | store i8 %x15, ptr %x15.addr, align 1 # | %0 = load i8, ptr %x0.addr, align 1 # | %1 = load i8, ptr %x1.addr, align 1 # | %2 = load i8, ptr %x2.addr, align 1 # | %3 = load i8, ptr %x3.addr, align 1 # | %4 = load i8, ptr %x4.addr, align 1 # | %5 = load i8, ptr %x5.addr, align 1 # | %6 = load i8, ptr %x6.addr, align 1 # | %7 = load i8, ptr %x7.addr, align 1 # | %8 = load i8, ptr %x8.addr, align 1 # | %9 = load i8, ptr %x9.addr, align 1 # | %10 = load i8, ptr %x10.addr, align 1 # | %11 = load i8, ptr %x11.addr, align 1 # | %12 = load i8, ptr %x12.addr, align 1 # | %13 = load i8, ptr # | ... # `---data was truncated (10240/42600) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056514b9cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056514b9c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056514b9cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6f691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056514b962bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056514b962a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056514b9478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056514b5f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056514b5f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6f691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056514b5f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612a1fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612a1fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612a1fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2387c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2387ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2387c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2387c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612a1f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612a1f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612a1f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612a1c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612a1c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2387c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2387c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2387c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612a1c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (644 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9b29afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9b29ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9b29b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0409d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0409d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0409d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0409d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9b2945bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9b2945a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9b292a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9b25d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9b25d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0409d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0409d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0409d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9b25d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630e6b78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630e6b75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630e6b7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcafd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcafd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcafd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcafd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630e6b0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630e6b0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630e6af38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630e67a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630e67a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efcafd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcafd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcafd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630e67a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e4cee2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e4cedfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e4cee362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff67f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff67f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff67f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff67f403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e4ce78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e4ce78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e4ce5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e4cb0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e4cb0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff67f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff67f4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff67f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e4cb0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv32i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv32i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/121927) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0d5e0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0d5e08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0d5e0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb0aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb0aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb0aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb0aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0d5da1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0d5da1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0d5d868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0d5a35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0d5a35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb0aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb0aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb0aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0d5a35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (648 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b484406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b484403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b48440762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4b9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4b9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4b9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4b9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b48439cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b48439ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4843818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b484030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b484030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4b9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4b9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4b9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b484030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (649 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4d10aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4d10a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4d10ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78a1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78a138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78a1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78a131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4d1042bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4d1042a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4d10278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4d0cd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4d0cd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78a131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78a131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78a131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4d0cd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648b75b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648b75b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648b75b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f248e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f248e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f248e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f248e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648b754abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648b754aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648b752f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648b71dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648b71deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f248e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f248e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f248e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648b71dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055945bc4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055945bc47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055945bc4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe545733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe54578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe545733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe54571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055945bbe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055945bbe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055945bbc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055945b874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055945b874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe54571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe54571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe54571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055945b874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (652 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558f15780eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f1577de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f1578162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde1c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde1c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde1c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde1c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f15716bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f15716a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f156fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f153aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f153aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde1c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde1c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde1c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f153aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (653 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055579693feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055579693ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055579694062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e2a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e2a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e2a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e2a831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557968d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557968d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557968ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555796569e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555796569b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e2a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e2a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e2a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555796569a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (654 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2i64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2f64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %3) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !" # | ... # `---data was truncated (10240/10573) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556bd6d5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bd6d5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bd6d6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc32d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc32d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc32d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc32d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bd6cf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bd6cf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bd6cda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bd6989e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bd6989b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc32d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc32d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc32d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bd6989a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (655 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | ... # `---data was truncated (10240/78234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557974491eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055797448ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055797449262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e48705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e4875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e48705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e486ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557974427bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557974427a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055797440c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579740bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579740bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e486eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e486ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e486ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579740bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu( %maske # | ... # `---data was truncated (10240/75397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b44286eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b44283e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b4428762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b24d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b24d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b24d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b24d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b4421cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b4421ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b442018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b43eb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b43eb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b24d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b24d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b24d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b43eb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (657 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalt_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561cb09cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cb09cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cb09d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c22533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c2258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c22533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c2251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cb0965bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cb0965a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cb094a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cb05f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cb05f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c2251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c2251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c2251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cb05f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (658 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub # | ... # `---data was truncated (10240/84979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdf1a7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdf1a77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdf1a7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23b5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23b5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23b5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23b5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdf1a10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdf1a10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdf19f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdf16a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdf16a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23b5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23b5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23b5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdf16a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564593254eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564593251e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056459325562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc18d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc18d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc18d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc18d031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645931eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005645931eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645931cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564592e7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564592e7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc18d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc18d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc18d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564592e7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556edc46ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556edc469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556edc46d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd252733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd25278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd252733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd25271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556edc402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556edc402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556edc3e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556edc096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556edc096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd25271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd25271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd25271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556edc096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/135111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559efb811eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559efb80ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559efb81262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8ee649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8ee6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8ee649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8ee631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559efb7a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559efb7a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559efb78c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559efb43be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559efb43bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8ee632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8ee6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8ee6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559efb43ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (662 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8f16(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edaba62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055edaba5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055edaba6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f6c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edab9f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055edab9f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055edab9dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055edab68ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055edab68cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15f6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f6c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edab68ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (664 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056000d43beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056000d438e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056000d43c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45fe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45fe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45fe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45fe831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056000d3d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056000d3d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056000d3b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056000d065e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056000d065b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f45fe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45fe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45fe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056000d065a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (665 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/153905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcd4ed0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcd4ecde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcd4ed162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9f2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9f2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9f2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9f2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcd4e66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcd4e66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcd4e4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcd4afae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcd4afab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9f2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9f2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9f2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcd4afaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/18353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640b11a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640b11a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640b11a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec3bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec3bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec3bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec3beed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640b113dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640b113da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640b11228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640b0dd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640b0dd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec3beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec3beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec3beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640b0dd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (667 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578183beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578183bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578183bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9dce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9dce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9dce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9dce03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557818354bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557818354a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578183398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557817fe8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557817fe8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9dce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9dce050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9dce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557817fe8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (668 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622d867beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622d8678e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622d867c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd23333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd2338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd23333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd2331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622d8611bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622d8611a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622d85f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622d82a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622d82a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd2331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd2331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd2331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622d82a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (669 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de0c901eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de0c8fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de0c90262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc07f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc07f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc07f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc07eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de0c897bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de0c897a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de0c87c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de0c52be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de0c52bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc07eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc07eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc07eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de0c52ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (670 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eae08dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eae08d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eae08dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2292d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2292d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2292d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2292d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eae0871bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eae0871a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eae08568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eae0505e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eae0505b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2292d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2292d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2292d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eae0505a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055985c8e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055985c8e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055985c8ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdda3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdda3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdda3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdda3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055985c87fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055985c87fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055985c8648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055985c513e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055985c513b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdda3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdda3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdda3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055985c513a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cae0d28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cae0d25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cae0d2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff015d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff015d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff015d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff015d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cae0cbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cae0cbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cae0ca38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cae0952e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cae0952b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff015d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff015d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff015d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cae0952a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (673 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %low.addr = alloca <4 x half>, align 8 # | %high.addr = alloca <4 x half>, align 8 # | store <4 x half> %low, ptr %low.addr, align 8 # | store <4 x half> %high, ptr %high.addr, align 8 # | %0 = load <4 x half>, ptr %low.addr, align 8 # | %1 = load <4 x half>, ptr %high.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 { # | entry: # | %__p0.addr. # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558931309eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558931306e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055893130a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4c3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4c3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4c3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4c3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055893129fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055893129fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589312848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558930f33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558930f33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4c3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4c3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4c3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558930f33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (674 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600329c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600329c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600329c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21b3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21b3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21b3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21b3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056003295cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056003295ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600329418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600325f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600325f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21b3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21b3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21b3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600325f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (675 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1f503aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1f5037e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1f503b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f0c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f0c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f0c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f0c203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1f4fd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1f4fd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1f4fb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1f4c64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1f4c64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f0c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f0c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f0c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1f4c64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/95445) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f4e577eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f4e574e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f4e57862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f724e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f724e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f724e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f724e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4e50dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f4e50da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f4e4f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f4e1a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f4e1a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f724e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f724e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f724e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f4e1a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b41a1abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b41a1a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b41a1ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ea8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ea818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ea8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ea811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b41a141bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b41a141a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b41a1268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b419dd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b419dd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ea811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ea811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ea811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b419dd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (678 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(, ptr, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_s32offset( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/16554) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559acfc23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559acfc20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559acfc2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f56725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f5603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559acfbb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559acfbb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559acfb9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559acf84de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559acf84db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6f5604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f56050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f56050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559acf84da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (679 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e318247eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e318244e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e31824862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fcd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fcd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fcd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fcd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3181ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3181dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3181c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e317e71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e317e71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fcd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fcd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fcd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e317e71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (680 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 2) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8f16( %0, i32 4) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8f16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4f32( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4f32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2f64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2f64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8bf16( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8bf16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561e1d17aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e1d177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e1d17b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e1d110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e1d110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e1d0f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e1cda4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e1cda4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e1cda4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (681 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628db97deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628db97ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628db97e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5151733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f515178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5151733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f515171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628db913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628db913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628db8f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628db5a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628db5a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f515171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f515171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f515171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628db5a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (682 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load # | ... # `---data was truncated (10240/31171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ec8cfa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec8cfa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec8cfa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efda9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efda9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efda9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efda9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec8cf3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec8cf3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec8cf218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec8cbd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec8cbd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efda9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efda9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efda9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec8cbd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (683 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/83088) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612d178feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612d178ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612d179062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe274849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2748a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe274849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe274831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612d1725bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612d1725a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612d170a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612d13b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612d13b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe274832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2748330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2748330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612d13b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed356e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed356dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed356e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8280f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8280f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8280f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8280f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed35676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed35676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed3565b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed3530ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed3530ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8280f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8280f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8280f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed3530aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (685 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (686 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055d42ec59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d42ec56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d42ec5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39f1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39f1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39f1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39f1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d42ebefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d42ebefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d42ebd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d42e883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d42e883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39f1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39f1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39f1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d42e883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (687 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4929b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4929aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4929b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bba11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c492947bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c492947a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c49292c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4925dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4925dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bba11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4925dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (689 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563284eb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563284eb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563284eba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98e5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98e558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98e5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98e551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563284e4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563284e4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563284e348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563284ae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563284ae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98e551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98e551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98e551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563284ae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a601047eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a601044e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a60104862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2479f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2479f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2479f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2479f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a600fddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a600fdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a600fc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a600c71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a600c71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2479f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2479f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2479f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a600c71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef # | ... # `---data was truncated (10240/78336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f1c7e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f1c7e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f1c7ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feed8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feed84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feed8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feed8431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f1c77fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f1c77fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f1c7648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f1c413e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f1c413b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feed8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feed84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feed84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f1c413a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055567cc9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055567cc97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055567cc9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8df4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8df4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8df4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8df4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055567cc30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055567cc30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055567cc158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055567c8c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055567c8c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8df4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8df4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8df4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055567c8c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055571359ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555713599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055571359d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c73305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c7335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c73305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c732ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555713532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555713532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557135178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557131c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557131c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c732eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c732ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c732ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557131c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (694 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <2 x float>, align 8 # | store <2 x float> %x, ptr %x.addr, align 8 # | %0 = load <2 x float>, ptr %x.addr, align 8 # | %1 = bitcast <2 x float> %0 to <8 x i8> # | ret <8 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <8 x i8> %0 to <2 x float> # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <4 x float>, align 16 # | store <4 x float> %x, ptr %x.addr, align 16 # | %0 = load <4 x float>, ptr %x.addr, align 16 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 { # | entry: # | %x.addr = alloca i128, align 16 # | store i128 %x, ptr %x.addr, align 16 # | %0 = load i128, ptr %x.addr, align 16 # | %1 = bitcast i128 %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to i128 # | ret i128 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x0000565085cfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565085cf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565085cfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f093ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f093ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f093ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f093ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565085c90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565085c90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565085c758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565085924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565085924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f093ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f093ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f093ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565085924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577c9485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577c9482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577c948662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff499f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff499f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff499f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff499eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577c941bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577c941ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577c94008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577c90afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577c90afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff499eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff499eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff499eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577c90afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (696 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf22d4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf22d4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf22d5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcef6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcef638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcef6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcef631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf22ce5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf22ce5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf22cca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf22979e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf22979b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcef631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcef631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcef631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf22979a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, # | ... # `---data was truncated (10240/223801) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f89f8a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f89f8a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f89f8aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3634649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36346a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3634649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3634631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f89f83fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f89f83fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f89f8248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f89f4d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f89f4d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3634632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36346330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36346330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f89f4d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (698 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563238d0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563238d0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563238d0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3277c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3277ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3277c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3277c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563238ca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563238ca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563238c898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563238938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563238938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3277c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3277c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3277c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563238938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (700 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (701 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (702 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560425872eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056042586fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056042587362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac8301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac830725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac8301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac83003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560425808bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560425808a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604257ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056042549ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056042549cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac83004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac830050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac830050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056042549ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (704 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613683adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613683aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613683ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69fe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69fe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69fe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69fe51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561368343bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561368343a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613683288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561367fd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561367fd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69fe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69fe51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69fe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561367fd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (705 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (706 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a874868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a874865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a87486962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fd0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fd015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fd0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fd00ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8747febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8747fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8747e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a874492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a874492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4fd00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fd00ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fd00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a874492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7b9936eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7b9933e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7b993762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69e3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69e34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69e3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69e3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7b98ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7b98cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7b98b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7b9560e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7b9560b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69e3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69e34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69e34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7b9560a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562640f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562640f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562640f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf66849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf66849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf66831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562640f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562640f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562640ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562640ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562640ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf66832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf668330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562640ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (709 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005636d292feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636d292ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636d293062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3975c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3975ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3975c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3975c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636d28c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636d28c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636d28aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636d2559e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636d2559b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3975c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3975c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3975c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636d2559a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/68065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596cb1b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596cb1ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596cb1b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7f111b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596cb146bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596cb146a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596cb12b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596caddae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596caddab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7f111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596caddaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (711 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000558785dc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558785dc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558785dca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f742c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f742c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f742c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f742c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558785d5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558785d5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558785d448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587859f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587859f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f742c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f742c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f742c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587859f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (712 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | # | ... # `---data was truncated (10240/100521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fb1b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fb1b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fb1b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1847533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f184758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1847533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f184751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fb1ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fb1ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fb1a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fb1749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fb1749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f184751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f184751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f184751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fb1749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (713 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = # | ... # `---data was truncated (10240/124514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056075371ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560753719e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056075371d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0c811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607536b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607536b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607536978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560753346e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560753346b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0c811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560753346a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (714 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b035888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b035885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b03588962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d4f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d4f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d4f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d4f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b03581ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b03581ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0358038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0354b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0354b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d4f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d4f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d4f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0354b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (715 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ac92a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ac92a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ac92a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45bb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ac923dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ac923da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ac92228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ac8ed1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ac8ed1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f45bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45bb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ac8ed1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c167669eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c167666e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c16766a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c5001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c500725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c5001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c50003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1675ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1675ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1675e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c167293e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c167293b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c50004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c500050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c500050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c167293a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (718 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (719 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562895da5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562895da2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562895da662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21fc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21fc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21fc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21fc71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562895d3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562895d3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562895d208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628959cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628959cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21fc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21fc71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21fc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628959cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16 # | ... # `---data was truncated (10240/33616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558deb3e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558deb3e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558deb3e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34b8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34b818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34b8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34b811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558deb37abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558deb37aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558deb35f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558deb00ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558deb00eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34b811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34b811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34b811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558deb00ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (721 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056069321ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560693219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056069321d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee47849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee47849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee47831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606931b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005606931b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606931978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560692e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560692e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee47832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee478330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560692e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (722 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561921b0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561921b08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561921b0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f372fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f372fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f372fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f372fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561921aa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561921aa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561921a868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561921735e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561921735b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f372fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f372fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f372fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561921735a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eab0a4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eab0a4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eab0a4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d2231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eab09e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eab09e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eab09c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eab0677e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eab0677b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3d2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eab0677a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a658a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a658a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a658a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eced1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a6583cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a6583ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a658218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a654d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a654d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8eced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eced1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a654d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (725 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__p2.addr.i3 = alloca <4 x half>, align 8 # | %__ret.i4 = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i1, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8 # | store <4 x half> %5, ptr %__p2.addr.i3, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %13, ptr %__ret.i4, align 8 # | %14 = load <4 x half>, ptr %__ret.i4, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__p1.addr.i2 = alloca <8 x half>, align 16 # | %__p2.addr.i3 = alloca <8 x half>, align 16 # | %__ret.i4 = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i1, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16 # | store <8 x half> %5, ptr %__p2.addr.i3, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %13, ptr %__ret.i4, align 16 # | %14 = load <8 x half>, ptr %__ret.i4, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <4 x half>, ptr %__s0, align 8 # | %4 = load <4 x half>, ptr %__s1, align 8 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <4 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %9 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %3, ptr %__p0.addr.i, align 8 # | store <4 x half> %4, ptr %__p1.addr.i, align 8 # | store <4 x half> %9, ptr %__p2.addr.i, align 8 # | %10 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %13 = bitcast <8 x i8> %10 to <4 x half> # | %14 = bitcast <8 x i8> %11 to <4 x half> # | %15 = bitcast <8 x i8> %12 to <4 x half> # | %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13) # | store <4 x half> %16, ptr %ref.tmp.i, align 8 # | %17 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %17, ptr %__ret.i, align 8 # | %18 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %18, ptr %__ret, align 8 # | %19 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %19, ptr %tmp, align 8 # | %20 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %20 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store half %c, ptr %c.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <8 x half>, ptr %__s0, align 16 # | %4 = load <8 x half>, ptr %__s1, align 16 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <8 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3 # | %9 = load half, ptr %__s2, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4 # | %10 = load half, ptr %__s2, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5 # | %11 = load half, ptr %__s2, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6 # | %12 = load half, ptr %__s2, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %13 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %3, ptr %__p0.addr.i, align 16 # | store <8 x half> %4, ptr %__p1.addr.i, align 16 # | store <8 x half> %13, ptr %__p2.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %15 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %16 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %17 = bitcast <16 x i8> %14 to <8 x half> # | %18 = bitcast <16 x i8> %15 to <8 x half> # | %19 = bitcast <16 x i8> %16 to <8 x half> # | %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17) # | store <8 x half> %20, ptr %ref.tmp.i, align 16 # | %21 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %21, ptr %__ret.i, align 16 # | %22 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %22, ptr %__ret, align 16 # | %23 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %23, ptr %tmp, align 16 # | %24 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half # | ... # `---data was truncated (10240/31903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b08c5c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b08c5bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b08c5c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8abf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8abf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8abf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8abf831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b08c558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b08c558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b08c53d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b08c1ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b08c1ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8abf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8abf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8abf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b08c1eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/minv.c (726 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055996064deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055996064ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055996064e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70d5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70d56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70d5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70d5631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599605e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599605e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599605c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559960277e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559960277b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70d5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70d56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70d56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559960277a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (727 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e7bb52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e7bb4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e7bb5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcbcf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcbcf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcbcf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcbceed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e7bae8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e7bae8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e7bacd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e7b77ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e7b77cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efcbceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcbceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcbceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e7b77ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (728 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (729 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (730 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/66065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b832fbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b832fbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b832fbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b832f54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b832f54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b832f398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b832be8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b832be8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b832be8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (731 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (732 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056471cf39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056471cf36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056471cf3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb03fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb03fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb03fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb03fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056471cecfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056471cecfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056471ceb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056471cb63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056471cb63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb03fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb03fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb03fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056471cb63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (733 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (734 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e3137b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3137b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3137b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f601aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f601aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f601aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f601aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e313749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e313749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e31372e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3133dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3133ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f601aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f601aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f601aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3133dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (735 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005571ff2e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571ff2e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571ff2e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e9fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e9fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e9fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e9fced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571ff279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571ff279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571ff25e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571fef0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571fef0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e9fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e9fcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e9fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571fef0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056282e066eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056282e063e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056282e06762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9953c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9953ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9953c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9953c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056282dffcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056282dffca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056282dfe18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056282dc90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056282dc90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9953c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9953c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9953c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056282dc90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (737 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i # | ... # `---data was truncated (10240/14644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561128f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561128f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561128f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7550905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f755095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7550905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75508ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561128ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561128ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561128eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561128b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561128b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75508eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75508ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75508ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561128b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (738 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | # | ... # `---data was truncated (10240/31781) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563bef823eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bef820e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bef82462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bef7b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bef7b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bef79e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bef44de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bef44db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efca3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bef44da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (739 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpa_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpa.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpa.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559888e01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559888dfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559888e0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc948e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc948ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc948e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc948e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559888d97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559888d97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559888d7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559888a2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559888a2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc948e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc948e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc948e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559888a2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (740 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cfcf42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cfcf3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cfcf4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1021249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1021249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1021231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cfced8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cfced8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cfcebd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cfcb6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cfcb6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1021232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10212330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cfcb6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (741 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (742 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fcd37beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fcd378e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fcd37c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff520849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5208a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff520849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff520831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fcd311bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fcd311a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fcd2f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fccfa5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fccfa5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff520832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5208330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5208330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fccfa5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba13781eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba1377ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba1378262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef2e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef2e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef2e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef2e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba13717bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba13717a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba136fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba133abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba133abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef2e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef2e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef2e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba133aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (744 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 29, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 30, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557327134eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557327131e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055732713562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa542a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa542aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa542a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa542a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573270cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005573270caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573270af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557326d5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557326d5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa542a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa542a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa542a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557326d5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (745 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565146f81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565146f7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565146f8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f4c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f4c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f4c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f4c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565146f17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565146f17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565146efc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565146babe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565146babb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f4c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f4c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f4c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565146baba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (746 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f04ceb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f04ceb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f04ceb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f432f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f432f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f432f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f432f603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f04ce4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f04ce4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f04ce2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f04cadee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f04cadeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f432f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f432f6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f432f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f04cadea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa77aa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa77aa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa77aa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f47c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f47ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f47c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f47c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa77a3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa77a3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa77a208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa776cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa776cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f47c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f47c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f47c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa776cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (748 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bfbdb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558bfbdb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558bfbdba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe480733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe48078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe480733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe48071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bfbd4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558bfbd4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558bfbd348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bfb9e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bfb9e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe48071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe48071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe48071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bfb9e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (749 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpkhi.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpkhi.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b94ae99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b94ae96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b94ae9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dcac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dcac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dcac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dcac03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b94ae2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b94ae2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b94ae148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b94aac3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b94aac3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8dcac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dcac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dcac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b94aac3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649608caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649608c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649608cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0eb0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0eb038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0eb0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0eb031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564960860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564960860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649608458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649604f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649604f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0eb031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0eb031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0eb031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649604f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (751 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef9d7cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef9d7c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef9d7cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc10a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc10a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc10a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc10a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef9d761bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef9d761a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef9d7468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef9d3f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef9d3f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc10a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc10a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc10a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef9d3f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (753 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056541fce4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056541fce1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056541fce562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa904649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9046a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa904649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa904631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056541fc7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056541fc7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056541fc5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056541f90ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056541f90eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa904632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9046330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9046330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056541f90ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-fma.c (754 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %sub.i = fsub <4 x float> %3, %mul.i # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %sub.i = fsub <2 x float> %3, %mul.i # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_68 = alloca <2 x float>, align 8 # | %__s0_68 = alloca <2 x float>, align 8 # | %__s1_68 = alloca <2 x float>, align 8 # | %__s2_68 = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp1 = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0_68, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_68, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_68, align 8 # | %3 = load <2 x float>, ptr %__s0_68, align 8 # | %4 = load <2 x float>, ptr %__s1_68, align 8 # | %5 = load <2 x float>, ptr %__s2_68, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | %mul = fmul <2 x float> %4, %10 # | %add = fadd <2 x float> %3, %mul # | store <2 x float> %add, ptr %__ret_68, align 8 # | %11 = load <2 x float>, ptr %__ret_68, align 8 # | store <2 x float> %11, ptr %tmp1, align 8 # | %12 = load <2 x float>, ptr %tmp1, align 8 # | ret <2 x float> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_58 = alloca <4 x float>, align 16 # | %__s0_58 = alloca <4 x float>, align 16 # | %__s1_58 = alloca <4 x float>, align 16 # | %__s2_58 = alloca <2 x float>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp1 = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__s0_58, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_58, align 16 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_58, align 8 # | %3 = load <4 x float>, ptr %__s0_58, align 16 # | %4 = load <4 x float>, ptr %__s1_58, align 16 # | %5 = load <2 x float>, ptr %__s2_58, align 8 # | store <2 x f # | ... # `---data was truncated (10240/44730) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005627c26b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627c26aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627c26b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba63933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba6398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba63933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba6391b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627c2647bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627c2647a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627c262c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627c22dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627c22dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba6391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba6391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba6391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627c22dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-poly-add.c (755 of 27910) ******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | store <8 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <4 x i16> # | store <4 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <1 x i64> # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | store <16 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <16 x i8>, ptr %ref.tmp.i, align 8 # | store <16 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <16 x i8>, ptr %__ret.i, align 8 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | store <8 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <8 x i16> # | store <8 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 8 # | store <8 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i16>, ptr %__ret.i, align 8 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 8 # | %__p1.addr.i = alloca <2 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = load <2 x i64>, ptr %b.addr, align 8 # | store <2 x i64> %0, ptr %__p0.addr.i, align 8 # | store <2 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | store <2 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i64>, ptr %ref.tmp.i, align 8 # | store <2 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i64>, ptr %__ret.i, align 8 # | ret <2 x i64> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005594df6dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594df6dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594df6e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f088e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f088e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f088e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f088e831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594df675bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594df675a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594df65a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594df309e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594df309b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f088e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f088e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f088e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594df309a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d8ba34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d8ba31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d8ba3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cdac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cdac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cdac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cdac03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d8b9cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d8b9caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d8b9af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d8b65ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d8b65eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cdac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cdac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cdac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d8b65ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (758 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df75c0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df75c0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df75c1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3fa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3fa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3fa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3fa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df75ba5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df75ba5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df75b8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df75839e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df75839b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3fa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3fa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3fa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df75839a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055975ebadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055975ebaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055975ebae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd187a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd187a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd187a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd187a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055975eb43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055975eb43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055975eb288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055975e7d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055975e7d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd187a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd187a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd187a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055975e7d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (760 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055907540eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055907540be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055907540f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f618e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f618e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f618e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f618e203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590753a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005590753a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590753898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559075038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559075038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f618e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f618e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f618e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559075038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.a # | ... # `---data was truncated (10240/174713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557155eefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557155eece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557155ef062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf7a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf7a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf7a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf7a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557155e85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557155e85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557155e6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557155b19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557155b19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febf7a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf7a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf7a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557155b19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ccef40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ccef3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ccef4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ea9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ea978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ea9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ea971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cceed6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cceed6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cceebb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cceb6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cceb6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ea971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ea971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ea971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cceb6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d6e292eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d6e28fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d6e29362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9a1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9a10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9a1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9a1031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d6e228bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d6e228a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d6e20d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d6debce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d6debcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9a1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9a10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9a10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d6debca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (764 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055cfb6145eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfb6142e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfb614662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe14e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe14e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe14e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe14e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfb60dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfb60dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfb60c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfb5d6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfb5d6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe14e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe14e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe14e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfb5d6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (765 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c101f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c101f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c101f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febe2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febe26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febe2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febe2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c101f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c101f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c101efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c101bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c101bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febe2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febe26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febe26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c101baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (767 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp sle i32 %2, %3 # | %sle.i = zext i1 %4 to i32 # | ret i32 %sle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp ule i32 %2, %3 # | %sleu.i = zext i1 %4 to i32 # | ret i32 %sleu.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = sext i16 %1 to i32 # | %exths.i = sext i16 %1 to i32 # | ret i32 %exths.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = zext i16 %1 to i32 # | %exthz.i = zext i16 %1 to i32 # | ret i32 %exthz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = sext i8 %1 to i32 # | %extbs.i = sext i8 %1 to i32 # | ret i32 %extbs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = zext i8 %1 to i32 # | %extbz.i = zext i8 %1 to i32 # | ret i32 %extbz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | st # | ... # `---data was truncated (10240/15696) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557fd521eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557fd51ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557fd52262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bbf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bbf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bbf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bbf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557fd4b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557fd4b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557fd49c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557fd14be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557fd14bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bbf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bbf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bbf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557fd14ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (768 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588ba582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588ba57fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588ba58362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4abd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4abd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4abd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4abd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588ba518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588ba518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588ba4fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588ba1ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588ba1acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4abd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4abd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4abd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588ba1aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9d3db6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9d3db3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9d3db762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3671649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36716a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3671649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3671631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9d3d4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9d3d4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9d3d318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9d39e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9d39e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3671632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36716330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36716330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9d39e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d3913ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d39139e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d3913d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b60933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b6098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b60933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b6091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d390d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d390d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d390b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d38d66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d38d66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b6091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b6091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b6091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d38d66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (771 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (772 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.fr # | ... # `---data was truncated (10240/27970) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005606fb5c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005606fb5bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005606fb5c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3a5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3a555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3a5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3a54ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606fb556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005606fb556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606fb53b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606fb1eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606fb1eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3a54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3a54ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3a54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606fb1eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (773 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/22483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556209e63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556209e60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556209e6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce35a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce35aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce35a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce35a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556209df9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556209df9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556209dde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556209a8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556209a8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce35a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce35a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce35a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556209a8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (774 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , # | ... # `---data was truncated (10240/170497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649fae1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649fae1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649fae2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f390d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f390d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f390d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f390d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649fadb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649fadb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649fad9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649faa49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649faa49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f390d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f390d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f390d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649faa49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (775 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cb5e27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cb5e24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cb5e2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c1d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c1d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c1d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c1d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cb5dbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cb5dbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cb5da28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cb5a51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cb5a51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c1d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c1d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c1d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cb5a51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (776 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bf16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056076aab1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056076aaaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056076aab262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8d7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8d798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8d7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8d791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056076aa47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056076aa47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056076aa2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056076a6dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056076a6dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8d791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8d791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8d791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056076a6dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e90f3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e90f3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e90f4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb55f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb55f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb55f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb55f003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e90ed5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e90ed5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e90eba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e90b69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e90b69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb55f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb55f0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb55f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e90b69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (778 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f062ca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f062c9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f062ca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadbf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadbf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadbf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadbf0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f062c38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f062c38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f062c1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0628cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0628ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadbf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadbf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadbf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0628cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b97f6a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b97f69ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b97f6a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3c3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3c315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3c3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3c30ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b97f637bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b97f637a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b97f61c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b97f2cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b97f2cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3c30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3c30ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3c30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b97f2cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ac334beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ac3348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ac334c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2e071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ac32e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ac32e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ac32c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ac2f75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ac2f75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2e071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ac2f75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (781 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4e736feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4e736ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4e737062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4c5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4c56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4c5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4c5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4e7305bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c4e7305a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4e72ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4e6f99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4e6f99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4c5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4c56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4c56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4e6f99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-neon-vld.c (782 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float16x4x3_t, ptr %retval, align 8 # | ret %struct.float16x4x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float16x4x4_t, ptr %retval, align 8 # | ret %struct.float16x4x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float32x2x2_t, ptr %retval, align 8 # | ret %struct.float32x2x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float32x2x3_t, ptr %retval, align 8 # | ret %struct.float32x2x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float32x2x4_t, ptr %retval, align 8 # | ret %struct.float32x2x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0) # | store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.poly16x4x2_t, ptr %retval, align 8 # | ret %struct.poly16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16 # | ... # `---data was truncated (10240/109928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e6b115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e6b112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e6b11662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f492a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f492a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f492a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f492a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e6b0abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e6b0aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e6b0908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e6ad3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e6ad3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f492a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f492a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f492a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e6ad3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565492424eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565492421e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056549242562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a26d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a26d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a26d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a26d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654923babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654923baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056549239f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056549204ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056549204eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a26d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a26d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a26d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056549204ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (784 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055738c429eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055738c426e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055738c42a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f851a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f851a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f851a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f851a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055738c3bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055738c3bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055738c3a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055738c053e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055738c053b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f851a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f851a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f851a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055738c053a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (785 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649b9e3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649b9e3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649b9e3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ca1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ca16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ca1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ca1631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649b9dd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649b9dd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649b9db98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649b9a68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649b9a68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ca1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ca16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ca16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649b9a68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (786 of 27910) ******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32-unknown-unknown" # | # | %struct.asc = type { i8, i16, i32, i32, float, double } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %0 = load i32, ptr %argp.next, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16 # | store ptr %argp.next2, ptr %va, align 4 # | %2 = load double, ptr %1, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %2 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11 # | %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load i32, ptr %argp.next, align 8, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0) # | store <2 x i64> %call, ptr %r, align 16, !tbaa !9 # | ret void # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr n # | ... # `---data was truncated (10240/20646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default)' --expand-variadics-override=optimize -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default) --expand-variadics-override=optimize -o - # | #0 0x00005624305efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624305ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624305f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f649da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f649daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f649da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f649da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562430585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562430585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056243056a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562430219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562430219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f649da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f649da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f649da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562430219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (787 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvt.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvt.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvt.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_u32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_s32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcvt_f32_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, p # | ... # `---data was truncated (10240/39207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562aaf5f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562aaf5f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562aaf5f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed68133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed6818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed68133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed6811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aaf58abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562aaf58aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562aaf56f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562aaf21ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562aaf21eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed6811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed6811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed6811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aaf21ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (788 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (789 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 { # | entry: # | %cnt.addr = alloca target("aarch64.svcount"), align 2 # | store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2 # | %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount( %0) # | ret target("aarch64.svcount") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b606b15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b606b12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b606b1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1b521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1b52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1b521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1b5203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b606aabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b606aaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b606a908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b60673fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b60673fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1b5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1b52050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1b52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b60673fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (790 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618fb116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618fb113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618fb11762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d9e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d9e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d9e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d9e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618fb0acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618fb0aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618fb0918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618fad40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618fad40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d9e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d9e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d9e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618fad40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (791 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619f662eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619f662be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619f662f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c0e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c0e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c0e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c0e203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619f65c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619f65c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619f65a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619f6258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619f6258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c0e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c0e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c0e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619f6258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (792 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562dc7676eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562dc7673e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562dc767762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47dff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47dff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47dff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47dff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dc760cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562dc760ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562dc75f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562dc72a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562dc72a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47dff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47dff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47dff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dc72a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (793 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_812 = alloca <4 x float>, align 16 # | %__s0_812 = alloca <4 x float>, align 16 # | %__s1_812 = alloca <8 x bfloat>, align 16 # | %__s2_812 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <4 x float>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp2 = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0_812, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1_812, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <8 x bfloat> %2, ptr %__s2_812, align 16 # | %3 = load <4 x float>, ptr %__s0_812, align 16 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 16 # | %5 = load <4 x float>, ptr %__s2_812, align 16 # | store <4 x float> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 16 # | %8 = load <4 x float>, ptr %ref.tmp1, align 16 # | store <4 x float> %8, ptr %__ret, align 16 # | %9 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %9, ptr %tmp, align 16 # | %10 = load <4 x float>, ptr %tmp, align 16 # | store <4 x float> %10, ptr %ref.tmp, align 16 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <4 x float> %3, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %15, ptr %__ret.i, align 16 # | %16 = load <4 x float>, ptr %__ret.i, align 16 # | store <4 x float> %16, ptr %__ret_812, align 16 # | %17 = load <4 x float>, ptr %__ret_812, align 16 # | store <4 x float> %17, ptr %tmp2, align 16 # | %18 = load <4 x float>, ptr %tmp2, align 16 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, # | ... # `---data was truncated (10240/54685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bb93df6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb93df3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb93df762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42cb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb93d8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb93d8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb93d718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb93a20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb93a20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb93a20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e00d0f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e00d0f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e00d0f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58e5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58e5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58e5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58e5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e00d089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e00d089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e00d06e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e00cd1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e00cd1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58e5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58e5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58e5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e00cd1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (795 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b20ba7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b20ba78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b20ba7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31f4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b20ba11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b20ba11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b20b9f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b20b6a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b20b6a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31f4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b20b6a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (797 of 27910) ******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # | #0 0x000055e7cf1ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7cf1cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7cf1cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a65e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a65ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a65e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a65e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7cf164bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7cf164a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7cf1498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7cedf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7cedf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a65e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a65e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a65e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7cedf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (798 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a3bef7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a3bef4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a3bef862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eb6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eb66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eb6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eb6631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a3be8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a3be8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a3be728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a3bb21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a3bb21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5eb6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eb66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eb66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a3bb21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (799 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562398c7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562398c7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562398c7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06be533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06be58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06be533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06be51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562398c14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562398c14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562398bf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623988a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623988a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06be51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06be51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06be51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623988a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056483b972eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056483b96fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056483b97362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb64b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb64b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb64b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb64b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056483b908bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056483b908a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056483b8ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056483b59ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056483b59cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb64b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb64b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb64b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056483b59ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b68f6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b68f68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b68f6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f224781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22478725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f224781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2247803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b68f01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b68f01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b68ee68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b68b95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b68b95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2247804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22478050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22478050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b68b95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (802 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { < # | ... # `---data was truncated (10240/50724) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056119594deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056119594ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056119594e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f507f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f507f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f507f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f507f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611958e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611958e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611958c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561195577e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561195577b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f507f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f507f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f507f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561195577a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (803 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a02eedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a02eeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a02eee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bb2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bb2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bb2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bb2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a02e83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a02e83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a02e688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a02b17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a02b17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bb2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bb2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bb2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a02b17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (805 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f009445eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f009442e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f00944662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a4821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a482725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a4821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a48203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0093dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0093dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0093c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f00906fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f00906fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a48204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a482050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a482050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f00906fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b32d8edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b32d8eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b32d8ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0064933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f006498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0064933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f006491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b32d883bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b32d883a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b32d8688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b32d517e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b32d517b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f006491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f006491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f006491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b32d517a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (808 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562588a94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562588a91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562588a9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67a4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67a458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67a4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67a451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562588a2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562588a2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562588a0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625886bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625886beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67a451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67a451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67a451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625886bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056105d7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056105d7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056105d7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3555449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3555449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3555431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056105d791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056105d791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056105d7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056105d425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056105d425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3555432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35554330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056105d425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (810 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brka.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brka.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555c21f5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c21f5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c21f6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8a5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8a5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8a5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8a5e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c21ef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c21ef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c21eda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c21b89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c21b89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8a5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8a5e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8a5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c21b89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (811 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b9734ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b97349e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b9734d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd865733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd86578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd865733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd86571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b972e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b972e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b972c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b96f76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b96f76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd86571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd86571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd86571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b96f76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaf9380eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eaf937de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eaf938162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dc5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dc538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dc5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dc531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaf9316bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eaf9316a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eaf92fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eaf8faae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eaf8faab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3dc531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dc531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dc531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaf8faaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (814 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565115355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565115352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056511535662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3f9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3f9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3f9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3f9a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651152ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651152eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651152d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565114f7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565114f7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3f9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3f9a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3f9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565114f7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (815 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, % # | ... # `---data was truncated (10240/291999) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6e200feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6e200ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6e201062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4194105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f419415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4194105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41940ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6e1fa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6e1fa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6e1f8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6e1c39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6e1c39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41940eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41940ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41940ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6e1c39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c3b327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c3b324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c3b32862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6b9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6b9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6b9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6b9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c3b2bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c3b2bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c3b2a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c3af51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c3af51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6b9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6b9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6b9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c3af51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (817 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6) # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6) # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__p1.addr.i.i = alloca <4 x half>, align 8 # | %__p2.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8 # | store <4 x half> %5, ptr %__p2.addr.i.i, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %13, ptr %__ret.i.i, align 8 # | %14 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <8 x half>, align 16 # | %__p1.addr.i.i = alloca <8 x half>, align 16 # | %__p2.addr.i.i = alloca <8 x half>, align 16 # | %__ret.i.i = alloca <8 x half>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i.i, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16 # | store <8 x half> %5, ptr %__p2.addr.i.i, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16 # | store <8 x half> %13, ptr %__ret.i.i, align 16 # | %14 = load <8 x half>, ptr %__ret.i.i, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1) # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1 # | ... # `---data was truncated (10240/42739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ef94c7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef94c78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef94c7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f50d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef94c11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef94c11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef94bf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef948a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef948a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef948a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (818 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlastb_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lastb.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lastb.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlastb_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lastb.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lastb.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlastb_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lastb.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lastb.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlastb_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005591acf91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591acf8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591acf9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31b0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31b018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31b0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31b011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591acf27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591acf27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591acf0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591acbbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591acbbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31b011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31b011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31b011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591acbbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (819 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562155a45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562155a42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562155a4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bb9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bb92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bb9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bb9231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621559dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621559dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621559c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056215566fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056215566fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bb9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bb92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bb92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056215566fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (820 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565473c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565473c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565473c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9683733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f968378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9683733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f968371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565473be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565473be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565473bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565473874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565473874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f968371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f968371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f968371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565473874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx # | ... # `---data was truncated (10240/75125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631e6a39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631e6a36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631e6a3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3b541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3b54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3b541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3b5403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631e69cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631e69cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631e69b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631e6663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631e6663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3b5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3b54050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3b54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631e6663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (823 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function # | ... # `---data was truncated (10240/12439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d41c4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d41c4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d41c5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe39f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe39f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe39f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe39f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d41be5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d41be5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d41bca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d41879e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d41879b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe39f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe39f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe39f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d41879a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af6a9f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af6a9f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af6a9fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01bcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af6a98fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af6a98fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af6a9748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af6a623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af6a623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af6a623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, al # | ... # `---data was truncated (10240/169925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056173630feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056173630ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056173631062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34b541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34b54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34b541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34b5403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617362a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617362a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056173628a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561735f39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561735f39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34b5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34b54050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34b54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561735f39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (826 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (827 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631f0565eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631f0562e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631f056662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd530449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5304a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd530449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd530431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631f04fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631f04fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631f04e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631f018fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631f018fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd530432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5304330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5304330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631f018fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (828 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svadda_f16( %pg, half noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca half, align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store half %initial, ptr %initial.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load half, ptr %initial.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call half @llvm.aarch64.sve.fadda.nxv8f16( %3, half %1, %2) # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fadda.nxv8f16(, half, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svadda_f32( %pg, float noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca float, align 4 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store float %initial, ptr %initial.addr, align 4 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load float, ptr %initial.addr, align 4 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call float @llvm.aarch64.sve.fadda.nxv4f32( %3, float %1, %2) # | ret float %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fadda.nxv4f32(, float, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svadda_f64( %pg, double noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca double, align 8 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store double %initial, ptr %initial.addr, align 8 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load double, ptr %initial.addr, align 8 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call double @llvm.aarch64.sve.fadda.nxv2f64( %3, double %1, %2) # | ret double %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fadda.nxv2f64(, double, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056430d5bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056430d5bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056430d5be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb93133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb9318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb93133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb9311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056430d553bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056430d553a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056430d5388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056430d1e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056430d1e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb9311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb9311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb9311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056430d1e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (829 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.lane.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx3( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx7( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 7) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eddbc2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eddbc2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eddbc2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe840533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe84058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe840533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe84051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eddbbc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eddbbc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eddbba98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eddb858e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eddb858b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe84051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe84051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe84051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eddb858a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (830 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563634902eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636348ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056363490362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa434333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa43438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa434333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa43431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563634898bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563634898a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056363487d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056363452ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056363452cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa43431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa43431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa43431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363452ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (832 of 27910) ******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | @X = global i32 0, align 4 # | @Y = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @foo() #0 { # | entry: # | %retval = alloca i32, align 4 # | %i = alloca i32, align 4 # | store i32 0, ptr %i, align 4 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %entry # | %0 = load i32, ptr %i, align 4 # | %cmp = icmp slt i32 %0, 100 # | br i1 %cmp, label %for.body, label %for.end # | # | for.body: ; preds = %for.cond # | br label %for.end # | # | for.inc: ; No predecessors! # | %1 = load i32, ptr %i, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %i, align 4 # | br label %for.cond # | # | for.end: ; preds = %for.body, %for.cond # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type] # | 13 | } # | | ^ # | 1 warning generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # | #0 0x000055c157b16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c157b13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c157b1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d70d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d70d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d70d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d70d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c157aacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c157aaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c157a918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c157740e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c157740b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d70d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d70d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d70d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c157740a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (833 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557c20781eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c2077ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c2078262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c4d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c20717bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c20717a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c206fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c203abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c203abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c4d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c203aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (834 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = # | ... # `---data was truncated (10240/39218) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbaece3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbaece0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbaece462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f70533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f7058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f70533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f7051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbaec79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbaec79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbaec5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbae90de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbae90db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f7051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f7051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f7051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbae90da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (835 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsetffr() #0 { # | entry: # | call void @llvm.aarch64.sve.setffr() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.setffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bbaa0e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbaa0e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbaa0e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f085d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f085d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f085d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f085d4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbaa07abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbaa07aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbaa05f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bba9d0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bba9d0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f085d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f085d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f085d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bba9d0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr % # | ... # `---data was truncated (10240/67150) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564019d27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564019d24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564019d2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f5ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f5baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f5ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f5ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564019cbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564019cbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564019ca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564019951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564019951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f5ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f5ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f5ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564019951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align # | ... # `---data was truncated (10240/18311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5ce480eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5ce47de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5ce48162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22bd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22bd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22bd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22bd803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5ce416bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5ce416a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5ce3fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5ce0aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5ce0aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22bd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22bd8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22bd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5ce0aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f4e067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f4e064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f4e06862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feff6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feff68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feff6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feff6831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4dffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f4dffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f4dfe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f4dc91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f4dc91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feff6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feff68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feff68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f4dc91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0ad100eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0ad0fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0ad10162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a8b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a8b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a8b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a8b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0ad096bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0ad096a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0ad07b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0acd2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0acd2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a8b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a8b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a8b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0acd2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (840 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %6, ptr %__ret.i, align 8 # | %7 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_812 = alloca <4 x float>, align 8 # | %__s0_812 = alloca <4 x float>, align 8 # | %__s1_812 = alloca <8 x bfloat>, align 8 # | %__s2_812 = alloca <8 x bfloat>, align 8 # | %ref.tmp = alloca <4 x float>, align 8 # | %__ret = alloca <4 x float>, align 8 # | %__s0 = alloca <4 x float>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x float>, align 8 # | %tmp2 = alloca <4 x float>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | store <4 x float> %0, ptr %__s0_812, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | store <8 x bfloat> %1, ptr %__s1_812, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <8 x bfloat> %2, ptr %__s2_812, align 8 # | %3 = load <4 x float>, ptr %__s0_812, align 8 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 8 # | %5 = load <4 x float>, ptr %__s2_812, align 8 # | store <4 x float> %5, ptr %__s0, align 8 # | %6 = load <16 x i8>, ptr %__s0, align 8 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <4 x float>, ptr %ref.tmp1, align 8 # | store <4 x float> %8, ptr %__ret, align 8 # | %9 = load <4 x float>, ptr %__ret, align 8 # | store <4 x float> %9, ptr %tmp, align 8 # | %10 = load <4 x float>, ptr %tmp, align 8 # | store <4 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x float> %3, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %15, ptr %__ret.i, align 8 # | %16 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %16, ptr %__ret_812, align 8 # | %17 = load <4 x float>, ptr %__ret_812, align 8 # | store <4 x float> %17, ptr %tmp2, align 8 # | %18 = load <4 x float>, ptr %tmp2, align 8 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_814 = alloca <2 x float>, al # | ... # `---data was truncated (10240/54174) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b71f29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b71f297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b71f29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f2b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f2b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f2b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f2b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b71f230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b71f230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b71f2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b71eec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b71eec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f2b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f2b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f2b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b71eec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (841 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/100952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b32d08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b32d05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b32d0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc30133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc3018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc30133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc3011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b32c9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b32c9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b32c838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b32932e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b32932b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc3011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc3011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc3011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b32932a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (842 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (843 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_mf8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_bf16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d4fa73eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4fa73be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4fa73f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f365e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f365e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f365e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f365e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4fa6d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4fa6d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4fa6b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4fa368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4fa368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f365e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f365e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f365e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4fa368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (844 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566d242deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566d242ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566d242e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ac881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ac88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ac881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ac8803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566d23c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566d23c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566d23a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566d2057e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566d2057b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ac8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ac88050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ac88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566d2057a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (845 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %add.i = fadd <4 x float> %2, %3 # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %sub.i = fsub <2 x float> %2, %3 # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <4 x float> %2, %3 # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <2 x double> %2, %3 # | store <2 x double> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <4 x float> %2, %3 # | store <4 x float> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <2 x double> %2, %3 # | store <2 x double> %mul.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | %v3.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | store <2 x float> %v3, ptr %v3.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | %2 = load <2 x float>, ptr %v3.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x float>, ptr %__p2.addr.i, align 8 # | %mul.i = fmul <2 x float> %4, %5 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %6 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | %v3.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | store <4 x float> %v3, ptr %v3.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | %2 = load <4 x float>, ptr %v3.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load <4 x float>, ptr %__p2.addr.i, align 16 # | %mul.i = fmul <4 x float> %4, %5 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; F # | ... # `---data was truncated (10240/91378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005621fa0dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621fa0d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621fa0dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcef2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcef22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcef2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcef2231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621fa072bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621fa072a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621fa0578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621f9d06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621f9d06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcef2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcef22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcef22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621f9d06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl # | ... # `---data was truncated (10240/78896) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe2f6ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe2f6fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe2f70062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efce5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efce52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efce5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efce5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe2f695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe2f695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe2f67a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe2f329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe2f329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efce5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efce52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efce52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe2f329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (847 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> # | ... # `---data was truncated (10240/16951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ef8995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ef8992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ef899662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff719249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7192a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff719249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff719231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ef892bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ef892ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ef89108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ef85bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ef85bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff719232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7192330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7192330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ef85bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (848 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646a0bc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646a0bc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646a0bca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0543b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0543b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0543b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0543b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646a0b5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646a0b5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646a0b448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646a07f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646a07f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0543b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0543b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0543b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646a07f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563244b06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563244b03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563244b0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0389933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f038998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0389933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f038991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563244a9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563244a9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563244a818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563244730e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563244730b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f038991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f038991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f038991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563244730a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (850 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv # | ... # `---data was truncated (10240/255166) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a55034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a55031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a5503562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0200333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f020038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0200333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f020031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a54fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a54fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a54faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a54c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a54c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f020031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f020031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f020031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a54c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (851 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrinta_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frinta.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frinta.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrinta_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintam_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintm.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frintm.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrintm_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintn_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintn.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn me # | ... # `---data was truncated (10240/17932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557d63a0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d63a0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d63a0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9a971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d639a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d639a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d639898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d63638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d63638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9a971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d63638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (852 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a90b80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a90b7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a90b8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66fe71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a90b16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a90b16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a90afb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a907aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a907aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f66fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a907aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (853 of 27910) ******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | @con_unify_unimap_p1 = global ptr null, align 8 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @con_unify_unimap_q1() #0 { # | entry: # | %p.addr.i = alloca ptr, align 8 # | %q.addr.i = alloca ptr, align 8 # | %size.addr.i = alloca i64, align 8 # | %0 = load ptr, ptr @con_unify_unimap_p1, align 8 # | store ptr %0, ptr %p.addr.i, align 8 # | store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8 # | store i64 4, ptr %size.addr.i, align 8 # | %1 = load ptr, ptr %p.addr.i, align 8 # | %2 = load ptr, ptr %q.addr.i, align 8 # | %3 = load i64, ptr %size.addr.i, align 8 # | %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2 # | ret i32 %call.i # | } # | # | ; Function Attrs: alwaysinline nobuiltin nounwind # | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #2 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # | #0 0x000055f6893cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6893c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6893cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4941733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f494178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4941733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f494171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f689362bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f689362a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6893478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f688ff6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f688ff6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f494171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f494171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f494171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f688ff6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fa11a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fa11a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fa11a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5764449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5764449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5764431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fa113dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fa113da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fa11228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fa0dd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fa0dd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5764432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57644330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fa0dd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055705ded2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055705decfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055705ded362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecedea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecede31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055705de68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055705de68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055705de4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055705dafce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055705dafcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecede330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055705dafca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (856 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560aa0810eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560aa080de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560aa081162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c29133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c2918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c29133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c2911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560aa07a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560aa07a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560aa078b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560aa043ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560aa043ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c2911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c2911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c2911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560aa043aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (858 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (859 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055784f9edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055784f9eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055784f9ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7519733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f751978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7519733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f751971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055784f983bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055784f983a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055784f9688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055784f617e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055784f617b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f751971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f751971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f751971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055784f617a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056056cff6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056056cff3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056056cff762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d2dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d2dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d2dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d2dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056056cf8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056056cf8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056056cf718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056056cc20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056056cc20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d2dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d2dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d2dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056056cc20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (861 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603887c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603887c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603887c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe15a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe15a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe15a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe15a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056038875ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056038875ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603887438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603883f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603883f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe15a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe15a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe15a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603883f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/70971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564034d41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564034d3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564034d4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1599133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f159918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1599133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f159911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564034cd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564034cd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564034cbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056403496be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056403496bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f159911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f159911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f159911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056403496ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a39662beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a396628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a39662c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd99a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd99aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd99a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd99a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3965c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3965c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3965a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a396255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a396255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd99a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd99a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd99a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a396255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu # | ... # `---data was truncated (10240/156765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ea155beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ea1558e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ea155c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f799941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79994725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f799941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7999403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ea14f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ea14f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ea14d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ea1185e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ea1185b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7999404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79994050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79994050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ea1185a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (865 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl # | ... # `---data was truncated (10240/27434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d4b855eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d4b852e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d4b85662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28cf41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28cf4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28cf41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28cf403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d4b7ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d4b7eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d4b7d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d4b47fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d4b47fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28cf404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28cf4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28cf4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d4b47fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9dbce0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9dbcdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9dbce162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd54e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd54e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd54e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd54e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9dbc76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9dbc76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9dbc5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9db90ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9db90ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd54e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd54e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd54e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9db90aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/add.c (867 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %add.i = add <16 x i8> %2, %3 # | store <16 x i8> %add.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %add.i = add <8 x i16> %2, %3 # | store <8 x i16> %add.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b # | ... # `---data was truncated (10240/221881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000564e4c0f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e4c0ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e4c0f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2fd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2fd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2fd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2fd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e4c086bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e4c086a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e4c06b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e4bd1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e4bd1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2fd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2fd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2fd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e4bd1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (868 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005593d0571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593d056ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593d057262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f731a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f731a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f731a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f731a031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593d0507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593d0507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593d04ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593d019be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593d019bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f731a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f731a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f731a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593d019ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (869 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv2f64( undef, %2, %1) # | # | ... # `---data was truncated (10240/23662) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056402eee9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056402eee6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056402eeea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7587c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7587c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7587c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7587c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056402ee7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056402ee7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056402ee648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056402eb13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056402eb13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7587c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7587c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7587c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056402eb13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055710ef6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055710ef69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055710ef6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ca049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ca0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ca049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ca031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055710ef02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055710ef02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055710eee78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055710eb96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055710eb96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3ca032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ca0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ca0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055710eb96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i1 # | ... # `---data was truncated (10240/182173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ce0155eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ce0152e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ce015662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f564e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f564e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f564e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f564e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ce00ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ce00eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ce00d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cdfd7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cdfd7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f564e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f564e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f564e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cdfd7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/13625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e08ab3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e08ab37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e08ab3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d14649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d14649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d14631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e08aad0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e08aad0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e08aab58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e08a764e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e08a764b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d14632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d146330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e08a764a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (874 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %and = and <8 x i8> %2, %3 # | store <8 x i8> %and, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %and = and <8 x i64> %0, %1 # | store <8 x i64> %and, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (875 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595a11edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595a11eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595a11ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff971e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff971ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff971e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff971e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595a1183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595a1183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595a11688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595a0e17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595a0e17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff971e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff971e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff971e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595a0e17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (876 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bd73265eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd73262e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd7326662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f829db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f829db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f829db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f829daed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd731fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd731fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd731e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd72e8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd72e8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f829daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f829daef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f829daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd72e8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (877 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad43041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad4303ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad4304262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f55905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f5595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f55905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f558ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad42fd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad42fd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad42fbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad42c6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad42c6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f558eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f558ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f558ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad42c6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (878 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bbf947eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bbf944e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bbf94862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4204a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4204a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4204a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4204a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bbf8ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bbf8dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bbf8c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bbf571e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bbf571b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4204a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4204a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4204a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bbf571a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (880 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_s32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_s64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_u32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_u64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564978e43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564978e40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564978e4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65da933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65da98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65da933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65da91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564978dd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564978dd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564978dbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564978a6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564978a6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65da91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65da91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65da91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564978a6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6cab8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6cab88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6cab8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17e0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17e0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17e0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17e0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6cab21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6cab21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6cab068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6ca7b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6ca7b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17e0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17e0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17e0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6ca7b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (882 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @xor_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6edf3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6edf3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6edf3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff29b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff29b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff29b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff29b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6eded4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6eded4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6edeb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6edb68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6edb68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff29b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff29b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff29b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6edb68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (884 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; # | ... # `---data was truncated (10240/14699) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611c67a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611c679de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611c67a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0762849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0762849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0762831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611c6736bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611c6736a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611c671b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611c63cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611c63cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0762832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07628330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611c63caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558784fd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558784fd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558784fd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0c811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558784f6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558784f6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558784f528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558784c01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558784c01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0c811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558784c01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/12381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ac13d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ac13d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ac13da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff12721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1272725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff12721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff127203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ac136fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ac136fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ac13548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ac1003e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ac1003b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff127204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1272050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1272050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ac1003a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (887 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565a35d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565a35d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565a35d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f541d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f541d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f541d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f541d8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565a356abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565a356aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565a354f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565a31fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565a31feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f541d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f541d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f541d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565a31fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ea3653eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ea3650e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ea365462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe567533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe56758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe567533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe56751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ea35e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ea35e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ea35ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ea327de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ea327db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe56751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe56751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe56751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ea327da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056487d75deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056487d75ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056487d75e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff41c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff41c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff41c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff41c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056487d6f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056487d6f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056487d6d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056487d387e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056487d387b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff41c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff41c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff41c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056487d387a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e673225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e673222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e67322662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feabb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feabb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feabb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feabb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6731bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6731bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6731a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e672e4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e672e4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feabb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feabb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feabb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e672e4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/424041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a7008beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a70088e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a7008c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eeb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eeb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eeb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eeb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a70021bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a70021a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a700068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a6fcb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a6fcb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9eeb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eeb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eeb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a6fcb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6fc124eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6fc121e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6fc12562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbead933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbead98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbead933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbead91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6fc0babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6fc0baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6fc09f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6fbd4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6fbd4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbead91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbead91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbead91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6fbd4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (893 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4f32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2f64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005567e1d0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005567e1d08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567e1d0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32dd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32dd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32dd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32dd031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567e1ca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567e1ca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567e1c868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567e1935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567e1935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32dd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32dd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32dd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567e1935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (894 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_b( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | %x2.addr = alloca , align 2 # | %x4.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | store %x2, ptr %x2.addr, align 2 # | store %x4, ptr %x4.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = load , ptr %x2.addr, align 2 # | %3 = load , ptr %x4.addr, align 2 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564498596eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564498593e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056449859762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4201f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4201f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4201f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4201f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056449852cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056449852ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644985118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644981c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644981c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4201f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4201f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4201f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644981c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (895 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597190afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597190ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597190b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cb1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cb1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cb1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cb1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559719045bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559719045a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055971902a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559718cd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559718cd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cb1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cb1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cb1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559718cd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (896 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> # | ... # `---data was truncated (10240/63117) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055ac2f6f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac2f6f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac2f6f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f224c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f224c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f224c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f224c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac2f68bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac2f68ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac2f6708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac2f31fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac2f31fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f224c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f224c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f224c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac2f31fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (898 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 8) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 16) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 32) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 64) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %1, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, # | ... # `---data was truncated (10240/14353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e0fdecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0fdecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0fdece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbeba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbeba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbeba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbeba431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0fde63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0fde63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0fde488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0fdaf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0fdaf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbeba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbeba4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbeba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0fdaf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2d65adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2d65aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2d65ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7874933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f787498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7874933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f787491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2d6543bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2d6543a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2d65288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2d61d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2d61d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f787491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f787491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f787491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2d61d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (900 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055667116aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556671167e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055667116b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d0d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d0d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d0d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d0d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556671100bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556671100a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566710e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556670d94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556670d94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d0d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d0d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d0d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556670d94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (901 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c65f821eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c65f81ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c65f82262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9850249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98502a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9850249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9850231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c65f7b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c65f7b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c65f79c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c65f44be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c65f44bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9850232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98502330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98502330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c65f44ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa8832beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa88328e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa8832c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c37649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c37649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c37631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa882c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa882c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa882a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa87f55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa87f55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c37632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c376330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa87f55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (904 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfaf1adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfaf1aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfaf1ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f949a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f949a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f949a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f949a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfaf143bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfaf143a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfaf1288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfaedd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfaedd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f949a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f949a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f949a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfaedd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (906 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005580bce4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580bce48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580bce4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c10733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c1078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c10733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c1071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580bcde1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005580bcde1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580bcdc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580bca75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580bca75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c1071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c1071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c1071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580bca75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (907 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/15264) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005629b78d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629b78d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629b78d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c6ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c6ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c6ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c6ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629b786bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629b786ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629b78508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629b74ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629b74ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c6ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c6ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c6ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629b74ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055daa32f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055daa32f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055daa32f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faed3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faed378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faed3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faed371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055daa328cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055daa328ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055daa32718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055daa2f20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055daa2f20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faed371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faed371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faed371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055daa2f20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde # | ... # `---data was truncated (10240/16083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f84d34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f84d31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f84d3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c90333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c9038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c90333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c9031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f84ccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f84ccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f84caf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f8495ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f8495eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c9031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c9031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c9031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f8495ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (910 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc59b3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc59b38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc59b3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef7af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef7af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef7af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef7af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc59ad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc59ad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc59ab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc59765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc59765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef7af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef7af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef7af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc59765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (911 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564494c99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564494c96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564494c9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb049b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb049b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb049b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb049b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564494c2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564494c2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564494c148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644948c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644948c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb049b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb049b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb049b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644948c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (912 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.ad # | ... # `---data was truncated (10240/17434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f7e6c93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7e6c90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7e6c9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46cf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46cf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46cf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46cf831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7e6c29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7e6c29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7e6c0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7e68bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7e68bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46cf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46cf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46cf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7e68bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (913 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (915 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056058f65ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056058f659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056058f65d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b19b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b19b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b19b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b19b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056058f5f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056058f5f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056058f5d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056058f286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056058f286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b19b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b19b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b19b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056058f286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (916 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %v, ptr %v.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | declare void @g(<1 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_cst(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %vecext = extractelement <16 x i8> %0, i32 3 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # | #0 0x00005568efee8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568efee5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568efee962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc836b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc836b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc836b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc836b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568efe7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568efe7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568efe638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568efb12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568efb12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc836b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc836b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc836b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568efb12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dc5ce6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dc5ce3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dc5ce762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6cb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6cb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6cb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6cb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dc5c7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dc5c7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dc5c618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dc5910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dc5910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6cb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6cb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6cb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dc5910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv64i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr # | ... # `---data was truncated (10240/26240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0f276ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0f2769e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0f276d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f287c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f287c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f287c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f287c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0f2702bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0f2702a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0f26e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0f2396e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0f2396b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f287c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f287c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f287c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0f2396a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (920 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560efe8b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560efe8b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560efe8b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0856133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f085618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0856133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f085611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560efe849bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560efe849a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560efe82e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560efe4dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560efe4ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f085611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f085611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f085611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560efe4dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (921 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a18c5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a18c59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a18c5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9a1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9a1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9a1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9a1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a18bf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a18bf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a18bd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a18886e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a18886b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9a1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9a1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9a1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a18886a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (922 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/poly128.c (923 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | ret i128 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__s1 = alloca i128, align 16 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | store i128 %4, ptr %__s1, align 16 # | %5 = load ptr, ptr %ptr.addr, align 8 # | %add.ptr = getelementptr inbounds i128, ptr %5, i64 1 # | %6 = load i128, ptr %__s1, align 16 # | store i128 %6, ptr %add.ptr, align 16 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca i128, align 16 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load i64, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3) # | %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128 # | store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16 # | %4 = load i128, ptr %ref.tmp.i, align 16 # | store i128 %4, ptr %__ret.i, align 16 # | %5 = load i128, ptr %__ret.i, align 16 # | ret i128 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { # | entry: # | %__p0.addr.i3 = alloca <2 x i64>, align 16 # | %__ret.i4 = alloca <1 x i64>, align 8 # | %__p0.addr.i1 = alloca <2 x i64>, align 16 # | %__ret.i2 = alloca <1 x i64>, align 8 # | %__p0.addr.i.i = alloca i64, align 8 # | %__p1.addr.i.i = alloca i64, align 8 # | %__ret.i.i = alloca i128, align 16 # | %ref.tmp.i.i = alloca i128, align 16 # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %ref.tmp1.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %2, ptr %__p0.addr.i3, align 16 # | %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> # | store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8 # | %5 = load <1 x i64>, ptr %__ret.i4, align 8 # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load i64, ptr %ref.tmp.i, align 8 # | %7 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | store <2 x i64> %7, ptr %__p0.addr.i1, align 16 # | %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8 # | %10 = load <1 x i64>, ptr %__ret.i2, align 8 # | store <1 x i64> %10, ptr %ref.tmp1.i, align 8 # | %11 = load i64, ptr %ref.tmp1.i, align 8 # | store i64 %6, ptr %__p0.addr.i.i, align 8 # | store i64 %11, ptr %__p1.addr.i.i, align 8 # | %12 = load i64, ptr %__p0.addr.i.i, align 8 # | %13 = load i64, ptr %__p1.addr.i.i, align 8 # | %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13) # | %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128 # | store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16 # | %14 = load i128, ptr %ref.tmp.i.i, align 16 # | store i128 %14, ptr %__ret.i.i, align 16 # | %15 = load i128, ptr %__ret.i.i, align 16 # | store i128 %15, ptr %__ret.i, align 16 # | %16 = load i128, ptr %__ret.i, align 16 # | ret i128 %16 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.ad # | ... # `---data was truncated (10240/19795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ee1fc4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee1fc47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee1fc4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99c9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee1fbe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee1fbe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee1fbc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee1f874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee1f874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99c9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee1f874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x # | ... # `---data was truncated (10240/164783) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb9a85aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb9a857e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb9a85b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70acc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70acca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70acc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70acc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb9a7f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb9a7f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb9a7d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb9a484e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb9a484b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70acc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70acc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70acc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb9a484a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8d00dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8d00d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8d00dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50ebe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50ebea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50ebe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50ebe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8d0071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8d0071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8d00568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8cfd05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8cfd05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50ebe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50ebe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50ebe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8cfd05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/58460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582e6caceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582e6ca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582e6cad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff003f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff003f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff003f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff003f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582e6c42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582e6c42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582e6c278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582e68d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582e68d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff003f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff003f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff003f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582e68d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (927 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056257d416eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056257d413e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056257d41762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b18c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b18c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b18c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b18c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056257d3acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056257d3aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056257d3918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056257d040e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056257d040b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b18c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b18c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b18c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056257d040a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (929 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (930 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df564d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df564cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df564d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8abe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8abe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8abe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8abe031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df56468bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df56468a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df5644d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df560fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df560fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8abe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8abe0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8abe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df560fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (931 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561532469eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561532466e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056153246a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda87533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda8758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda87533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda8751b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615323ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615323ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615323e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561532093e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561532093b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda8751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda8751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda8751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561532093a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/94157) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578d73bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578d73b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578d73bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd667933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd66798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd667933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd66791b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578d7352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578d7352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578d73378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578d6fe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578d6fe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd66791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd66791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd66791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578d6fe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (933 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa5396eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa5396be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa5396f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eac81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eac8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eac81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eac803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa53904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa53904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa538e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa53598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa53598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9eac804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eac8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eac8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa53598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4b6484eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4b6481e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4b648562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a79933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a7998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a79933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a7991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4b641abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4b641aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4b63ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4b60aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4b60aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a7991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a7991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a7991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4b60aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | # | ... # `---data was truncated (10240/169917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e9ad0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e9ad0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e9ad0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8922a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8922aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8922a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8922a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e9aca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e9aca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e9ac898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e9a938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e9a938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8922a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8922a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8922a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e9a938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloc # | ... # `---data was truncated (10240/27533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5f1ff3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5f1ff0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5f1ff462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4027e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4027ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4027e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4027e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5f1f89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5f1f89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5f1f6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5f1c1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5f1c1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4027e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4027e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4027e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5f1c1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (937 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568bcb92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568bcb8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568bcb9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d57249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d572a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d57249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d57231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568bcb28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568bcb28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568bcb0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568bc7bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568bc7bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d57232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d572330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d572330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568bc7bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (938 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da30159eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da30156e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da3015a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f395bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f395bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f395bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f395beed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da300efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da300efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da300d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da2fd83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da2fd83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f395beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f395beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f395beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da2fd83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (939 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d631953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d631950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d63195462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6a3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6a3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6a3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6a3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6318e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6318e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6318ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d63157de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d63157db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6a3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6a3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6a3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d63157da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (940 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555733ffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555733ff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555733ffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92bb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92bb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92bb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92bb603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555733f91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555733f91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555733f768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555733c25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555733c25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f92bb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92bb6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92bb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555733c25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (941 of 27910) ******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | %struct.S = type { ptr, ptr } # | %struct.T = type { [2 x ptr] } # | %struct.SS = type { ptr } # | # | @__hip_cuid_ = addrspace(1) global i8 0 # | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4 # | %1 = load i32, ptr %0, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 { # | entry: # | %x.addr = alloca ptr addrspace(2), align 8, addrspace(5) # | %y.addr = alloca ptr addrspace(1), align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr # | store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8 # | store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8 # | %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0 # | %1 = load i32, ptr addrspace(2) %arrayidx, align 4 # | %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8 # | %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0 # | store i32 %1, ptr addrspace(1) %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline nounwind # | define dso_local void @_Z4funcPi(ptr noundef %x) #1 { # | entry: # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr %x, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 { # | entry: # | %s = alloca %struct.S, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %s.ascast = addrspacecast ptr addrspace(5) %s to ptr # | %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1 # | %3 = load ptr, ptr %y, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %4, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 { # | entry: # | %s = alloca ptr, align 8, addrspace(5) # | %s.addr = alloca ptr, align 8, addrspace(5) # | %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr # | store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8 # | %s1 = load ptr, ptr addrspace(5) %s, align 8 # | store ptr %s1, ptr %s.addr.ascast, align 8 # | %0 = load ptr, ptr %s.addr.ascast, align 8 # | %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %3 = load ptr, ptr %s.addr.ascast, align 8 # | %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1 # | %4 = load ptr, ptr %y, align 8 # | %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0 # | %5 = load float, ptr %arrayidx2, align 4 # | %add = fadd contract float %5, 1.000000e+00 # | store float %add, ptr %arrayidx2, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 { # | entry: # | %t = alloca %struct.T, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %t.ascast = addrspacecast ptr addrspace(5) %t to ptr # | %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0 # | %1 = load ptr, ptr %arrayidx, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0 # | %2 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %2, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1 # | %3 = load ptr, ptr %arrayidx3, align 8 # | %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx4, align 4 # | %add5 = fadd contract float %4, 2.000000e+00 # | store float %add5, ptr %arrayidx4, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 { # | entry: # | %a = alloca %struct.SS, align 8, addrspace(5) # | %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0 # | store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8 # | %a.ascast = addrspacecast ptr addrspace(5) %a to ptr # | %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0 # | %0 = load ptr, ptr %x, align 8 # | %1 = load float, ptr %0, align 4 # | %add = fadd contract float %1, 3.000000e+00 # | store float %add, ptr %0, align 4 # | ret void # | } # | # | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !2 = !{!"clang version 24.0.0"} # | !3 = !{} # | !4 = !{i64 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x000055f5bb1cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5bb1c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5bb1cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46f691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5bb162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5bb162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5bb1478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5badf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5badf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46f691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5badf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (942 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ff5a15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ff5a12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ff5a1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61fb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61fb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61fb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61fb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ff59abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ff59aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ff59908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ff563fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ff563fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61fb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61fb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61fb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ff563fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (944 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e472ef3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e472ef0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e472ef462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2989f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2989f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2989f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2989eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e472e89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e472e89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e472e6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e472b1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e472b1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2989eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2989eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2989eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e472b1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055835daf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055835daefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055835daf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa422d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa422d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa422d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa422d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055835da88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055835da88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055835da6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055835d71ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055835d71cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa422d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa422d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa422d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055835d71ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0f5b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0f5b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0f5b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad9e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad9e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad9e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad9e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0f5ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0f5ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0f5ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0f5766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0f5766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad9e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad9e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad9e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0f5766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (949 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/151253) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a50a8b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a50a8aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a50a8b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56b4505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56b455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56b4505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56b44ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a50a847bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a50a847a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a50a82c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a50a4dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a50a4dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56b44eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56b44ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56b44ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a50a4dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (950 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d97b2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d97b2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d97b2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77dfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77dfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77dfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77dfc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d97ac4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d97ac4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d97aa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d97758e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d97758b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77dfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77dfc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77dfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d97758a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/builtins-arm.c (951 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-unknown-unknown-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @f0() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | %b.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load ptr, ptr %b.addr, align 4 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf0(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtr.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf1(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtru.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd0(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtr.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd1(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtru.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 0, ptr %res, align 4 # | store volatile i32 1, ptr %res, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_barrier() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | call void @llvm.arm.dsb(i32 2) # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch(i32 noundef %i) #0 { # | entry: # | %i.addr = alloca i32, align 4 # | store i32 %i, ptr %i.addr, align 4 # | call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp() #0 { # | entry: # | call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp2() #0 { # | entry: # | call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc2() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr2(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_lo # | ... # `---data was truncated (10240/15632) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd530bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd530bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd530be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22b0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22b058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22b0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22b051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd53053bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd53053a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd530388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd52ce7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd52ce7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22b051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22b051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22b051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd52ce7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (952 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i) # | %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8> # | store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %6, ptr %__ret.i, align 8 # | %7 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %acc, ptr %acc.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %acc.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float> # | %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float> # | %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float> # | %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i) # | %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8> # | store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %lhs.addr = alloca <8 x half>, align 16 # | %rhs.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %lhs, ptr %lhs.addr, align 16 # | store <8 x half> %rhs, ptr %rhs.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %lhs.addr, align 16 # | %2 = load <8 x half>, ptr %rhs.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half> # | %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half> # | %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half> # | %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i) # | %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8> # | store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %lhs.addr = alloca <4 x float>, align 16 # | %rhs.addr = alloca <4 x float>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <4 x float> %lhs, ptr %lhs.addr, align 16 # | store <4 x float> %rhs, ptr %rhs.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <4 x float>, ptr %lhs.addr, align 16 # | %2 = load <4 x float>, ptr %rhs.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float> # | %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float> # | %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float> # | %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i) # | %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8> # | store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <2 x double>, align 16 # | %lhs.addr = alloca <2 x double>, align 16 # | %rhs.addr = alloca <2 x double>, align 16 # | store <2 x double> %acc, ptr %acc.addr, align 16 # | store <2 x double> %lhs, ptr %lhs.addr, align 16 # | store <2 x double> %rhs, ptr %rhs.addr, align 16 # | %0 = load <2 x double>, ptr %acc.addr, align 16 # | %1 = load <2 x double>, ptr %lhs.addr, align 16 # | %2 = load <2 x double>, ptr %rhs.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double> # | %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double> # | %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double> # | %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i) # | %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8> # | store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16 # | %6 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %6, ptr %__ret.i, align 16 # | %7 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v # | ... # `---data was truncated (10240/166298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # | #0 0x00005644ec048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644ec045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644ec04962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8463649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84636a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8463649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8463631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644ebfdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644ebfdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644ebfc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644ebc72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644ebc72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8463632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84636330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84636330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644ebc72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654a4b82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654a4b7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654a4b8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a9f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a9f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a9f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a9f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654a4b18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654a4b18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654a4afd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654a47ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654a47acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a9f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a9f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a9f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654a47aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e88072eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e8806fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e8807362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59ad449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59ad4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59ad449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59ad431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e88008bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e88008a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e87fed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e87c9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e87c9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59ad432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59ad4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59ad4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e87c9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (955 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaa46a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eaa46a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eaa46a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60d5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60d5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60d5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60d5a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaa463cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eaa463ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eaa46218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eaa42d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eaa42d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60d5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60d5a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60d5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaa42d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (956 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557881b4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557881b47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557881b4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d78c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d78ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d78c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d78c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557881ae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557881ae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557881ac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557881774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557881774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d78c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d78c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d78c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557881774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-cde-vfp.c (957 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 { # | entry: # | %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11) # | %1 = bitcast float %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %m.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = load i32, ptr %m.addr, align 4 # | %5 = bitcast i32 %4 to float # | %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5) # | %7 = bitcast float %6 to i32 # | ret i32 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 { # | entry: # | %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11) # | %1 = bitcast double %0 to i64 # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %m.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = load i64, ptr %m.addr, align 8 # | %5 = bitcast i64 %4 to double # | %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5) # | %7 = bitcast double %6 to i64 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635be203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635be200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635be20462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb982505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb98255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb982505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9824ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635be199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635be199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635be17e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635bde2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635bde2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9824eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9824ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9824ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635bde2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (958 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | % # | ... # `---data was truncated (10240/201226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9f1589eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9f1586e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9f158a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cbd41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cbd4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cbd41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cbd403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9f151fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9f151fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9f15048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9f11b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9f11b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cbd404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cbd4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cbd4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9f11b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (959 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svminnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005614bcc99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614bcc96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614bcc9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f847cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f847cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f847cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f847cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614bcc2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614bcc2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614bcc148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614bc8c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614bc8c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f847cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f847cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f847cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614bc8c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bc8264eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bc8261e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bc826562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc8c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc8c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc8c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc8c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bc81fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bc81faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bc81df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bc7e8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bc7e8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc8c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc8c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc8c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bc7e8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/78328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d773f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d773f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d773f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f790af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f790af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f790af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f790af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d77389bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d77389a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d7736e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d7701de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d7701db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f790af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f790af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f790af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d7701da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a334f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a334f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a334f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d72733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d7278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d72733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d7271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a3348cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a3348ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a334718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a33120e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a33120b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d7271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d7271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d7271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a33120a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (963 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583945d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583945d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583945d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c24449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c24449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c24431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558394569bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558394569a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055839454e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583941fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583941fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c24432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583941fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a09682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a0967fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a0968362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35c3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35c34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35c3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35c3431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a09618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a09618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a095fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a092ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a092acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35c3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35c34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35c34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a092aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (965 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cd16f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cd16f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cd16f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe943933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe94398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe943933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe94391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cd1689bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cd1689a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cd166e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cd131de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cd131db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe94391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe94391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe94391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cd131da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bffc89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bffc86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bffc8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8083a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8083aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8083a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8083a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bffc1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bffc1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bffc048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bff8b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bff8b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8083a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8083a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8083a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bff8b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e5735aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e57357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e5735b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0df8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0df80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0df8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0df8031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e572f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e572f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e572d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e56f84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e56f84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0df8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0df80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0df80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e56f84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (971 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, %1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (972 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056116cb3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056116cb38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056116cb3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedaf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedaf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedaf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedaf631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056116cad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056116cad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056116cab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056116c765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056116c765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fedaf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedaf6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedaf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056116c765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv. # | ... # `---data was truncated (10240/16654) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cfcad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cfcad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cfcada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9383649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9383649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9383631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cfca6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cfca6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cfca548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cfc703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cfc703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9383632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93836330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cfc703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (974 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3f619feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3f619ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3f61a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8490133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f849018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8490133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f849011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3f6135bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3f6135a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3f611a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3f5dc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3f5dc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f849011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f849011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f849011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3f5dc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (976 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (977 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596abc23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596abc20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596abc2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e95649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e956a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e95649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e95631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596abbb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596abbb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596abb9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596ab84de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596ab84db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e95632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e956330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e956330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596ab84da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a71f868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a71f865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a71f86962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bb1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bb158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bb1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bb151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a71f7febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a71f7fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a71f7e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a71f492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a71f492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bb151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bb151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bb151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a71f492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (979 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625ffbc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625ffbc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625ffbc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9a291b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625ffb5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625ffb5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625ffb3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625ff7eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625ff7eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9a291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625ff7eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560acc155eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560acc152e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560acc15662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cac71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560acc0ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560acc0eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560acc0d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560acbd7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560acbd7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cac71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560acbd7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, a # | ... # `---data was truncated (10240/30276) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055687f2b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055687f2b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055687f2b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cfbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cfbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cfbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cfbeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055687f24dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055687f24da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055687f2328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055687eee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055687eee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cfbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cfbeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cfbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055687eee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d98185eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d98182e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d9818662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cb2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cb2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cb2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cb2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d9811bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d9811ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d981008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d97dafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d97dafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9cb2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cb2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cb2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d97dafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (985 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fc1ef5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fc1ef2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fc1ef662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42fea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42feaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42fea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42fea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fc1e8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fc1e8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fc1e708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fc1b1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fc1b1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42fea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42fea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42fea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fc1b1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (986 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cls.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/11769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a345d01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a345cfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a345d0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b6ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b6ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b6ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b6ac03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a345c97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a345c97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a345c7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a34592be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a34592bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b6ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b6ac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b6ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a34592ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (987 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1) # | store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.fptosi.sat.i64.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | st # | ... # `---data was truncated (10240/53064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b7b270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b7b26de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b7b27162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ad7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ad7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ad7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ad7ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b7b206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b7b206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b7b1eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b7ae9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b7ae9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ad7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ad7cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ad7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b7ae9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (988 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e83ccb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e83ccb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e83ccb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2b6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2b698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2b6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2b691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e83cc4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e83cc4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e83cc318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e83c8e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e83c8e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2b691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2b691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2b691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e83c8e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (989 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 { # | entry: # | %__p0_824.addr.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8 # | store <4 x i16> %1, ptr %__s0.i, align 8 # | %2 = load <8 x i8>, ptr %__s0.i, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | %4 = zext <4 x i16> %3 to <4 x i32> # | %vshll_n.i = shl <4 x i32> %4, splat (i32 16) # | store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16 # | %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %5, ptr %__ret.i, align 16 # | %6 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %6, ptr %tmp.i, align 16 # | %7 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %7, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret_824.i, align 16 # | %9 = load <4 x float>, ptr %__ret_824.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | store <4 x bfloat> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8 # | store <4 x bfloat> %4, ptr %__ret.i, align 8 # | %5 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> # | store <8 x bfloat> %4, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %inactive.addr = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <8 x bfloat> %inactive, ptr %inactive.addr, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %inactive.addr, align 16 # | %1 = load <4 x float>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x bfloat> # | %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = fptrunc <4 x float> %6 to <4 x bfloat> # | %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> # | store <8 x bfloat> %8, ptr %ref.tmp.i, align 16 # | %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca bfloat, align 2 # | %ref.tmp.i = alloca bfloat, align 2 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | store bfloat %2, ptr %ref.tmp.i, align 2 # | %3 = load bfloat, ptr %ref.tmp.i, align 2 # | store bfloat %3, ptr %__ret.i, align 2 # | %4 = load bfloat, ptr %__ret.i, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca i32, align 4 # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load # | ... # `---data was truncated (10240/10974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561131203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561131200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056113120462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f940f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f940f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f940f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f940f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561131199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561131199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056113117e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561130e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561130e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f940f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f940f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f940f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561130e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591ecc3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591ecc3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591ecc3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b40f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b40f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b40f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b40f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591ecbd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591ecbd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591ecbb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591ec867e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591ec867b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b40f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b40f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b40f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591ec867a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (991 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056545928feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056545928ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056545929062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b16133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b1618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b16133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b1611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565459225bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565459225a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056545920a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565458eb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565458eb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b1611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b1611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b1611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565458eb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (992 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c228cf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c228cf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c228cf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94b3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c228c8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c228c8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c228c6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c22891ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c22891eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c22891ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/andv.c (993 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.andv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.andv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.andv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.andv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x000055d290d15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d290d12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d290d1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8831f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8831f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8831f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8831f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d290cabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d290caba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d290c908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d29093fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d29093fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8831f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8831f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8831f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d29093fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e46b91deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e46b91ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e46b91e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe03661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0366725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe03661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe036603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e46b8b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e46b8b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e46b8988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e46b547e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e46b547b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe036604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0366050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0366050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e46b547a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d539a0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d539a0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d539a0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd605649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd605649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd605631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5399a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5399a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5399898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d539638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d539638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd605632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6056330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d539638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cfa68beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cfa688e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cfa68c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fd7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fd778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fd7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fd771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cfa621bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cfa621a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cfa6068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cfa2b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cfa2b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fd771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fd771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fd771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cfa2b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (997 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8b0708eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8b0705e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8b070962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32f2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32f22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32f2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32f2231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8b069ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8b069ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8b06838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8b0332e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8b0332b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32f2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32f22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32f22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8b0332a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056438b4deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056438b4dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056438b4df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0cef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0cef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0cef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0ceeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056438b474bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056438b474a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056438b4598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056438b108e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056438b108b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0ceeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0ceeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0ceeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056438b108a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (1000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e6199eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646e6196e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646e619a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa249733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa24978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa249733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa24971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e612fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646e612fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646e61148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646e5dc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646e5dc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa24971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa24971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa24971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e5dc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (1001 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cc269eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cc269be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cc269f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b24a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b24aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b24a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b24a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc2634bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cc2634a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cc26198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cc22c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cc22c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b24a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b24a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b24a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc22c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e01a97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e01a94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e01a9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2113a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2113aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2113a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2113a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e01a2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e01a2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e01a128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e016c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e016c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2113a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2113a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2113a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e016c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (1003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/410391) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aef92eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559aef92be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559aef92f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffae721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffae72725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffae721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffae7203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aef8c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559aef8c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559aef8a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559aef558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559aef558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffae7204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffae72050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffae72050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559aef558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (1004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636db4afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636db4ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636db4b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64cbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64cbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64cbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64cbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636db445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636db445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636db42a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636db0d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636db0d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f64cbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64cbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64cbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636db0d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (1005 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.clz.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.clz.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (1006 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %4, ptr %__ret.i, align 16 # | %5 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %5, ptr %__ret.i, align 16 # | %6 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i # | ... # `---data was truncated (10240/23350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055ce2a01deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce2a01ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce2a01e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb09333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb0938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb09333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb0931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce29fb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce29fb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce29f988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce29c47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce29c47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb0931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb0931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb0931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce29c47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/perm.c (1007 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, # | ... # `---data was truncated (10240/231562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055a82f1fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a82f1f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a82f1fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a82f191bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a82f191a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a82f1768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a82ee25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a82ee25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a82ee25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (1008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055728ce5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055728ce5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055728ce5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee1f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee1f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee1f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee1f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055728cdf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055728cdf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055728cdd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055728ca88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055728ca88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee1f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee1f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee1f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055728ca88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (1009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556512f1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556512f19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556512f1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fedb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fedb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fedb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fedb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556512eb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556512eb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556512e978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556512b46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556512b46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fedb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fedb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fedb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556512b46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (1010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwi # | ... # `---data was truncated (10240/235604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055652f378eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055652f375e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055652f37962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3aca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3aca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3aca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3aca91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055652f30ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055652f30ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055652f2f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055652efa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055652efa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3aca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3aca91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3aca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055652efa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (1011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (1012 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9c3efceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9c3ef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9c3efd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feecb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feecb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feecb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feecb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9c3e92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9c3e92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9c3e778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9c3b26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9c3b26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feecb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feecb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feecb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9c3b26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm64_vcopy.c (1013 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_336 = alloca <16 x i8>, align 16 # | %__s0_336 = alloca <16 x i8>, align 16 # | %__s2_336 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_336, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_336, align 16 # | %2 = load <16 x i8>, ptr %__s2_336, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_336, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_336, align 16 # | %13 = load <16 x i8>, ptr %__ret_336, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_328 = alloca <16 x i8>, align 16 # | %__s0_328 = alloca <16 x i8>, align 16 # | %__s2_328 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_328, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_328, align 16 # | %2 = load <16 x i8>, ptr %__s2_328, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_328, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_328, align 16 # | %13 = load <16 x i8>, ptr %__ret_328, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_346 = alloca <8 x i16>, align 16 # | %__s0_346 = alloca <8 x i16>, align 16 # | %__s2_346 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_346, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_346, align 16 # | %2 = load <8 x i16>, ptr %__s2_346, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_346, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_346, align 16 # | %13 = load <8 x i16>, ptr %__ret_346, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_334 = alloca <8 x i16>, align 16 # | %__s0_334 = alloca <8 x i16>, align 16 # | %__s2_334 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_334, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_334, align 16 # | %2 = load <8 x i16>, ptr %__s2_334, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_334, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_334, align 16 # | %13 = load <8 x i16>, ptr %__ret_334, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <4 x i32>, align 16 # | %a2.addr = alloca <4 x i32>, align 16 # | %__ret_340 = alloca <4 x i32>, align 16 # | %__s0_340 = alloca <4 x i32>, align 16 # | %__s2_340 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca i32, align 4 # | %__ret1 = alloca i32, align 4 # | %__s02 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp3 = alloca <4 x i32>, align 16 # | %tmp4 = alloca <4 x i32>, align 16 # | %tmp5 = alloca <4 x i32>, align 16 # | store <4 x i32> %a1, ptr %a1.addr, align 16 # | store <4 x i32> %a2, ptr %a2.addr, align 16 # | %0 = load <4 x i32>, ptr %a1.addr, align 16 # | store <4 x i32> %0, ptr %__s0_340, align 16 # | %1 = load <4 x i32>, ptr %a2.addr, align 16 # | store <4 x i32> %1, ptr %__s2_340, align 16 # | %2 = load <4 x i32>, ptr %__s2_340, align 16 # | store <4 x i32> %2, ptr %__s02, align 16 # | %3 = load <4 x i32>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <4 x i32> %3, i32 3 # | store i32 %vgetq_lane, ptr %ref.tmp, align 4 # | %4 = load i32, ptr %ref.tmp, align 4 # | store i32 %4, ptr %__ret1, align 4 # | %5 = load i32, ptr %__ret1, align 4 # | store i32 %5, ptr %tmp, align 4 # | %6 = load i32, ptr %tmp, align 4 # | store i32 %6, ptr %__s0, align 4 # | %7 = load <4 x i32> # | ... # `---data was truncated (10240/22011) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b4b386eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b4b383e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b4b38762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46fd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46fd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46fd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46fd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b4b31cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b4b31ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b4b3018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b4afb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b4afb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46fd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46fd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46fd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b4afb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (1014 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.i6 # | ... # `---data was truncated (10240/18619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b668418eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b668415e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b66841962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b8cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b8cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b8cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b8cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6683aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6683aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6683938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b668042e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b668042b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b8cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b8cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b8cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b668042a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (1015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/151245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b60646feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b60646ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b60647062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd408e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd408e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd408e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd408e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b606405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b606405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6063ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b606099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b606099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd408e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd408e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd408e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b606099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (1016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581583d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581583d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581583d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd896849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd896849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd896831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055815836ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055815836ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581583538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558158002e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558158002b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd896832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558158002a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a0bf54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a0bf51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a0bf5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb88dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb88dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb88dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb88dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a0beeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a0beeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a0becf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a0bb7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a0bb7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb88dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb88dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb88dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a0bb7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (1018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector. # | ... # `---data was truncated (10240/78690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6bd780eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6bd77de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6bd78162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15ed449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15ed4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15ed449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15ed431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6bd716bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6bd716a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6bd6fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6bd3aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6bd3aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15ed432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15ed4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15ed4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6bd3aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (1019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/68141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fa144aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fa1447e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fa144b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33eae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33eaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33eae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33eae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fa13e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fa13e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fa13c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fa1074e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fa1074b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33eae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33eae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33eae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fa1074a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (1020 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1021 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, a # | ... # `---data was truncated (10240/81515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056120c422eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056120c41fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056120c42362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23fc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23fc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23fc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23fc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056120c3b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056120c3b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056120c39d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056120c04ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056120c04cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23fc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23fc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23fc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056120c04ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (1022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564df9a89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564df9a86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564df9a8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65aa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65aa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65aa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65aa231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564df9a1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564df9a1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564df9a048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564df96b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564df96b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65aa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65aa2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65aa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564df96b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (1023 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (1024 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f857eb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f857eb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f857eb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea8881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea888725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea8881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea88803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f857e4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f857e4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f857e318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f857ae0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f857ae0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea88804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea888050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea888050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f857ae0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (1025 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %v # | ... # `---data was truncated (10240/86747) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca8d251eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca8d24ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca8d25262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa64c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa64c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa64c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa64c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca8d1e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca8d1e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca8d1cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca8ce7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca8ce7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa64c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa64c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa64c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca8ce7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (1026 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (1027 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f272874eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f272871e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f27287562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0919f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0919f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0919f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0919f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f27280abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f27280aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2727ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f27249ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f27249eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0919f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0919f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0919f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f27249ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (1028 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582e362aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582e3627e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582e362b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4aea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4aea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4aea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4aea431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582e35c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582e35c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582e35a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582e3254e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582e3254b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4aea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4aea4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4aea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582e3254a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (1029 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da868caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da868c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da868cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03cb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da86860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da86860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da868458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da864f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da864f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da864f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (1030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581a4976eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581a4973e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581a497762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3856133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f385618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3856133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f385611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581a490cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581a490ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581a48f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581a45a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581a45a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f385611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f385611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f385611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581a45a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (1031 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4e455deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4e455ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4e455e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff724d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff724d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff724d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff724d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4e44f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4e44f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4e44d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4e4187e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4e4187b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff724d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff724d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff724d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4e4187a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (1032 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) # | ... # `---data was truncated (10240/68437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056197a6eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056197a6e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056197a6ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1eb3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1eb398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1eb3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1eb391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056197a682bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056197a682a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056197a6678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056197a316e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056197a316b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1eb391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1eb391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1eb391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056197a316a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (1033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b736bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b736b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b736bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec99249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec99249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec99231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b73651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b73651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b736368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b732e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b732e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec99232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec992330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b732e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (1034 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (1035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (1036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d009108eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d009105e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d00910962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f309a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f309a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f309a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f309a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d00909ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d00909ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0090838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d008d32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d008d32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f309a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f309a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f309a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d008d32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (1037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da868a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da8689fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da868a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc74ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da86838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da86838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da8681d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da864cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da864ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bc74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc74ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da864cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (1038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (1039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = c # | ... # `---data was truncated (10240/207083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c18978eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c18975e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c1897962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a37905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a3795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a37905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a378ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c1890ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c1890ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c188f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c185a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c185a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a378eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a378ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a378ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c185a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (1040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056217a332eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056217a32fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056217a33362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85b2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85b2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85b2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85b2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056217a2c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056217a2c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056217a2ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562179f5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562179f5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85b2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85b2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85b2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562179f5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (1041 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/65723) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056545e4ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056545e4fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056545e50062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4126d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4126d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4126d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4126d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056545e495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056545e495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056545e47a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056545e129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056545e129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4126d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4126d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4126d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056545e129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (1042 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, a # | ... # `---data was truncated (10240/18875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575a510ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575a5109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575a510d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0b2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0b295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0b2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0b28ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575a50a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575a50a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575a50878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575a4d36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575a4d36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0b28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0b28ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0b28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575a4d36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1043 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (1044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | # | ... # `---data was truncated (10240/43478) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c74743eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c74740e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c7474462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa27e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa27e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa27e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa27e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c746d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c746d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c746be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c7436de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c7436db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa27e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa27e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa27e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c7436da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (1045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (1046 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2e42f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2e42efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2e42f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2aa1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2aa1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2aa1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2aa1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2e4288bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2e4288a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2e426d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2e3f1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2e3f1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2aa1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2aa1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2aa1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2e3f1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (1047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (1048 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 2, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 3, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056400d379eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056400d376e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056400d37a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfe9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfe958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfe9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfe951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056400d30fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056400d30fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056400d2f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056400cfa3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056400cfa3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfe951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfe951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfe951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056400cfa3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (1049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3a6472eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3a646fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3a647362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19f4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19f478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19f4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19f471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3a6408bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3a6408a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3a63ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3a609ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3a609cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19f471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19f471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19f471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3a609ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (1050 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565ddc4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565ddc48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565ddc4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f246cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f246cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f246cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f246cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565ddbe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565ddbe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565ddbc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565dd875e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565dd875b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f246cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f246cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f246cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565dd875a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f971970eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f97196de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f97197162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff127c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff127ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff127c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff127c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f971906bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f971906a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9718eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f97159ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f97159ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff127c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff127c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff127c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f97159aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (1052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (1054 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562f6d08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562f6d05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562f6d0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562f6c9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562f6c9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562f6c838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562f6932e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562f6932b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562f6932a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (1055 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | defin # | ... # `---data was truncated (10240/13035) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a73aa7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a73aa7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a73aa7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab61733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab6178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab61733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab6171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a73aa14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a73aa14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a73a9f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a73a6a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a73a6a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab6171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab6171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab6171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a73a6a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (1056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559090fd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559090fcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559090fd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba72249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba72249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba72231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559090f66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559090f66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559090f4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559090bfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559090bfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba72232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba722330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559090bfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (1057 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d326adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d326aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d326ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9ec533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9ec58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9ec533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9ec51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d32643bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d32643a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d326288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d322d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d322d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9ec51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9ec51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9ec51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d322d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (1058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloc # | ... # `---data was truncated (10240/71123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055704e5feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055704e5fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055704e5ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d88f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d88f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d88f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d88f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055704e594bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055704e594a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055704e5798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055704e228e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055704e228b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d88f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d88f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d88f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055704e228a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (1059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (1060 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to double # | %7 = bitcast <8 x i8> %4 to double # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %extract = extractelement <2 x double> %8, i32 0 # | %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | %10 = bitcast double %9 to <1 x double> # | store <1 x double> %10, ptr %ref.tmp, align 8 # | %11 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %11, ptr %__ret, align 8 # | %12 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %12, ptr %tmp, align 8 # | %13 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %13 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__s0, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1, align 16 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> # | %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %9, ptr %ref.tmp, align 16 # | %10 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %10, ptr %__ret, align 16 # | %11 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %11, ptr %tmp, align 16 # | %12 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load float, ptr %__s0, align 4 # | %4 = load float, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %5, i32 1 # | %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store float %6, ptr %ref.tmp, align 4 # | %7 = load float, ptr %ref.tmp, align 4 # | store float %7, ptr %__ret, align 4 # | %8 = load float, ptr %__ret, align 4 # | store float %8, ptr %tmp, align 4 # | %9 = load float, ptr %tmp, align 4 # | ret float %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005585267e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585267e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585267e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34d8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34d8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34d8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34d8a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055852677ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055852677ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585267638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558526412e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558526412b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34d8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34d8a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34d8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558526412a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (1061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fa8e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fa8e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fa8e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5f831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fa8df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fa8df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fa8ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fa8a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fa8a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5f831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fa8a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (1062 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local half @subscript_float16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x half>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x half> %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x float>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32( %a.coerce, i64 0) # | store <16 x float> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x float>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x double>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64( %a.coerce, i64 0) # | store <8 x double> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x double>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000555574f84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555574f81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555574f8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5b6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5b62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5b6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5b6231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555574f1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555574f1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555574eff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555574baee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555574baeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5b6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5b62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5b62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555574baea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (1063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e4c6f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e4c6f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e4c6f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3728333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f372838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3728333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f372831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e4c68cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e4c68ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e4c6718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e4c320e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e4c320b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f372831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f372831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f372831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e4c320a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (1064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i64, i64, # | ... # `---data was truncated (10240/120460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dafb041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dafb03ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dafb04262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d56649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d566a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d56649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d56631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dafafd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dafafd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dafafbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dafac6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dafac6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d56632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d566330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d566330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dafac6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (1065 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa45c44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa45c41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa45c4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63f3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63f318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63f3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63f311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa45bdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa45bdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa45bbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa4586ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa4586eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63f311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63f311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63f311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa4586ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (1066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, # | ... # `---data was truncated (10240/69839) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bab0a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557bab0a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557bab0a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31b5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31b5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31b5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31b5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bab03ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557bab03ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557bab0238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557baacd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557baacd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31b5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31b5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31b5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557baacd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (1067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6d53d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6d53d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6d53d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc704a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc704aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc704a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc704a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6d5369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6d5369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6d534e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6d4ffde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6d4ffdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc704a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc704a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc704a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6d4ffda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (1068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055947b920eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055947b91de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055947b92162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02d9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02d9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02d9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02d9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055947b8b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055947b8b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055947b89b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055947b54ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055947b54ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02d9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02d9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02d9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055947b54aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (1069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (1070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (1071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ada561feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ada561ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ada562062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42c7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ada55b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ada55b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ada559a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ada5249e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ada5249b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42c72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ada5249a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/widen.c (1072 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = sext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = sext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = sext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = zext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = zext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = zext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i1 = alloca <8 x i8>, align 8 # | %__p0_561.addr.i = alloca <16 x i8>, align 16 # | %__ret_561.i = alloca <8 x i16>, align 16 # | %__a1_561.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %__s0.i = alloca <8 x i8>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0_561.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16 # | store <16 x i8> %1, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <8 x i8>, ptr %__ret.i1, align 8 # | store <8 x i8> %4, ptr %__a1_561.i, align 8 # | %5 = load <8 x i8>, ptr %__a1_561.i, align 8 # | store <8 x i8> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = sext <8 x i8> %6 to <8 x i16> # | store <8 x i16> %7, ptr %ref.tmp1.i, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16 # | store <8 x i16> %8, ptr %__ret.i, align 16 # | %9 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %9, ptr %tmp.i, align 16 # | %10 = load <8 x i16>, ptr %tmp.i, align 16 # | store <8 x i16> %10, ptr %ref.tmp.i, align 16 # | %11 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %11, ptr %__ret_561.i, align 16 # | %12 = load <8 x i16>, ptr %__ret_561.i, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i1 = alloca <4 x i16>, align 8 # | %__p0_567.addr.i = alloca <8 x i16>, align 16 # | %__ret_567.i = alloca <4 x i32>, align 16 # | %__a1_567.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0_567.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16 # | store <8 x i16> %1, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <4 x i16>, ptr %__ret.i1, align 8 # | store <4 x i16> %4, ptr %__a1_567.i, align 8 # | %5 = load <4 x i16>, ptr %__a1_567.i, align 8 # | store <4 x i16> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = sext <4 x i16> %7 to <4 x i32> # | store <4 x i32> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %9, ptr %__ret.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %10, ptr %tmp.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i, align 16 # | %12 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %12, ptr %__ret_567.i, align 16 # | %13 = load <4 x i32>, ptr %__ret_567.i, align 16 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i1 = alloca <2 x i32>, align 8 # | %__p0_564.addr.i = alloca <4 x i32>, align 16 # | %__ret_564.i = alloca <2 x i64>, align 16 # | %__a1_564.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %__s0.i = alloca <2 x i32>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0_564.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16 # | store <4 x i32> %1, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <2 x i32>, ptr %__ret.i1, align 8 # | store <2 x i32> %4, ptr %__a1_564.i, align 8 # | %5 = load <2 x i32>, ptr %__a1_564.i, align 8 # | store <2 x i32> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %8 = sext <2 x i32> %7 to <2 x i64> # | store <2 x i64> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16 # | store <2 x i64> %9, ptr %__ret.i, align 16 # | %10 = load <2 x i64>, ptr %__ret.i, align 16 # | store <2 x i64> %10, ptr %tmp.i, align 16 # | %11 = load <2 x i64>, ptr %tmp.i, align 16 # | store <2 x i64> %11, ptr %ref.tmp.i, align 16 # | %12 = load <2 # | ... # `---data was truncated (10240/16529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561a0dcedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a0dceae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a0dcee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f609681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60968725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f609681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6096803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a0dc83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a0dc83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a0dc688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a0d917e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a0d917b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6096804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60968050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60968050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a0d917a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (1073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (1075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570ea203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570ea200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570ea20462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe72b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe72b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe72b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe72b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570ea199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570ea199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570ea17e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570e9e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570e9e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe72b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe72b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe72b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570e9e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (1076 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c09d965eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c09d962e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c09d96662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd45649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd45649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd45631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c09d8fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c09d8fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c09d8e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c09d58fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c09d58fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd45632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd456330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c09d58fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (1077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , a # | ... # `---data was truncated (10240/98437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558539b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558539b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558539ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c7b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c7b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c7b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c7b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055585394fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055585394fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558539348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558535e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558535e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c7b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c7b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c7b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558535e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (1078 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ... # `---data was truncated (10240/69831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602a69fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602a69f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602a69fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f686f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f686f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f686f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f686f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602a6991bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602a6991a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602a69768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602a6625e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602a6625b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f686f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f686f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f686f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602a6625a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (1079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (1080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e50e8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e50e8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e50e8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13ec049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13ec0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13ec049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13ec031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e50e23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e50e23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e50e088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e50ab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e50ab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13ec032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13ec0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13ec0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e50ab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1081 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align # | ... # `---data was truncated (10240/22890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056242109ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562421099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056242109d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec27e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec27ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec27e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec27e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562421032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562421032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624210178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562420cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562420cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec27e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec27e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec27e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562420cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (1082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056367373ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563673739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056367373d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbabee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbabeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbabee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbabee31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636736d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636736d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636736b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563673366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563673366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbabee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbabee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbabee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563673366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (1083 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056472ead4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056472ead1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056472ead562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f139ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f139ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f139ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f139ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056472ea6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056472ea6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056472ea4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056472e6fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056472e6feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f139ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f139ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f139ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056472e6fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (1084 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055743e9c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055743e9bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055743e9c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7195133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f719518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7195133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f719511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055743e958bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055743e958a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055743e93d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055743e5ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055743e5ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f719511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f719511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f719511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055743e5eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (1085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (1086 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055db132afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db132ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db132b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e3da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e3daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e3da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e3da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db13245bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db13245a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db1322a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db12ed9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db12ed9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e3da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e3da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e3da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db12ed9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (1087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a071351eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a07134ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a07135262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f527ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f527eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f527ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f527ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0712e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0712e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0712cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a070f7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a070f7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f527ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f527ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f527ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a070f7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/63140) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583c6fa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583c6fa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583c6fa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88fcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583c6f3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583c6f3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583c6f218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583c6bd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583c6bd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583c6bd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (1089 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ae8ec0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ae8ebde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ae8ec162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d84c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d84ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d84c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d84c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ae8e56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ae8e56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ae8e3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ae8aeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ae8aeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d84c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d84c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d84c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ae8aeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (1090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llv # | ... # `---data was truncated (10240/59779) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617fdc78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617fdc75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617fdc7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff775649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff775649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff775631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617fdc0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617fdc0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617fdbf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617fd8a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617fd8a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff775632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7756330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617fd8a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (1091 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da15a60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da15a5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da15a6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1216049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1216049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1216031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da159f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da159f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da159db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da1568ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da1568ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1216032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12160330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da1568aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (1092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d39dc4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d39dc49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d39dc4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffabbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffabbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffabbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffabbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d39dbe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d39dbe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d39dbc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d39d876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d39d876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffabbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffabbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffabbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d39d876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (1093 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (1094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (1095 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svldr_zt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svstr_zt(ptr noundef %base) #2 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) } # | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055af80a51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af80a4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af80a5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a6b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a6b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a6b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a6b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af809e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af809e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af809cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af8067be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af8067bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a6b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a6b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a6b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af8067ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (1096 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582d9da0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582d9d9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582d9da162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ee8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ee858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ee8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ee851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582d9d36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582d9d36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582d9d1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582d99cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582d99cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ee851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ee851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ee851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582d99caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (1097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630b350aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630b3507e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630b350b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33f9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33f9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33f9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33f9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630b34a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630b34a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630b34858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630b3134e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630b3134b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33f9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33f9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33f9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630b3134a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (1098 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fc78abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fc78a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fc78ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc35933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc3598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc35933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc3591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fc7841bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fc7841a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fc78268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fc74d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fc74d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc3591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc3591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc3591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fc74d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (1099 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fff4f0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fff4f09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fff4f0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1853133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f185318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1853133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f185311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fff4ea2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fff4ea2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fff4e878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fff4b36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fff4b36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f185311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f185311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f185311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fff4b36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (1100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056324dd83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056324dd80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056324dd8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14b6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14b60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14b6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14b6031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056324dd19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056324dd19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056324dcfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056324d9ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056324d9adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14b6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14b60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14b60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056324d9ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (1101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592836b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592836aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592836b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f468e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f468e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f468e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f468e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559283647bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559283647a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055928362c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592832dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592832dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f468e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f468e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f468e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592832dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (1102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (1103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (1104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564167794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564167791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056416779562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c4f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c4f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c4f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c4f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056416772abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056416772aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056416770f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641673bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641673beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c4f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c4f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c4f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641673bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (1105 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1 # | ... # `---data was truncated (10240/37926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055624699aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556246997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055624699b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9a831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556246930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556246930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562469158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562465c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562465c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9a831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562465c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (1106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (1107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, # | ... # `---data was truncated (10240/142319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fefb274eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fefb271e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fefb27562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd142133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd14218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd142133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd14211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fefb20abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fefb20aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fefb1ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fefae9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fefae9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd14211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd14211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd14211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fefae9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (1108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055635b9d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055635b9d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055635b9d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4f1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4f18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4f1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4f1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055635b96ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055635b96ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055635b9538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055635b602e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055635b602b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4f1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4f18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4f18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055635b602a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (1109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (1110 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f9c4bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f9c4bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f9c4be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eac71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f9c453bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f9c453a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f9c4388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f9c0e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f9c0e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4eac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eac71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f9c0e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (1111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1e0e6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1e0e6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1e0e6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71fd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71fd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71fd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71fd803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1e0e03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1e0e03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1e0de88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1e0a97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1e0a97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71fd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71fd8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71fd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1e0a97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (1112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645b1a32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645b1a2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645b1a3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47bac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47baca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47bac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47bac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645b19c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005645b19c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645b19ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645b165ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645b165cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47bac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47bac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47bac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645b165ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (1113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (1114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acdc361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acdc35ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acdc36262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f940ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f940ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f940ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f940ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acdc2f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acdc2f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acdc2dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acdbf8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acdbf8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f940ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f940ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f940ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acdbf8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ce7a3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ce7a3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ce7a3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a4a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a4a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a4a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a4a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ce79d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ce79d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ce79b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ce7667e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ce7667b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a4a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a4a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a4a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ce7667a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (1116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff3482ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff34829e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff3482d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb42e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb42e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb42e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb42e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff347c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff347c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff347a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff34456e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff34456b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb42e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb42e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb42e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff34456a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (1117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.add # | ... # `---data was truncated (10240/153913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8a5fedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8a5feae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8a5fee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6519933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f651998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6519933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f651991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8a5f83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8a5f83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8a5f688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8a5c17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8a5c17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f651991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f651991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f651991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8a5c17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (1118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e301a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e301a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e301a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd669b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd669b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd669b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd669b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e30139bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e30139a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e3011e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e2fdcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e2fdcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd669b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd669b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd669b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e2fdcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (1119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558886144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558886141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055888614562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ad3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ad358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ad3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ad351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588860dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588860daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588860bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558885d6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558885d6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ad351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ad351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ad351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558885d6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (1120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd5f0d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd5f0cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd5f0d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f633da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f633da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f633da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f633da03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd5f068bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd5f068a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd5f04d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd5ecfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd5ecfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f633da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f633da050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f633da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd5ecfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (1121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/12656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cd70c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cd70c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cd70c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a37849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a378a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a37849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a37831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cd705ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cd705ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cd70438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cd6cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cd6cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a37832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a378330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a378330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cd6cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (1122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555766ad1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555766acee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555766ad262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdee449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdee4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdee449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdee431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555766a67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555766a67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555766a4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557666fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557666fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbdee432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdee4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdee4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557666fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (1123 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %class.anon = type { i8 } # | # | $_Z15template_functyIiET_S0_ = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_caller() #0 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | declare i32 @normal_callee() #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_callee() #0 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret i32 %call # | } # | # | declare i32 @streaming_decl() #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_caller() #3 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_callee() #3 { # | entry: # | %call = call i32 @streaming_compatible_decl() #16 # | ret i32 %call # | } # | # | declare i32 @streaming_compatible_decl() #4 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_caller() #5 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_callee() #5 { # | entry: # | %call = call i32 @locally_streaming_caller() #17 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_caller() #6 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_callee() #6 { # | entry: # | %call = call i32 @shared_za_decl() #18 # | ret i32 %call # | } # | # | declare i32 @shared_za_decl() #7 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_caller() #8 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_callee() #8 { # | entry: # | %call = call i32 @preserves_za_decl() #19 # | ret i32 %call # | } # | # | declare i32 @preserves_za_decl() #9 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_caller() #10 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_callee() #10 { # | entry: # | %call = call i32 @private_za_decl() # | ret i32 %call # | } # | # | declare i32 @private_za_decl() #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_caller() #11 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee() #12 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | declare i32 @agnostic_za_decl() #13 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee_live_za() #6 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #16 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #18 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #19 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %fptr.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %fptr, ptr %fptr.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %fptr.addr, align 8 # | %1 = load ptr, ptr %0, align 8 # | %2 = load ptr, ptr %1, align 8 # | %3 = load i32, ptr %x.addr, align 4 # | %4 = load i32, ptr %y.addr, align 4 # | call void %2(i32 noundef %3, i32 noundef %4) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @_Z24test_same_type_streamingv() #12 { # | entry: # | call void @_Z10streaming1v() #15 # | call void @_Z10streaming2v() #15 # | call void @_Z20same_type_streaming1v() #15 # | call void @_Z20same_type_streaming2v() #15 # | ret void # | } # | # | declare void @_Z10streaming1v() #2 # | # | declare void @_Z10streaming2v() #2 # | # | declare void @_Z20same_type_streaming1v() #2 # | # | declare void @_Z20same_type_streaming2v() #2 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | ret float %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | %call = call noundef float @_Z12overloadedfnf(float noundef %0) # | ret float %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | %F = alloca %class.anon, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 { # | entry: # | %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z25locally_streaming_inheritv() #5 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret void # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define dso_local noundef i32 @_Z4callv() #14 { # | entry: # | ret i32 0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 { # | entry: # | %f.addr.i16 = alloca ptr, align 8 # | %f.addr.i12 = alloca ptr, align 8 # | %other.addr.i13 = alloca ptr, align 8 # | %f.addr.i7 = alloca ptr, align 8 # | %other.addr.i8 = alloca ptr, align 8 # | %other.addr2.i9 = alloca ptr, align 8 # | %f.addr.i1 = alloca ptr, align 8 # | %other.addr.i2 = alloca ptr, align 8 # | %other.addr2.i3 = alloca ptr, align 8 # | %other.addr4.i4 = alloca ptr, align 8 # | %f.addr.i = alloca ptr, align 8 # | %other.addr.i = alloca ptr, align 8 # | %other.addr2.i = alloca ptr, align 8 # | %other.addr4.i = alloca ptr, align 8 # | %other.addr6.i = alloca ptr, align 8 # | store ptr @normal_callee, ptr %f.addr.i, align 8 # | store ptr @streaming_decl, ptr %other.addr.i, align 8 # | store ptr @streaming_compatible_decl # | ... # `---data was truncated (10240/15241) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9cb458eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9cb455e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9cb45962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e63133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e6318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e63133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e6311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9cb3eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9cb3eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9cb3d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9cb082e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9cb082b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e6311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e6311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e6311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9cb082a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x0000559724596eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559724593e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055972459762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9de133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9de18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9de133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9de11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055972452cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055972452ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597245118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597241c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597241c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9de11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9de11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9de11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597241c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (1124 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_z( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_m( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_x( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055670989beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556709898e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055670989c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b4f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b4f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b4f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b4f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556709831bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556709831a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567098168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567094c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567094c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b4f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b4f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b4f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567094c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (1125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056197a0daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056197a0d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056197a0db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb842b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb842b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb842b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb842b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056197a070bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056197a070a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056197a0558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561979d04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561979d04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb842b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb842b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb842b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561979d04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (1126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg # | ... # `---data was truncated (10240/20531) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b2b7f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b2b7f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b2b7f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86e6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86e658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86e6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86e651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b2b789bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b2b789a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b2b76e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b2b41de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b2b41db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86e651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86e651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86e651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b2b41da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (1127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582fd92aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582fd927e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582fd92b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed36305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed3635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed36305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed362ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582fd8c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582fd8c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582fd8a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582fd554e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582fd554b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed362eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed362ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed362ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582fd554a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (1128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0fe0f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0fe0eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0fe0f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a21e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a21ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a21e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a21e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0fe087bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0fe087a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0fe06c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0fdd1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0fdd1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a21e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a21e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a21e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0fdd1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (1129 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/79071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fed4e49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fed4e46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fed4e4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd071733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd07178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd071733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd07171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fed4ddfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fed4ddfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fed4dc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fed4a73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fed4a73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd07171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd07171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd07171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fed4a73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (1130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset # | ... # `---data was truncated (10240/287213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b20c7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b20c7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b20c7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35ce249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35ce2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35ce249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35ce231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b20c14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b20c14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b20bf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b208a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b208a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35ce232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35ce2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35ce2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b208a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1131 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %and.i = and <8 x i16> %2, %3 # | store <8 x i16> %and.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %and.i = and <2 x i32> %2, %3 # | store <2 x i32> %and.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %and.i = and <4 x i32> %2, %3 # | store <4 x i32> %and.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %and.i = and <1 x i64> %2, %3 # | store <1 x i64> %and.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %and.i = and <2 x i64> %2, %3 # | store <2 x i64> %and.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, al # | ... # `---data was truncated (10240/70553) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fbfc27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fbfc24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fbfc2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa742449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa742449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa742431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fbfbbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fbfbbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fbfba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fbf851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fbf851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa742432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7424330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fbf851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (1132 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80) # | %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64) # | %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %addr, ptr %addr.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4) # | %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1 # | store <2 x i64> %6, ptr %0, align 8 # | %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef5f5ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef5f5e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef5f5ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7926f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7926f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7926f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7926f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef5f581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef5f581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef5f5668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef5f215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef5f215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7926f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7926f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7926f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef5f215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (1133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056057f953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056057f950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056057f95462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8840a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8840aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8840a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8840a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056057f8e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056057f8e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056057f8ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056057f57de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056057f57db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8840a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8840a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8840a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056057f57da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (1134 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv4f32( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv2f64( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv2f64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamin_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famin.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famin.x2.nxv8f16(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (1135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (1136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (1137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055620b99eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055620b99be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055620b99f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46e2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46e2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46e2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46e2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055620b934bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055620b934a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055620b9198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055620b5c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055620b5c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46e2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46e2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46e2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055620b5c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (1138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26badaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c26bad7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c26badb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eb7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eb758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eb7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eb751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c26ba70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c26ba70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c26ba558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c26b704e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c26b704b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5eb751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eb751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eb751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26b704a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (1139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ca8c7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ca8c7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ca8c8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8945d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8945d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8945d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8945d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ca8c15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ca8c15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ca8bfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ca88a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ca88a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8945d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8945d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8945d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ca88a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (1140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cf5bcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cf5bcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cf5bce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa919933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa91998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa919933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa91991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cf5b63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560cf5b63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560cf5b488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560cf57f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560cf57f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa91991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa91991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa91991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cf57f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (1141 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmov_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.and.z.nxv16i1( %0, %1, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556b6f59aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b6f597e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b6f59b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc95449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc954a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc95449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc95431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b6f530bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b6f530a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b6f5158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b6f1c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b6f1c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc95432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc954330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc954330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b6f1c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (1142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/69542) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9577a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9577a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9577a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3744649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37446a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3744649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3744631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b957739bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b957739a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b95771e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9573cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9573cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3744632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37446330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37446330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9573cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (1143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (1144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (1145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562d22f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562d22f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562d22f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff663c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff663c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff663c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff663c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562d2289bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562d2289a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562d226e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562d1f1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562d1f1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff663c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff663c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff663c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562d1f1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (1146 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i3 # | ... # `---data was truncated (10240/57708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561786e8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561786e8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561786e8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb407049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4070a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb407049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb407031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561786e23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561786e23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561786e088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561786ab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561786ab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb407032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4070330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4070330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561786ab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (1147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cb3a81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cb3a7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cb3a8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee69133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee6918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee69133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee6911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cb3a17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cb3a17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cb39fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cb36abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cb36abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee6911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee6911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee6911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cb36aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (1148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | % # | ... # `---data was truncated (10240/21774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5a80c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5a80c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5a80c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6116f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6116f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6116f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6116f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5a805ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5a805ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5a80438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5a7cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5a7cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6116f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6116f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6116f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5a7cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (1149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb0496beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb04968e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb0496c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95af631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb04901bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb04901a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb048e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb04595e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb04595b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95af6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb04595a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a726646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a726643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a72664762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe8f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe8f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe8f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe8f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7265dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7265dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7265c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a726270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a726270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe8f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe8f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe8f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a726270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void # | ... # `---data was truncated (10240/179328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561959d7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561959d7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561959d8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e21649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e216a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e21649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e21631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561959d15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561959d15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561959cfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619599a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619599a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e21632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e216330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e216330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619599a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (1152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559f3a48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559f3a45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559f3a4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d2eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d2eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d2eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d2eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559f39debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559f39dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559f39c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559f3672e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559f3672b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d2eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d2eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d2eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559f3672a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (1153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564a1f09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564a1f06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564a1f0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feda9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feda9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feda9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feda9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564a1e9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564a1e9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564a1e848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564a1b33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564a1b33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feda9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feda9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feda9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564a1b33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (1154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f69bcc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f69bcc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f69bcca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7532a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7532aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7532a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7532a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f69bc5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f69bc5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f69bc448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f69b8f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f69b8f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7532a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7532a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7532a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f69b8f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (1155 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | # | ... # `---data was truncated (10240/29535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f13306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f13303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f1330762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd48461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4846725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd48461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd484603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f1329cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f1329ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f132818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f12f30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f12f30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd484604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4846050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4846050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f12f30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (1156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6870cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6870cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6870ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f213ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f213ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f213ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f213ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f687063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f687063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6870488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f686cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f686cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f213ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f213ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f213ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f686cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (1157 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i) # | %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8> # | store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i) # | %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8> # | store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i) # | %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8> # | store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i) # | %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8> # | store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i) # | %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8> # | store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i) # | %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8> # | store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i) # | %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8> # | store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i) # | %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8> # | store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i) # | %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8> # | store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i) # | %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8> # | store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i) # | %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8> # | store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x # | ... # `---data was truncated (10240/16447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055abddbceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abddbcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abddbcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93e1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93e1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93e1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93e1ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abddb64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abddb64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abddb498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abdd7f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abdd7f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93e1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93e1cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93e1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abdd7f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (1158 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp eq %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ne %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | stor # | ... # `---data was truncated (10240/44453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055d758d80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d758d7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d758d8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62db31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d758d16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d758d16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d758cfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7589aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7589aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62db31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7589aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (1159 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (1160 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bece944eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bece941e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bece94562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd23a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd23a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd23a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd23a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bece8dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bece8daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bece8bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bece56ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bece56eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd23a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd23a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd23a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bece56ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (1161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/76627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c28396beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c283968e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c28396c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2bff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2bff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2bff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2bff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c283901bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c283901a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2838e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c283595e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c283595b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2bff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2bff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2bff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c283595a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (1162 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/46416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c543e1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c543e17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c543e1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e86a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e86aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e86a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e86a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c543db0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c543db0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c543d958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c543a44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c543a44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e86a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e86a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e86a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c543a44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (1163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056025a496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056025a493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056025a49762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10d361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10d36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10d361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10d3603507 abort ./stdlib/abort.c:85:3 # | #7 0x000056025a42cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056025a42ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056025a4118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056025a0c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056025a0c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10d3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10d36050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10d36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056025a0c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (1164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.abs.i32(i32 %0, i1 true) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.abs.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp sle i32 %0, %1 # | %sle = zext i1 %2 to i32 # | ret i32 %sle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp ule i32 %0, %1 # | %sleu = zext i1 %2 to i32 # | ret i32 %sleu # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = sext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exths = sext i16 %1 to i32 # | ret i32 %exths # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = zext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exthz = zext i16 %1 to i32 # | ret i32 %exthz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = sext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbs = sext i8 %1 to i32 # | ret i32 %extbs # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = zext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbz = zext i8 %1 to i32 # | ret i32 %extbz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xcvalu1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9dd212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9dd20fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9dd21362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bca631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9dd1a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9dd1a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9dd18d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9dce3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9dce3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bca6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9dce3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (1165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(< # | ... # `---data was truncated (10240/119297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ff82f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ff82f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ff82f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f58449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f58449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f58431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ff828ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ff828ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ff82738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ff7f22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ff7f22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f58432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f584330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ff7f22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (1166 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %value.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576) # | %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1 # | store <2 x i64> %3, ptr %0, align 8 # | %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = load <4 x i32>, ptr %value.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2) # | store <4 x i32> %3, ptr %0, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4 # | # | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cabb29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cabb26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cabb2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba33a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba33aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba33a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba33a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cababfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cababfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cabaa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cab753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cab753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba33a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba33a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba33a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cab753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (1167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, ali # | ... # `---data was truncated (10240/201234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e80c9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e80c97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e80c9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87e1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87e1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87e1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87e1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e80c30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e80c30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e80c158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e808c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e808c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87e1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87e1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87e1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e808c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (1168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605de8e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605de8e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605de8e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae21e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae21ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae21e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae21e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605de87bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605de87ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605de8608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605de50fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605de50fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae21e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae21e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae21e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605de50fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (1169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | # | ... # `---data was truncated (10240/211223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd76797eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd76794e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd7679862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4121e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4121ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4121e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4121e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd7672dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd7672da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd767128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd763c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd763c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4121e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4121e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4121e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd763c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (1170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (1171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1837b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1837b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1837b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60e611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e18374ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e18374ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1837338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1833e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1833e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60e611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1833e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (1172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597dc2b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597dc2b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597dc2b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24f5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24f5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24f5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24f5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597dc24abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597dc24aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597dc22f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597dbedee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597dbedeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f24f5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24f5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24f5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597dbedea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (1173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055945ef77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055945ef74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055945ef7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe5fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe5fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe5fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe5fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055945ef0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055945ef0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055945eef28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055945eba1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055945eba1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe5fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe5fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe5fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055945eba1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2462a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b24629fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2462a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3415533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f341558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3415533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f341551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b246238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b246238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b24621d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b245ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b245eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f341551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f341551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f341551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b245ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634e97feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634e97fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634e97ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4b2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4b2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4b2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4b2e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634e9794bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634e9794a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634e97798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634e9428e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634e9428b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4b2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4b2e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4b2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634e9428a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (1176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4bbdb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4bbdb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4bbdb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5127933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f512798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5127933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f512791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4bbd4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4bbd4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4bbd308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4bb9dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4bb9dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f512791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f512791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f512791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4bb9dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (1177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c85942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c8593fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c8594362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb633c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb633ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb633c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb633c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c858d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c858d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c858bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c8556ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c8556cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb633c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb633c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb633c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c8556ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (1178 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f8e3e4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8e3e47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8e3e4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff406333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff40638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff406333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff40631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8e3de0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8e3de0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8e3dc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8e3a74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8e3a74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff40631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff40631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff40631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8e3a74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (1179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648ef767eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648ef764e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648ef76862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff469b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff469b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff469b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff469b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648ef6fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648ef6fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648ef6e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648ef391e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648ef391b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff469b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff469b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff469b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648ef391a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608ffabbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608ffab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608ffabc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17f1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17f1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17f1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17f1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608ffa51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608ffa51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608ffa368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608ff6e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608ff6e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17f1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17f1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17f1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608ff6e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (1181 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("ris # | ... # `---data was truncated (10240/26965) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8874e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8874e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8874e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb02c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb02c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb02c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb02c4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f88747ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f88747ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8874638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f887112e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f887112b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb02c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb02c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb02c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f887112a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632d96a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632d96a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632d96a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e8e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e8e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e8e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e8e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632d963dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632d963da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632d96228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632d92d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632d92d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e8e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e8e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e8e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632d92d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (1183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m4_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv32i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv32i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m4_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, p # | ... # `---data was truncated (10240/54546) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574e708feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574e708ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574e709062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78a3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78a3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78a3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78a3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574e7025bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574e7025a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574e700a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574e6cb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574e6cb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78a3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78a3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78a3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574e6cb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (1184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f88a3f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f88a3eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f88a3f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8cb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f88a387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f88a387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f88a36c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f88a01be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f88a01bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f88a01ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (1185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b8d505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b8d502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b8d50662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd99f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd99f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd99f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd99f403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b8d49bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b8d49ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b8d4808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b8d12fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b8d12fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd99f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd99f4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd99f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b8d12fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (1186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc050fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc050f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc050fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc0aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc0aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc0aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc0aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc05092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc05092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc050778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc04d26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc04d26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc0aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc0aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc0aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc04d26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (1187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056552078deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056552078ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056552078e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1613a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1613aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1613a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1613a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565520723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565520723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005655207088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005655203b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005655203b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1613a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1613a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1613a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655203b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (1188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (1189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639bd584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639bd581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639bd58562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5308333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f530838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5308333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f530831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639bd51abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639bd51aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639bd4ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639bd1aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639bd1aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f530831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f530831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f530831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639bd1aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (1190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/92362) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b0ceaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b0cea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b0cead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2f7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b0ce42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b0ce42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b0ce278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b0cad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b0cad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2f7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b0cad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (1191 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (1192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/18669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5a5d31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5a5d2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5a5d3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53a0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5a5cc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5a5cc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5a5cac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5a595be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5a595bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53a08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5a595ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (1193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b42c60eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b42c60be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b42c60f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef0d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef0d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef0d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef0d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b42c5a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b42c5a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b42c5898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b42c238e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b42c238b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef0d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef0d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef0d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b42c238a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (1194 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587bd35deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587bd35ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587bd35e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf30f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf30f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf30f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf30f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587bd2f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587bd2f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587bd2d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587bcf87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587bcf87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf30f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf30f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf30f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587bcf87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: Modules/pr93497.cppm (1195 of 27910) ******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 3 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.Thing = type { i32 } # | %struct.C = type { i32 } # | %struct.NonConstexprDtor = type { i32 } # | # | $needed = comdat any # | # | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4 # | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4 # | @_ZW3mod11ConstantPtr = external global ptr, align 8 # | @_ZW3mod16NonConstantValue = external global %struct.C, align 4 # | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4 # | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }] # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z3usev() #0 { # | entry: # | %t1 = alloca %struct.Thing, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | declare noundef i32 @_Z7consumei(i32 noundef) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use2v() #0 { # | entry: # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %0 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0) # | ret i32 %call # | } # | # | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use3v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ptr = alloca ptr, align 8 # | %agg.tmp = alloca %struct.C, align 4 # | %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8 # | store ptr %0, ptr %Ptr, align 8 # | %1 = load ptr, ptr %Ptr, align 8 # | %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0 # | %2 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %2, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %3 = load ptr, ptr %Ptr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %4 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr i32 @needed() #0 comdat { # | entry: # | %call = call noundef i32 @_Z7consumei(i32 noundef 43) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use4v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ref = alloca %struct.C, align 4 # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false) # | %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0 # | %0 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %1 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use5v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %V = alloca %struct.NonConstexprDtor, align 4 # | %cleanup.dest.slot = alloca i32, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %1 = load i32, ptr %raw1, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %1) # | store i32 %call, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | if.end: ; preds = %entry # | %call2 = call i32 @needed() # | store i32 %call2, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | cleanup: ; preds = %if.end, %if.then # | call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5 # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind # | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3 # | # | declare void @_ZGIW3mod() # | # | ; Function Attrs: noinline nounwind # | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" { # | entry: # | call void @_ZGIW3mod() # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #5 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # | #0 0x000055ca1377aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca13777e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca1377b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fceafb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fceafb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fceafb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fceafaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca13710bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca13710a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca136f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca133a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca133a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fceafaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fceafaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fceafaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca133a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (1196 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x float>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %b.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store <8 x float> %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load <8 x float>, ptr %b.addr, align 8 # | %add = fadd <8 x float> %0, %1 # | store <8 x float> %add, ptr %retval, align 8 # | %2 = load <8 x float>, ptr %retval, # | ... # `---data was truncated (10240/145303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b97f63ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b97f639e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b97f63d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6754333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f675438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6754333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f675431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b97f5d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b97f5d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b97f5b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b97f266e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b97f266b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f675431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f675431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f675431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b97f266a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (1197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl. # | ... # `---data was truncated (10240/24951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653209a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653209a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653209aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4d0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4d06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4d0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4d0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056532093fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056532093fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653209248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653205d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653205d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4d0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4d06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4d06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653205d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (1198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648806d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648806cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648806d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3aea849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3aea8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3aea849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3aea831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564880666bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564880666a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056488064b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648802fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648802fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3aea832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3aea8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3aea8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648802faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (1199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2be70beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2be708e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2be70c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d7a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d7a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d7a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d7a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2be6a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2be6a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2be6868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2be335e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2be335b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d7a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d7a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d7a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2be335a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/getset.c (1200 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <1 x i8>, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <1 x i8>, align 1 # | %tmp = alloca <1 x i8>, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load <1 x i8>, ptr %ref.tmp, align 1 # | store <1 x i8> %2, ptr %__ret, align 1 # | %3 = load <1 x i8>, ptr %__ret, align 1 # | store <1 x i8> %3, ptr %tmp, align 1 # | %4 = load <1 x i8>, ptr %tmp, align 1 # | ret <1 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_847 = alloca half, align 2 # | %__s0_847 = alloca <4 x half>, align 8 # | %ref.tmp = alloca i16, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp1 = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %tmp2 = alloca half, align 2 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_847, align 8 # | %1 = load <4 x i16>, ptr %__s0_847, align 8 # | store <4 x i16> %1, ptr %__s0, align 8 # | %2 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %2, i32 1 # | store i16 %vget_lane, ptr %ref.tmp1, align 2 # | %3 = load i16, ptr %ref.tmp1, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | store i16 %5, ptr %ref.tmp, align 2 # | %6 = load half, ptr %ref.tmp, align 2 # | store half %6, ptr %__ret_847, align 2 # | %7 = load half, ptr %__ret_847, align 2 # | store half %7, ptr %tmp2, align 2 # | %8 = load half, ptr %tmp2, align 2 # | %conv = fpext half %8 to float # | ret float %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %1, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %1, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align # | ... # `---data was truncated (10240/76998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c0c03aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0c03a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0c03ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f222b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f222b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f222b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f222b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0c0340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0c0340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0c03258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0bffd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0bffd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f222b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f222b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f222b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0bffd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1201 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %p0.addr = alloca <4 x float>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <4 x float> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <4 x float>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c916ec0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c916ebde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c916ec162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca41133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca4118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca41133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca4111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c916e56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c916e56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c916e3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c916aeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c916aeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca4111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca4111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca4111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c916aeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (1202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , < # | ... # `---data was truncated (10240/117389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf16e25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf16e22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf16e2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bd1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bd178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bd1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bd171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf16dbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf16dbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf16da08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf16a4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf16a4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bd171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bd171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bd171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf16a4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d9ac9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d9ac9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d9aca062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7c1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7c1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7c1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7c1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d9ac35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d9ac35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d9ac1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d9a8c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d9a8c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7c1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7c1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7c1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d9a8c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (1204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560923a6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560923a6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560923a7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f15c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f15ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f15c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f15c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560923a05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560923a05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609239ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560923699e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560923699b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f15c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f15c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f15c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560923699a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (1205 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # | #0 0x000055e28621eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e28621be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e28621f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe080449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe080449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe080431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2861b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2861b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2861998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e285e48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e285e48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe080432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0804330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e285e48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (1206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (1207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef # | ... # `---data was truncated (10240/14333) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599d0c16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599d0c13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599d0c1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96c7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96c70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96c7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96c7031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599d0bacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599d0baca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599d0b918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599d0840e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599d0840b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96c7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96c70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96c70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599d0840a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (1208 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eaa24ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eaa249e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eaa24d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f765b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f765b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f765b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f765b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eaa1e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eaa1e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eaa1c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ea9e76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ea9e76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f765b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f765b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f765b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ea9e76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (1209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610aa895eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610aa892e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610aa89662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9a0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9a098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9a0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9a091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610aa82bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610aa82ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610aa8108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610aa4bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610aa4bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9a091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9a091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9a091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610aa4bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (1210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, # | ... # `---data was truncated (10240/12298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c225aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c225abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c225af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9f831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c22544bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c22544a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c225298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c221d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c221d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9f831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c221d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (1211 of 27910) ******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # | #0 0x000055e277905eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e277902e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e27790662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5792c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5792ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5792c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5792c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e27789bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e27789ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2778808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e27752fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e27752fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5792c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5792c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5792c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e27752fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (1212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567e6cbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005567e6cbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567e6cbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0558d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0558d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0558d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0558ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567e6c54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567e6c54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567e6c398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567e68e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567e68e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0558ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0558cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0558cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567e68e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (1213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (1214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055905ec1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055905ec18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055905ec1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f753e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f753e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f753e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f753e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055905ebb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055905ebb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055905eb968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055905e845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055905e845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f753e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f753e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f753e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055905e845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (1215 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557cd44f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cd44f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cd44f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f0bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f0bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f0bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f0bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cd448abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cd448aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cd446f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cd411ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cd411eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f0bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f0bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f0bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cd411ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (1216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055685e46feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055685e46ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055685e47062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d3e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d3e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d3e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d3e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055685e405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055685e405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055685e3ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055685e099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055685e099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d3e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d3e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d3e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055685e099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1217 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = # | ... # `---data was truncated (10240/154509) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dffb5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559dffb57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559dffb5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12a2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12a258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12a2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12a251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dffaf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559dffaf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559dffad58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559dff784e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559dff784b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f12a251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12a251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12a251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dff784a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (1218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eda0cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eda0cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eda0cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5be3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5be34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5be3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5be3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eda0c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eda0c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eda0c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eda0926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eda0926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5be3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5be34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5be34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eda0926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (1219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (1220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f41623ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f416239e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f41623d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f681d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f681d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f681d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f681d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4161d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4161d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4161b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f415e66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f415e66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f681d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f681d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f681d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f415e66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (1221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559e58ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559e58e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559e58ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcee7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcee778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcee7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcee771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559e5881bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559e5881a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559e58668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559e5515e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559e5515b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcee771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcee771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcee771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559e5515a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (1222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fbf6efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fbf6ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fbf6f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa524e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa524ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa524e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa524e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fbf685bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fbf685a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fbf66a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fbf319e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fbf319b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa524e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa524e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa524e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fbf319a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (1223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (1224 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (1225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556844613eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556844610e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055684461462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3885249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38852a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3885249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3885231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568445a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568445a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055684458e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055684423de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055684423db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3885232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38852330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38852330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055684423da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (1226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/210435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614c30c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614c30bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614c30c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f287e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f287e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f287e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f287e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614c3058bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614c3058a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614c303d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614c2cece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614c2cecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f287e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f287e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f287e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614c2ceca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (1227 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou # | ... # `---data was truncated (10240/28396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x00005643e47b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643e47ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643e47b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96f9231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643e4746bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643e4746a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643e472b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643e43dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643e43dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96f92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643e43daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056455f07feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056455f07ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056455f08062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d1641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d164725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d1641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d16403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056455f015bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056455f015a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056455effa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056455eca9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056455eca9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d16404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d164050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d164050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056455eca9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (1229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654a317beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654a3178e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654a317c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f573a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f573a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f573a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f573a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654a3111bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654a3111a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654a30f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654a2da5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654a2da5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f573a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f573a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f573a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654a2da5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (1230 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_790 = alloca <4 x i16>, align 8 # | %__s0_790 = alloca <4 x i16>, align 8 # | %__s1_790 = alloca <4 x i16>, align 8 # | %__s2_790 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_790, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_790, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_790, align 16 # | %3 = load <4 x i16>, ptr %__s0_790, align 8 # | %4 = load <4 x i16>, ptr %__s1_790, align 8 # | %5 = load <8 x i16>, ptr %__s2_790, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_790, align 8 # | %16 = load <4 x i16>, ptr %__ret_790, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_788 = alloca <2 x i32>, align 8 # | %__s0_788 = alloca <2 x i32>, align 8 # | %__s1_788 = alloca <2 x i32>, align 8 # | %__s2_788 = alloca <4 x i32>, align 16 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_788, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_788, align 8 # | %2 = load <4 x i32>, ptr %v.addr, align 16 # | store <4 x i32> %2, ptr %__s2_788, align 16 # | %3 = load <2 x i32>, ptr %__s0_788, align 8 # | %4 = load <2 x i32>, ptr %__s1_788, align 8 # | %5 = load <4 x i32>, ptr %__s2_788, align 16 # | store <4 x i32> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x i32> # | %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <2 x i32> %4, ptr %__p1.addr.i, align 8 # | store <2 x i32> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %14 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %14, ptr %__ret.i, align 8 # | %15 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %15, ptr %__ret_788, align 8 # | %16 = load <2 x i32>, ptr %__ret_788, align 8 # | store <2 x i32> %16, ptr %tmp1, align 8 # | %17 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_786 = alloca <8 x i16>, align 16 # | %__s0_786 = alloca <8 x i16>, align 16 # | %__s1_786 = alloca <8 x i16>, align 16 # | %__s2_786 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_786, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_786, align 16 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_786, align 16 # | %3 = load <8 x i16>, ptr %__s0_786, align 16 # | %4 = load <8 x i16>, ptr %__s1_786, align 16 # | %5 = load <8 x i16>, ptr %__s2_786, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | store <8 x i16> %3, ptr %__p0.addr.i, align 16 # | store <8 x i16> %4, ptr %__p1.addr.i, align 16 # | store <8 x i16> %10, ptr %__p2.addr.i, align 16 # | %11 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %14 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %14, ptr %__ret.i, align 16 # | %15 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %15, ptr %__ret_786, align 16 # | %16 = load <8 x i16>, ptr %__ret_786, align 16 # | store <8 x i16> %16, ptr %tmp1, align 16 # | %17 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_784 = alloca <4 x i32>, align 16 # | %__s0_784 = alloca <4 x i32>, align 16 # | %__s1_784 = alloca <4 x i32>, align 16 # | %__s2_784 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <4 # | ... # `---data was truncated (10240/50621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x0000555692802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556927ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055569280362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f577d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f577d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f577d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f577d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555692798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555692798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055569277d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055569242ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055569242cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f577d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f577d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f577d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055569242ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (1231 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559971fa7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559971fa4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559971fa862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb279049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2790a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb279049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb279031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559971f3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559971f3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559971f228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559971bd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559971bd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb279032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2790330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2790330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559971bd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (1232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600aac8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600aac89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600aac8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ff0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ff0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ff0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ff0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600aac22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600aac22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600aac078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600aa8b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600aa8b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ff0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ff0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ff0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600aa8b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (1233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8f1226eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8f1223e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8f122762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a9ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a9ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a9ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a9ba03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8f11bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8f11bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8f11a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8f0e50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8f0e50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a9ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a9ba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a9ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f0e50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (1234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a1e1c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a1e1c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a1e1c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91fb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91fb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91fb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91fb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a1e15ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a1e15ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a1e1438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a1ddf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a1ddf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91fb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91fb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91fb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a1ddf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (1235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ac0966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ac0963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ac096762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1416b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1416b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1416b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1416b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ac08fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ac08fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ac08e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ac0590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ac0590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1416b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1416b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1416b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ac0590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/205805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e71b694eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e71b691e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e71b69562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7217249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7217249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7217231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e71b62abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e71b62aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e71b60f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e71b2bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e71b2beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7217232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72172330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e71b2bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (1237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f15c48eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f15c48be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f15c48f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbadc61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbadc6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbadc61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbadc603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f15c424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f15c424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f15c4098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f15c0b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f15c0b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbadc604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbadc6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbadc6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f15c0b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (1238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595f5b3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595f5b3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595f5b4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d5db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d5db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d5db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d5db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595f5ad5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595f5ad5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595f5aba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595f5769e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595f5769b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d5db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d5db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d5db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595f5769a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (1239 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_ran # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7c471feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7c471ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7c472062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7c46b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7c46b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7c469a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7c4349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7c4349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6f371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7c4349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (1240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,102 # | ... # `---data was truncated (10240/10769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfc073eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfc073be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfc073f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5563905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f556395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5563905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55638ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfc06d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfc06d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfc06b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfc0368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfc0368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55638eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55638ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55638ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfc0368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1241 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fcmp oeq <4 x float> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = fcmp oeq <4 x float> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = icmp eq <4 x i32> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = # | ... # `---data was truncated (10240/125481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585f793feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585f793ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585f794062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc759249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7592a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc759249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc759231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585f78d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585f78d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585f78ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585f7569e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585f7569b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc759232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7592330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7592330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585f7569a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (1242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1f9214eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1f9211e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1f921562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c32b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c32b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c32b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c32b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1f91aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1f91aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1f918f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1f8e3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1f8e3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c32b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c32b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c32b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1f8e3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (1243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (1244 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557143e22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557143e1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557143e2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcc2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcc238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcc2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcc231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557143db8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557143db8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557143d9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557143a4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557143a4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdcc231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcc231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcc231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557143a4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (1245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (1246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636bbce6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636bbce3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636bbce762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ebba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ebbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ebba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ebba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636bbc7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636bbc7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636bbc618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636bb910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636bb910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ebba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ebba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ebba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636bb910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (1247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d45e42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d45e3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d45e4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f637ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f637ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f637ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f637ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d45dd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d45dd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d45dbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d45a6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d45a6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f637ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f637ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f637ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d45a6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (1248 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloc # | ... # `---data was truncated (10240/122004) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556350971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055635096ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055635097262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2076133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f207618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2076133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f207611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556350907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556350907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563508ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055635059be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055635059bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f207611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f207611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f207611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055635059ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (1249 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_any( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_first( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_last( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558c8f0c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c8f0c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c8f0ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ce6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ce618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ce6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ce611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c8f05fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c8f05fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c8f0448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c8ecf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c8ecf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ce611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ce611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ce611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c8ecf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (1250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055843bfe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055843bfe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055843bfea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd69649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd69649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd69631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055843bf7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055843bf7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055843bf648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055843bc13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055843bc13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd69632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd696330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055843bc13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (1251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (1252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/79861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb383f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb383f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb383f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc52fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc52fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc52fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc52fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb3838cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb3838ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb383718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb38020e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb38020b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc52fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc52fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc52fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb38020a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (1253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df469cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df469c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df469cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4d4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4d478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4d4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4d471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df46962bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df46962a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df469478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df465f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df465f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4d471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4d471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4d471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df465f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (1254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b06d5caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b06d5c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b06d5cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5da0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5da06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5da0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5da0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b06d560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b06d560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b06d5458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b06d1f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b06d1f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5da0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5da06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5da06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b06d1f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (1255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055896b28eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055896b28be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055896b28f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadedf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadedf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadedf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadedeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055896b224bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055896b224a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055896b2098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055896aeb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055896aeb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadedeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadedeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadedeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055896aeb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (1256 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (1257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a17198eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a17195e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a1719962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29a3505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29a355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29a3505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29a34ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a1712ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a1712ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a171138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a16dc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a16dc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29a34eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29a34ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29a34ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a16dc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (1258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633a7787eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633a7784e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633a778862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd138333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd13838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd138333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd13831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633a771dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633a771da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633a77028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633a73b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633a73b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd13831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd13831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd13831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633a73b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (1259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b53474eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b53471e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b5347562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55d4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55d4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55d4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55d4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b5340abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b5340aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b533ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b5309ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b5309eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55d4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55d4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55d4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b5309ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (1260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2a03efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2a03ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2a03f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c7f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c7f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c7f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c7f031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2a0385bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2a0385a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2a036a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2a0019e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2a0019b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c7f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c7f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c7f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2a0019a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (1261 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ef6fbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ef6fbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ef6fc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad7ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad7aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad7ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad7ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ef6f55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ef6f55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ef6f3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ef6be9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ef6be9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad7ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad7ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad7ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ef6be9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (1262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc361c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc361bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc361c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc54fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc54fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54fa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc36157bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc36157a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc3613c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc35debe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc35debb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc54fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54fa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc35deba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (1263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555abe608eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555abe605e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555abe60962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca4ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca4ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca4ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca4ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555abe59ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555abe59ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555abe5838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555abe232e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555abe232b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca4ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca4ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca4ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555abe232a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (1264 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d76c4cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d76c4cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d76c4d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10a8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10a818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10a8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10a811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d76c465bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d76c465a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d76c44a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d76c0f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d76c0f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10a811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10a811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10a811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d76c0f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (1265 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnda.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i) # | store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndp.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i) # | store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) # | store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %3, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x half> # | store <4 x half> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__ret.i3 = alloca <8 x half>, align 16 # | %__p0.addr.i.i = alloca <4 x float>, align 16 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 16 # | %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %5 = bitcast <16 x i8> %4 to <4 x float> # | %6 = fptrunc <4 x float> %5 to <4 x half> # | store <4 x half> %6, ptr %ref.tmp.i.i, align 8 # | %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %7, ptr %__ret.i.i, align 8 # | %8 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %2, ptr %__p0.addr.i1, align 8 # | store <4 x half> %8, ptr %__p1.addr.i2, align 8 # | %9 = load <4 x half>, ptr %__p0.addr.i1, align 8 # | %10 = load <4 x half>, ptr %__p1.addr.i2, align 8 # | %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i3, align 16 # | %11 = load <8 x half>, ptr %__ret.i3, align 16 # | store <8 x half> %11, ptr %__ret.i, align 16 # | %12 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fpext <4 x half> %2 to <4 x float> # | store <4 x float> %3, ptr %ref.tmp.i, align 16 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %4, ptr %__ret.i, align 16 # | %5 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__ret.i2 = alloca <4 x half>, align 8 # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x half>, ptr %__ret.i2, align 8 # | store <4 x half> %4, ptr %__p0.addr.i.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %7 = fpext <4 x half> %6 to <4 x float> # | store <4 x float> %7, ptr %ref.tmp.i.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %8, ptr %__ret.i.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i.i, align 16 # | store <4 x float> %9, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e27cb35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e27cb32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e27cb3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4806c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4806ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4806c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4806c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e27cacbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e27cacba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e27cab08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e27c75fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e27c75fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4806c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4806c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4806c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e27c75fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (1266 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef827b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef827b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef827b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f3a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f3a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f3a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f3a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef8274abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef8274aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef8272f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef823dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef823deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f3a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f3a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f3a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef823dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (1267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function A # | ... # `---data was truncated (10240/68067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e71fdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e71fdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e71fe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd04d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd04d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd04d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd04d831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e71f75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e71f75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e71f5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e71c09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e71c09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd04d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd04d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd04d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e71c09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (1268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f791741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f79173ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f79174262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffae0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffae02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffae0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffae0231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7916d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7916d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7916bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f79136be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f79136bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffae0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffae02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffae02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f79136ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (1269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf8bfdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf8bfd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf8bfdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd51f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd51f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd51f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd51f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf8bf70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf8bf70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf8bf558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf8bc04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf8bc04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd51f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd51f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd51f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf8bc04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (1270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558368968eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558368965e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055836896962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb7c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb7c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb7c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb7c031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583688febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583688fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583688e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558368592e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558368592b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb7c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb7c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb7c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558368592a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (1271 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563888dfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563888dfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563888dfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cbb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cbb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cbb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cbb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563888d93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563888d93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563888d788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563888a27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563888a27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cbb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cbb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cbb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563888a27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (1272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055783f935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055783f932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055783f93662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b57249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b572a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b57249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b57231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055783f8cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055783f8cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055783f8b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055783f55fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055783f55fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b57232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b572330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b572330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055783f55fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (1273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (1274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a6ba68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a6ba65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a6ba6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd778849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd778849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd778831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a6b9febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a6b9fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a6b9e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a6b692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a6b692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd778832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7788330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a6b692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (1275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, # | ... # `---data was truncated (10240/288103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f31024eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f31021e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f3102562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba18f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba18f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba18f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba18f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f30fbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f30fbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f30f9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f30c4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f30c4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba18f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba18f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba18f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f30c4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (1276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1bcd8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1bcd89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1bcd8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f994bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f994bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f994bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f994bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1bcd22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1bcd22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1bcd078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1bc9b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1bc9b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f994bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f994bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f994bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1bc9b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (1277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1b3137eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1b3134e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1b313862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7008305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f700835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7008305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70082ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1b30cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1b30cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1b30b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1b2d61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1b2d61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70082eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70082ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70082ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1b2d61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (1278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/79671) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056074be99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056074be96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056074be9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9c4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9c438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9c4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9c431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056074be2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056074be2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056074be148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056074bac3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056074bac3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9c431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9c431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9c431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056074bac3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (1279 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab43f00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab43efde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab43f0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9f4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9f478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9f4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9f471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab43e96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab43e96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab43e7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab43b2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab43b2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9f471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9f471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9f471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab43b2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (1280 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568af87beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568af878e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568af87c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5afae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5afaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5afae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5afae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568af811bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568af811a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568af7f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568af4a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568af4a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5afae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5afae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5afae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568af4a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (1281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | s # | ... # `---data was truncated (10240/12680) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be1d0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564be1d07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564be1d0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f492bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f492bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f492bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f492bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be1ca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564be1ca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564be1c858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564be1934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564be1934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f492bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f492bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f492bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be1934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (1282 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = sitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = uitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = sitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = uitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptosi <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptosi <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptoui <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptoui <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm # | ... # `---data was truncated (10240/37578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bd353deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bd353ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bd353e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefe4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefe4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefe4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefe4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bd34d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bd34d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bd34b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bd3167e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bd3167b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fefe4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefe4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefe4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bd3167a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557de947deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557de947ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557de947e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ee8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ee8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ee8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ee8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557de9413bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557de9413a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557de93f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557de90a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557de90a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ee8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ee8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ee8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557de90a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (1284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564f424aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564f4247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564f424b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41ab049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41ab0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41ab049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41ab031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564f41e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564f41e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564f41c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564f3e74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564f3e74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41ab032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41ab0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41ab0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564f3e74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (1285 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | } # | # | ; Fun # | ... # `---data was truncated (10240/34633) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557729f7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557729f78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557729f7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1866e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1866e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1866e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1866e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557729f11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557729f11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557729ef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557729ba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557729ba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1866e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1866e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1866e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557729ba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (1286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9b98caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9b98c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9b98cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee72d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee72d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee72d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee72d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9b9860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9b9860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9b98458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9b94f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9b94f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee72d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee72d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee72d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9b94f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (1287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b050eaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b050eabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b050eaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb757905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb75795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb757905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7578ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b050e44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b050e44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b050e298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b050ad8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b050ad8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7578eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7578ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7578ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b050ad8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1288 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055730ad63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055730ad60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055730ad6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3598449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35984a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3598449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3598431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055730acf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055730acf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055730acde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055730a98de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055730a98db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3598432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35984330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35984330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055730a98da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (1289 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nx # | ... # `---data was truncated (10240/83629) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b596911eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b59690ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b59691262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4fdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5968a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5968a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b59688c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b59653be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b59653bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b59653ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (1290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cb5218eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cb5215e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cb521962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc11a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc11a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc11a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc11a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cb51aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560cb51aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560cb51938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560cb4e42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560cb4e42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc11a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc11a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc11a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cb4e42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (1291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (1292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (1293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d7fe8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d7fe8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d7fe8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c62733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c6278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c62733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c6271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d7fe24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d7fe24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d7fe098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d7fab8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d7fab8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c6271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c6271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c6271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d7fab8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (1294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557faa725eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557faa722e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557faa72662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab62933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab6298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab62933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab6291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557faa6bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557faa6bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557faa6a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557faa34fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557faa34fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab6291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab6291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab6291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557faa34fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (1295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587bfb96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587bfb93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587bfb9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbc7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbc74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbc7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbc7431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587bfb2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587bfb2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587bfb118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587bf7c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587bf7c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbc7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbc74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbc74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587bf7c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (1296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1ead6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1ead6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1ead6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b1c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b1c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b1c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b1c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1ead03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1ead03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1eace88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1ea997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1ea997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b1c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b1c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b1c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1ea997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (1297 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (1298 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/246614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055637eda7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055637eda4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055637eda862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6c5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6c515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6c5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6c50ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055637ed3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055637ed3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055637ed228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055637e9d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055637e9d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6c50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6c50ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6c50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055637e9d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (1299 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623e0cf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623e0cf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623e0cf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f127ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f127aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f127ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f127ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623e0c8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623e0c8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623e0c738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623e0922e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623e0922b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f127ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f127ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f127ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623e0922a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (1300 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592c35d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592c35d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592c35d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadc2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadc20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadc2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadc2031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c356cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592c356ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592c35518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592c3200e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592c3200b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadc2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadc20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadc20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c3200a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (1301 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fadeda8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fadeda5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fadeda962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8230d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8230d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8230d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8230d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faded3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faded3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faded238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fade9d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fade9d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8230d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8230d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8230d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fade9d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (1302 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align # | ... # `---data was truncated (10240/30281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055d27f365eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d27f362e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d27f36662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a39933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a3998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a39933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a3991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d27f2fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d27f2fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d27f2e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d27ef8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d27ef8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a3991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a3991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a3991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d27ef8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (1303 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (1304 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a155358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a155355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a15535962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4301f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4301f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4301f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4301eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1552eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1552eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1552d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a154f82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a154f82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4301eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4301eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4301eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a154f82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (1305 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, # | ... # `---data was truncated (10240/20307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571ba124eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571ba121e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571ba12562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7111c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7111ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7111c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7111c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571ba0babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571ba0baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571ba09f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571b9d4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571b9d4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7111c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7111c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7111c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571b9d4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (1306 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (1307 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d696f26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d696f23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d696f2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa655d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa655d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa655d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa655ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d696ebcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d696ebca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d696ea18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d696b50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d696b50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa655ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa655cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa655cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d696b50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (1308 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055580f9d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055580f9d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055580f9d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f206d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f206d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f206d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f206d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055580f96ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055580f96ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055580f9538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055580f602e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055580f602b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f206d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f206d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f206d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055580f602a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (1309 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m4_bf16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vcreate_v_bf16mf4x2( %v0, %v1) #0 { # | entry: # | %v0.add # | ... # `---data was truncated (10240/71275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564b5a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564b5a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564b5a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3b7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3b76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3b7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3b7631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564b59a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564b59a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564b598b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564b563ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564b563ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3b7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3b76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3b76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564b563aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1310 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e22df77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e22df74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e22df7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac72d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac72d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac72d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac72d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e22df0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e22df0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e22def28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e22dba1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e22dba1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac72d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac72d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac72d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e22dba1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (1311 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055646d02eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055646d02be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055646d02f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd07bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd07bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd07bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd07bced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055646cfc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055646cfc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055646cfa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055646cc58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055646cc58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd07bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd07bcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd07bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055646cc58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (1312 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # | #0 0x00005586b0a9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586b0a9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586b0a9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9872b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9872b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9872b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9872b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586b0a34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586b0a34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586b0a198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586b06c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586b06c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9872b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9872b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9872b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586b06c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (1313 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed8696eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed8696be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed8696f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe65333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe6538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe65333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe6531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed86904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed86904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed868e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed86598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed86598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe6531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe6531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe6531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed86598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-crc32.c (1314 of 27910) ******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd7123aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd71237e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd7123b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f738f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f738f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f738f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f738f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd711d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd711d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd711b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd70e64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd70e64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f738f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f738f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f738f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd70e64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (1315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i6 # | ... # `---data was truncated (10240/67158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d753a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d753a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d753a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f303e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f303e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f303e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f303e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d75399ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d75399ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7539838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d753632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d753632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f303e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f303e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f303e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d753632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (1316 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f696d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f696d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f696d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f5cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f5cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f5cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f5cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f6966bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f6966ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f696508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f692ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f692ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f5cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f5cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f5cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f692ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (1317 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (1318 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbc5bb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbc5bb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbc5bb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1d2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1d28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1d2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1d2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbc5b49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbc5b49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbc5b2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbc57dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbc57ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1d2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1d28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1d28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbc57dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (1319 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564919d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564919d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564919d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd547533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd54758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd547533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd54751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564919d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564919d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564919cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649199a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649199a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd54751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd54751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd54751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649199a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (1320 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d38131feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d38131ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d38132062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8dff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8dff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8dff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8dff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3812b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3812b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d38129a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d380f49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d380f49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8dff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8dff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8dff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d380f49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1321 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf3d11beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf3d118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf3d11c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddda533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddda58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddda533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddda51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf3d0b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf3d0b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf3d0968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf3cd45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf3cd45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddda51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddda51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddda51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf3cd45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (1322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | % # | ... # `---data was truncated (10240/47698) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055649e2cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055649e2cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055649e2d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6957f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6957f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6957f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6957f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055649e265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055649e265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055649e24a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055649def9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055649def9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6957f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6957f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6957f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055649def9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (1323 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1abd97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1abd94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1abd9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdbff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdbff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdbff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdbff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1abd2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1abd2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1abd128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1ab9c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1ab9c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbdbff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdbff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdbff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1ab9c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (1324 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5a9b72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5a9b6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5a9b7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd323449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3234a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd323449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd323431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5a9b08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5a9b08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5a9aed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5a979ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5a979cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd323432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3234330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3234330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5a979ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1325 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c59d1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c59d1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c59d1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c5b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c5b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c5b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c5b6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c59cb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c59cb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c59c998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c59948e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c59948b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c5b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c5b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c5b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c59948a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (1326 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2d69ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2d69dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2d69de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10f8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10f835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10f8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10f82ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2d6973bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2d6973a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2d69588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2d6607e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2d6607b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10f82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10f82ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10f82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2d6607a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (1327 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563f58696eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f58693e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f5869762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd53221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5322725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd53221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd532203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f5862cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f5862ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f586118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f582c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f582c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd532204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5322050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5322050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f582c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (1328 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634f2b75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634f2b72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634f2b7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5ed831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634f2b0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634f2b0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634f2af08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634f279fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634f279fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5ed8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634f279fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (1329 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (1330 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9f1b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9f1b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9f1b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c5821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c582725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c5821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c58203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9f1aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9f1aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9f1a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9f1739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9f1739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c58204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c582050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c582050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9f1739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (1331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055711cac9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055711cac6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055711caca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe2bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe2bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe2bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe2bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055711ca5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055711ca5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055711ca448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055711c6f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055711c6f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe2bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe2bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe2bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055711c6f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (1332 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/81756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a26b059eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a26b056e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a26b05a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce1a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a26afefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a26afefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a26afd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a26ac83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a26ac83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ce1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce1a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a26ac83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (1333 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (1334 of 27910) ******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.annotated_flex = type { i64, i8, [0 x i8] } # | # | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8 # | @sink = external global i64, align 8 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_fam(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %2 = ptrtoint ptr %arraydecay to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %3 = icmp sgt i64 %flexible_array_member_size, -1 # | %4 = select i1 %3, i64 %flexible_array_member_size, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_subscript(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2 # | %2 = ptrtoint ptr %arrayidx to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 2 # | %3 = icmp sgt i64 %result, -1 # | %4 = and i1 true, %3 # | %5 = select i1 %4, i64 %result, i64 0 # | ret i64 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_addrof(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %2 = ptrtoint ptr %fam to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_fam() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %0 = icmp sgt i64 %flexible_array_member_size, -1 # | %1 = select i1 %0, i64 %flexible_array_member_size, i64 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_subscript() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %0 = icmp sgt i64 %result, -1 # | %1 = and i1 true, %0 # | %2 = select i1 %1, i64 %result, i64 0 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_addrof() #0 { # | entry: # | %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_fam(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %2 = icmp sgt i64 %flexible_array_member_size, -1 # | %3 = select i1 %2, i64 %flexible_array_member_size, i64 0 # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %2 = icmp sgt i64 %result, -1 # | %3 = and i1 true, %2 # | %4 = select i1 %3, i64 %result, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000564c56e75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c56e72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c56e7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f429b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f429b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f429b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f429b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c56e0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c56e0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c56df08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c56a9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c56a9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f429b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f429b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f429b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c56a9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (1335 of 27910) ******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # | #0 0x00005558506a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558506a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558506a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6736e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6736ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6736e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6736e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055585063dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055585063da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558506228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558502d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558502d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6736e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6736e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6736e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558502d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (1336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eed4a9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eed4a99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eed4a9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd862d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd862d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd862d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd862d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eed4a32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eed4a32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eed4a178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eed46c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eed46c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd862d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd862d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd862d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eed46c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (1337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2_m( %mask, # | ... # `---data was truncated (10240/13544) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055800083ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558000839e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055800083d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f644b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f644b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f644b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f644b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580007d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005580007d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580007b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558000466e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558000466b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f644b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f644b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f644b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558000466a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (1338 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (1339 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (1340 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (1341 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af9c8cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af9c8c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af9c8cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed67d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed67d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed67d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed67d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af9c861bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af9c861a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af9c8468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af9c4f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af9c4f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed67d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed67d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed67d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9c4f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (1342 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (1343 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (1344 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (1345 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055589709eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055589709be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055589709f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f354ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f354ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f354ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f354ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555897034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555897034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558970198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555896cc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555896cc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f354ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f354ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f354ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555896cc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (1346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocall # | ... # `---data was truncated (10240/12425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643bfde1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643bfddee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643bfde262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb908733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb90878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb908733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb90871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643bfd77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643bfd77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643bfd5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643bfa0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643bfa0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb90871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb90871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb90871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643bfa0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (1347 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db8cd9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db8cd98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db8cd9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd347333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd34738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd347333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd34731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db8cd31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db8cd31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db8cd168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db8c9c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db8c9c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd34731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd34731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd34731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db8c9c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055586796ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555867969e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055586796d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1810b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1810b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1810b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1810b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555867902bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555867902a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558678e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555867596e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555867596b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1810b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1810b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1810b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555867596a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (1349 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632caa5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632caa5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632caa6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf46d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf46d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf46d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf46d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632ca9f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632ca9f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632ca9da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632ca689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632ca689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf46d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf46d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf46d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632ca689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (1350 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (1351 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056191c807eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056191c804e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056191c80862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62bd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62bd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62bd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62bd431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056191c79dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056191c79da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056191c7828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056191c431e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056191c431b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62bd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62bd4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62bd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056191c431a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (1352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a323d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a323d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a323d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3a2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3a2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3a2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3a2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a3236bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a3236ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a323508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a31fffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a31fffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3a2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3a2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3a2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a31fffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (1353 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a331d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a331cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a331d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66dd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a33166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a33166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a3314b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a32dfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a32dfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f66dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a32dfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (1354 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (1355 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558af26f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558af26f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558af26f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e7fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e7faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e7fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e7fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558af2689bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558af2689a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558af266e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558af231de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558af231db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e7fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e7fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e7fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558af231da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (1356 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623f99f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623f99f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623f99fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c95d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c95d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c95d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c95d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623f998fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623f998fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623f99748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623f9623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623f9623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c95d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c95d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c95d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623f9623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (1357 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (1358 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @l # | ... # `---data was truncated (10240/62760) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647fbb41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647fbb3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647fbb4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f18733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f1878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f18733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f1871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647fbad7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647fbad7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647fbabc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647fb76be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647fb76bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f1871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f1871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f1871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647fb76ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (1359 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, al # | ... # `---data was truncated (10240/72135) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b02ee6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b02ee3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b02ee762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac88733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac8878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac88733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac8871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b02e7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b02e7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b02e618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b02b10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b02b10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac8871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac8871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac8871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b02b10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (1360 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c97f797eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c97f794e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c97f79862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fcdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fcdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fcdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fcdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c97f72dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c97f72da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c97f7128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c97f3c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c97f3c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fcdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fcdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fcdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c97f3c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (1361 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | # | ... # `---data was truncated (10240/34641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8c9e25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8c9e22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8c9e2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8705449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87054a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8705449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8705431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8c9dbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8c9dbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8c9da08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8c9a4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8c9a4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8705432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87054330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87054330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8c9a4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (1362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c27bfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c27bfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c27bfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f318cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f318cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f318cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f318cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c27b93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c27b93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c27b788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c27827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c27827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f318cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f318cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f318cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c27827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (1363 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cf7c0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cf7c0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cf7c0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14cbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cf7ba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cf7ba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cf7b898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cf7838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cf7838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cf7838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (1364 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625117cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625117c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625117cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f482f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f482f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f482f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f482f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562511761bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562511761a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625117468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625113f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625113f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f482f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f482f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f482f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625113f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (1365 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (1366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i # | ... # `---data was truncated (10240/51303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce8b6baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce8b6b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce8b6bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11d7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11d798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11d7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11d791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce8b650bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce8b650a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce8b6358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce8b2e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce8b2e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f11d791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11d791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11d791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce8b2e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (1367 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (1368 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb33e65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb33e62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb33e6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccb5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccb5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccb5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccb5a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb33dfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb33dfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb33de08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb33a8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb33a8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccb5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccb5a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccb5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb33a8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (1369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055def17edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055def17eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055def17ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04f9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055def1783bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055def1783a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055def17688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055def1417e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055def1417b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04f96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055def1417a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (1370 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654350c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654350bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654350c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84b3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565435056bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565435056a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056543503b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565434ceae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565434ceab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565434ceaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (1371 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d59433eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d59430e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d5943462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb831733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb83178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb831733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb83171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d593c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d593c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d593ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d5905de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d5905db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb83171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb83171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb83171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d5905da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (1372 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2fa2caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2fa2c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2fa2cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc74f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc74f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc74f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc74f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2fa260bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2fa260a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2fa2458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2f9ef4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2f9ef4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc74f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc74f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc74f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2f9ef4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (1373 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a9299deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a9299ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a9299e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ee3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ee378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ee3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ee371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a92933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a92933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a929188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a925c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a925c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ee371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ee371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ee371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a925c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (1374 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aed9920eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aed991de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aed992162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5167905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f516795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5167905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51678ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aed98b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aed98b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aed989b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aed954ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aed954ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51678eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51678ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51678ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aed954aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (1375 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.add # | ... # `---data was truncated (10240/14453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e1af57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e1af54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e1af5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1eba933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1eba98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1eba933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1eba91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e1aeedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e1aeeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e1aed28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e1ab81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e1ab81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1eba91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1eba91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1eba91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e1ab81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (1376 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1b9eceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1b9ecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1b9ecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde3b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde3b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde3b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde3b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1b9e64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1b9e64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1b9e498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1b9af8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1b9af8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde3b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde3b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde3b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1b9af8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (1377 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055652ab4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055652ab47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055652ab4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8328c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8328ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8328c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8328c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055652aae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055652aae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055652aac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055652a774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055652a774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8328c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8328c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8328c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055652a774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (1378 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558946b87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558946b84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558946b8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb01f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb01f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb01f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb01f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558946b1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558946b1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558946b028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589467b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589467b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb01f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb01f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb01f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589467b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (1379 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.a # | ... # `---data was truncated (10240/73947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610f9fd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610f9fd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610f9fd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8c4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610f9f6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610f9f6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610f9f528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610f9c01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610f9c01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8c4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610f9c01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (1380 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, alig # | ... # `---data was truncated (10240/26754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ce6c59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ce6c56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ce6c5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5862b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5862b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5862b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5862b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ce6befbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ce6befa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ce6bd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ce6883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ce6883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5862b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5862b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5862b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ce6883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (1381 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ae2bbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ae2bb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ae2bbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2906933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f290698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2906933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f290691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ae2b50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ae2b50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ae2b358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ae27e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ae27e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f290691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f290691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f290691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ae27e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (1382 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 # | ... # `---data was truncated (10240/67006) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563195152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056319514fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056319515362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2e241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2e24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2e241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2e2403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631950e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631950e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631950cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563194d7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563194d7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2e2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2e24050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2e24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563194d7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (1383 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b3dcc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b3dcbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b3dcc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7899933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f789998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7899933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f789991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b3dc56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b3dc56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b3dc3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b3d8eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b3d8eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f789991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f789991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f789991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b3d8eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (1384 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 nounde # | ... # `---data was truncated (10240/26592) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056511a50aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056511a507e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056511a50b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77bca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77bcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77bca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77bca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056511a4a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056511a4a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056511a4858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056511a134e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056511a134b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77bca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77bca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77bca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056511a134a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (1385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d373d17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d373d14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d373d1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d73305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d73305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d732ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d373cadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d373cada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d373c928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d373941e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d373941b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d732eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d732ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d732ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d373941a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (1386 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616ddeafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616ddeace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616ddeb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7ead1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616dde45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616dde45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616dde2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616ddad9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616ddad9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616ddad9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5faf0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5faf0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5faf0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b16049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b16049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b16031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5faea4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5faea4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5fae898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5fab38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5fab38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b16032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b160330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5fab38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (1388 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055681c728eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055681c725e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055681c72962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72ca249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72ca2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72ca249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72ca231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055681c6bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055681c6bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055681c6a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055681c352e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055681c352b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f72ca232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72ca2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72ca2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055681c352a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (1389 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626c9f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626c9f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626c9f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf71933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf7198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf71933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf7191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626c9f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626c9f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626c9f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626c9bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626c9bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf7191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf7191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf7191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626c9bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (1390 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6bcfe8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6bcfe5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6bcfe962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbd1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbd1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbd1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbd1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6bcf7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6bcf7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6bcf638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6bcc12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6bcc12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbd1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbd1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbd1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6bcc12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (1391 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d3d359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d3d356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d3d35a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ae9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ae978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ae9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ae971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d3d2efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d3d2efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d3d2d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d3cf83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d3cf83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ae971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ae971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ae971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d3cf83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (1392 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = ca # | ... # `---data was truncated (10240/67474) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055beda92eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055beda92be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055beda92f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d28c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d28ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d28c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d28c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055beda8c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055beda8c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055beda8a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055beda558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055beda558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d28c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d28c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d28c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055beda558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1393 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d36a93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d36a90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d36a9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa027d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa027d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa027d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa027d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d36a29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d36a29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d36a0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d366bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d366bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa027d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa027d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa027d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d366bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (1394 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b24077eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b24074e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b2407862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6b7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6b72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6b7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6b7231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b2400dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b2400da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b23ff28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b23ca1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b23ca1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6b7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6b72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6b72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b23ca1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (1395 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 # | ... # `---data was truncated (10240/11881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628b602beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628b6028e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628b602c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c91c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c91ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c91c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c91c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628b5fc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628b5fc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628b5fa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628b5c55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628b5c55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c91c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c91c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c91c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628b5c55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (1396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557319b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557319b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557319b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f484c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f484c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f484c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f484c0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557319ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557319ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557319ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557319768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557319768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f484c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f484c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f484c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557319768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (1397 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | # | ... # `---data was truncated (10240/28350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558301ea6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558301ea3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558301ea762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32ab21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32ab2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32ab21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32ab203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558301e3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558301e3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558301e218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558301ad0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558301ad0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32ab204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32ab2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32ab2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558301ad0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (1398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055948e497eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055948e494e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055948e49862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6eed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6eed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6eed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6eed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055948e42dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055948e42da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055948e4128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055948e0c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055948e0c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6eed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6eed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6eed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055948e0c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (1399 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f7e3c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f7e3c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f7e3c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1369333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f136938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1369333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f136931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f7e35bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f7e35ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f7e3408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f7dfefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f7dfefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f136931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f136931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f136931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f7dfefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (1400 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556775b2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556775b2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556775b3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5769933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5769933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556775ac5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556775ac5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556775aaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556775759e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556775759b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f576991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556775759a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1401 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/95437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d286e47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d286e44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d286e4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ee7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ee7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ee7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ee7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d286dddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d286ddda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d286dc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d286a71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d286a71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ee7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ee7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ee7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d286a71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (1402 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (1403 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (1404 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587d360beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587d3608e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587d360c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2648a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2648aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2648a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2648a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587d35a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587d35a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587d35868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587d3235e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587d3235b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2648a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2648a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2648a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587d3235a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (1405 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ff206feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ff206ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ff207062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1e9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1e978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1e9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1e971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ff2005bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ff2005a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ff1fea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ff1c99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ff1c99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1e971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1e971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1e971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ff1c99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1406 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056154e4abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056154e4a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056154e4ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49e6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49e6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49e6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49e6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056154e441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056154e441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056154e4268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056154e0d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056154e0d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49e6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49e6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49e6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056154e0d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (1407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056098aab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056098aab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056098aab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf30733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf3078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf30733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf3071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056098aa4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056098aa4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056098aa318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056098a6e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056098a6e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf3071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf3071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf3071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056098a6e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (1408 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055651764ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556517649e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055651764d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f666bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f666bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f666bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f666bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565175e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565175e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565175c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556517276e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556517276b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f666bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f666bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f666bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556517276a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (1409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e71d780eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e71d77de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e71d78162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32e7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32e74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32e7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32e7431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e71d716bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e71d716a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e71d6fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e71d3aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e71d3aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32e7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32e74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32e74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e71d3aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (1410 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654b5e19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654b5e16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654b5e1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37ae933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37ae98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37ae933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37ae91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654b5dafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654b5dafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654b5d948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654b5a43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654b5a43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37ae91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37ae91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37ae91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654b5a43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (1411 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648ed9d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648ed9cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648ed9d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f983c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f983c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f983c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f983c031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648ed968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648ed968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648ed94d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648ed5fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648ed5fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f983c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f983c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f983c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648ed5fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1412 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df63147eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df63144e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df6314862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49cba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49cbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49cba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49cba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df630ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df630dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df630c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df62d71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df62d71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49cba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49cba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49cba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df62d71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (1413 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560cb959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560cb956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560cb95a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44fc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44fc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44fc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44fc031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560cb8efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560cb8efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560cb8d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560cb583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560cb583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44fc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44fc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44fc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560cb583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (1414 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629ae539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629ae536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629ae53a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0204705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f020475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0204705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02046ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629ae4cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629ae4cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629ae4b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629ae163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629ae163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02046eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02046ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02046ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629ae163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (1415 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b720662eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b72065fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b72066362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06f0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06f038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06f0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06f031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7205f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7205f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7205dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b72028ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b72028cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06f031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06f031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06f031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b72028ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (1416 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (1417 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556589f3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556589f37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556589f3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effb5d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effb5d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effb5d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effb5ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556589ed0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556589ed0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556589eb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556589b64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556589b64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effb5ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effb5cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effb5cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556589b64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (1418 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %v # | ... # `---data was truncated (10240/110062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0be09eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0be09be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0be09f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47bc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47bc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47bc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47bc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0be034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0be034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0be0198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0bdcc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0bdcc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47bc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47bc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47bc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0bdcc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (1419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ff8958eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ff8955e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ff895962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3bd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3bd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3bd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3bd6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ff88eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ff88eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ff88d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ff8582e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ff8582b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3bd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3bd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3bd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ff8582a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (1420 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffd56a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ffd569fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ffd56a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3763d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3763d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3763d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3763d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffd5638bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ffd5638a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ffd561d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ffd52cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ffd52ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3763d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3763d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3763d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffd52cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (1421 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556267770eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055626776de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055626777162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc021133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc02118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc021133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc02111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556267706bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556267706a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562676eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055626739ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055626739ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc02111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc02111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc02111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055626739aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (1422 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e9c6a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e9c6a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e9c6a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab59e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab59ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab59e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab59e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e9c63cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e9c63ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e9c6218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e9c2d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e9c2d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab59e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab59e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab59e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e9c2d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (1423 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f7e144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f7e141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f7e14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f420b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f420b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f420b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f420b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f7e0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f7e0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f7e0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f7dd6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f7dd6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f420b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f420b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f420b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f7dd6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (1424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562491966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562491963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056249196762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f768b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f768b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f768b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f768b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624918fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624918fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624918e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562491590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562491590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f768b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f768b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f768b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562491590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (1425 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , float, i64) # | ... # `---data was truncated (10240/34765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d225bc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d225bc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d225bc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad1b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad1b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad1b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad1b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d225b5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d225b5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d225b418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2257f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2257f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad1b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad1b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad1b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2257f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (1426 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644ec549eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644ec546e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644ec54a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8acc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8acca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8acc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8acc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644ec4dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644ec4dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644ec4c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644ec173e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644ec173b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8acc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8acc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8acc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644ec173a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (1427 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056431018deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056431018ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056431018e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc46a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc46a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc46a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc46a803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564310123bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564310123a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643101088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056430fdb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056430fdb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc46a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc46a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc46a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056430fdb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (1428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc22076eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc22073e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc2207762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc06849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc068a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc06849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc06831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc2200cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc2200ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc21ff18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc21ca0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc21ca0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc06832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc068330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc068330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc21ca0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (1429 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633578eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633578ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633578ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0807e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0807ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0807e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0807e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563357884bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563357884a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633578698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563357518e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563357518b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0807e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0807e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0807e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563357518a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (1430 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8c3b56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8c3b53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8c3b5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4a8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4a80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4a8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4a8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8c3aecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8c3aeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8c3ad18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8c3780e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8c3780b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4a8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4a80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4a80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8c3780a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (1431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055932ee0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055932ee08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055932ee0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2541249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2541249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2541231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055932eda1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055932eda1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055932ed868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055932ea35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055932ea35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2541232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25412330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055932ea35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1432 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/77054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585c1b27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585c1b24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585c1b2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc477b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc477b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc477b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc477b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585c1abdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585c1abda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585c1aa28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585c1751e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585c1751b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc477b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc477b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc477b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585c1751a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (1433 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b9e900eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b9e8fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b9e90162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff449f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff449f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff449f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff449f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b9e896bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b9e896a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b9e87b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b9e52ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b9e52ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff449f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff449f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff449f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b9e52aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (1434 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf1265ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf12659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf1265d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0025933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f002598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0025933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f002591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf125f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf125f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf125d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf12286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf12286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f002591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f002591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f002591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf12286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (1435 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d30f34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d30f31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d30f3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92f0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92f078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92f0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92f071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d30ecabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d30ecaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d30eaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d30b5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d30b5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f92f071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92f071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92f071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d30b5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (1436 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3aeda8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b3aeda5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3aeda962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2928333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f292838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2928333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f292831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3aed3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b3aed3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3aed238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3ae9d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3ae9d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f292831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f292831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f292831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3ae9d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (1437 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a0a2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615a0a28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615a0a2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd72d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd72d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd72d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a09c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615a09c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615a09a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615a0655e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615a0655b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd72d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd72d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd72d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a0655a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (1438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580b4600eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580b45fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580b460162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe73ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe73eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe73ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe73ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580b4596bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005580b4596a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580b457b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580b422ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580b422ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe73ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe73ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe73ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580b422aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aec3edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558aec3eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558aec3ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0a8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0a818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0a8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0a811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aec383bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558aec383a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558aec3688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558aec017e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558aec017b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0a811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0a811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0a811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aec017a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (1440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb2f6faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb2f6f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb2f6fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb2f690bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb2f690a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb2f6758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb2f324e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb2f324b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ce7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb2f324a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (1441 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso # | ... # `---data was truncated (10240/148012) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055967b420eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055967b41de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055967b42162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f802c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f802c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f802c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f802c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055967b3b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055967b3b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055967b39b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055967b04ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055967b04ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f802c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f802c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f802c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055967b04aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (1442 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (1443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (1444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055835e3a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055835e3a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055835e3a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa6a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa6a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa6a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa6a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055835e33dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055835e33da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055835e3228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055835dfd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055835dfd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa6a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa6a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa6a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055835dfd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (1445 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d99c50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d99c4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d99c5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf75649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf75649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf75631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d99be6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d99be6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d99bcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d9987ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d9987ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf75632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf756330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d9987aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (1446 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx # | ... # `---data was truncated (10240/78682) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a141a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a141a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a141a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a9a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a9a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a9a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a9a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a1413cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a1413ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a141218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a13dd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a13dd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a9a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a9a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a9a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a13dd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (1447 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (1448 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (1449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fffa68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fffa65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fffa6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe528133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe52818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe528133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe52811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fff9febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fff9fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fff9e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fff692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fff692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe52811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe52811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe52811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fff692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (1450 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (1451 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ac15ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ac15e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ac15ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd650133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd65018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd650133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd65011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ac1581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ac1581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ac15668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ac1215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ac1215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd65011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd65011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd65011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ac1215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (1452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615ccdc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615ccdbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615ccdc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d5cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d5cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d5cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d5cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615ccd56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615ccd56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615ccd3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615cc9eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615cc9eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d5cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d5cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d5cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615cc9eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (1453 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cae429eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cae426e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cae42a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f463c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f463c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f463c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cae3bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cae3bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cae3a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cae053e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cae053b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f463c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f463c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f463c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cae053a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1454 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b055786eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b055783e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b05578762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84da849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84da8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84da849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84da831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b05571cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b05571ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0557018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0553b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0553b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84da832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84da8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84da8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0553b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (1455 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2 # | ... # `---data was truncated (10240/94673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627848bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627848bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627848be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a5ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a5ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a5ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a5ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562784853bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562784853a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627848388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627844e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627844e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a5ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a5ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a5ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627844e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1456 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e59baf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e59baf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e59baf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1086649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10866a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1086649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1086631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e59ba8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e59ba8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e59ba718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e59b720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e59b720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1086632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10866330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10866330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e59b720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (1457 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eedde8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eedde8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eedde8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f3e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f3e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f3e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f3e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eedde24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eedde24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eedde098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eeddab8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eeddab8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f3e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f3e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f3e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eeddab8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (1458 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563789368eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563789365e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056378936962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7233e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7233ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7233e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7233e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637892febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637892fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637892e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563788f92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563788f92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7233e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7233e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7233e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563788f92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (1459 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota # | ... # `---data was truncated (10240/94681) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cfc90deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cfc90ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cfc90e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a9ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a9ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a9ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a9ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cfc8a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cfc8a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cfc8888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cfc537e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cfc537b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a9ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a9ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a9ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cfc537a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (1460 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055707118beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557071188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055707118c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6f9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6f9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6f9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6f9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557071121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557071121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570711068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557070db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557070db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6f9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6f9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6f9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557070db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b09561eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b0955ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b0956262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc355e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc355ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc355e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc355e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b094f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b094f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b094dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b0918be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b0918bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc355e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc355e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc355e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b0918ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1462 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %bas # | ... # `---data was truncated (10240/60209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2b0a70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2b0a6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2b0a7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1360933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f136098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1360933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f136091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2b0a06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2b0a06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2b09eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2b069ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2b069ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f136091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f136091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f136091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2b069aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (1463 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (1464 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/97240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cc71cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563cc71cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563cc71ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5262505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f526255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5262505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52624ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cc7163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563cc7163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563cc71488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563cc6df7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563cc6df7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52624eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52624ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52624ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cc6df7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (1465 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32( %0, %1, %2, i32 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b22f899eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b22f896e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b22f89a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d35a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d35aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d35a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d35a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b22f82fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b22f82fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b22f8148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b22f4c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b22f4c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d35a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d35a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d35a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b22f4c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (1466 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c8e65aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c8e657e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c8e65b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8d7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8d735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8d7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8d72ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c8e5f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c8e5f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c8e5d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c8e284e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c8e284b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8d72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8d72ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8d72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c8e284a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (1467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561240732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056124072fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056124073362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5290333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f529038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5290333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f529031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612406c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612406c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612406ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056124035ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056124035cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f529031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f529031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f529031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056124035ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (1468 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (1469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a93704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a93701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a9370562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44ae649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44ae6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44ae649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44ae631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a9369abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a9369aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a9367f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a9332ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a9332eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44ae632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44ae6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44ae6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a9332ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (1470 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/12431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556722541eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055672253ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055672254262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b70933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b7098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b70933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b7091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567224d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567224d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567224bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055672216be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055672216bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b7091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b7091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b7091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055672216ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (1471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f9ba01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f9b9fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f9ba0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f9b997bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f9b997a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f9b97c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f9b62be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f9b62bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f9b62ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (1472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f43cab9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f43cab6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f43caba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cd7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cd718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cd7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cd711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f43ca4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f43ca4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f43ca348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f43c6e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f43c6e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cd711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cd711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cd711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f43c6e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (1473 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb4bac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb4babde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb4bac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f211ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f211ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f211ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f211ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb4ba56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb4ba56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb4ba3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb4b6eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb4b6eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f211ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f211ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f211ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb4b6eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (1474 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626325d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626325d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626325d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb859049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8590a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb859049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb859031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056263256cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056263256ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626325518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562632200e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562632200b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb859032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8590330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8590330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562632200a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (1475 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055937f417eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055937f414e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055937f41862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f024d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f024d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f024d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f024d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055937f3adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055937f3ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055937f3928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055937f041e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055937f041b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f024d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f024d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f024d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055937f041a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (1476 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_scatter_u32base_s32( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(, , , i64) # # | ... # `---data was truncated (10240/43213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000561ddab59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ddab56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ddab5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc732d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc732d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc732d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc732d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ddaaefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ddaaefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ddaad48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561dda783e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561dda783b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc732d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc732d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc732d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dda783a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (1477 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564120356eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564120353e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056412035762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d6ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d6ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641202ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641202eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641202d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056411ff80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056411ff80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d6ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056411ff80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (1478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm64-lanes.c (1479 of 27910) ******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %src, ptr %src.addr, align 8 # | %0 = load <2 x float>, ptr %src.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vdups_lane = extractelement <2 x float> %1, i32 0 # | store float %vdups_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %src, ptr %src.addr, align 8 # | %0 = load <1 x double>, ptr %src.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vdupd_lane = extractelement <1 x double> %1, i32 0 # | store double %vdupd_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b8a947eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b8a944e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b8a94862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4de0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4de0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4de0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4de0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b8a8ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b8a8dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b8a8c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b8a571e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b8a571b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4de0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4de0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4de0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b8a571a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (1480 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563eee064eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563eee061e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563eee06562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcd2d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcd2d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcd2d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcd2ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563eedffabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563eedffaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563eedfdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563eedc8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563eedc8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdcd2ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcd2cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcd2cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563eedc8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (1481 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae3e85deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae3e85ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae3e85e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4d1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4d1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4d1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4d1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae3e7f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae3e7f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae3e7d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae3e487e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae3e487b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4d1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4d1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4d1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae3e487a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (1482 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558901234eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558901231e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055890123562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7abed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7abed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7abed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7abed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589011cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005589011caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589011af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558900e5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558900e5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7abed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7abed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7abed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558900e5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (1483 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560180a19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560180a16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560180a1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb16c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb16c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb16c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb16c831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601809afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601809afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601809948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560180643e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560180643b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb16c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb16c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb16c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560180643a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (1484 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret bfloat %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x bfloat> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | !llvm.errno.tbaa = !{!6} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # | !6 = !{!7, !8, i64 0} # | !7 = !{!"__libc_errno", !8, i64 0} # | !8 = !{!"int", !9, i64 0} # | !9 = !{!"omnipotent char", !10, i64 0} # | !10 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000560ce60b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ce60b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ce60b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd90dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd90dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd90dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd90dced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ce604dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ce604da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ce60328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ce5ce1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ce5ce1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd90dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd90dcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd90dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ce5ce1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (1485 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, # | ... # `---data was truncated (10240/60217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff27b0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff27b08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff27b0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99ea849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99ea8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99ea849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99ea831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff27aa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff27aa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff27a868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff27735e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff27735b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99ea832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99ea8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99ea8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff27735a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (1486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a41f57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a41f54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a41f5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e95449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e954a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e95449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e95431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a41eedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a41eeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a41ed28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a41b81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a41b81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e95432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e954330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e954330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a41b81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (1487 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | s # | ... # `---data was truncated (10240/58326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f6a67eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f6a67be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f6a67f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fc5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fc5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fc5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fc5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f6a614bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f6a614a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f6a5f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f6a2a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f6a2a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fc5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fc5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fc5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f6a2a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (1488 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ded257eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ded254e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ded25862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8835e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8835ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8835e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8835e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ded1edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ded1eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ded1d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dece81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dece81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8835e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8835e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8835e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dece81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (1489 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, ali # | ... # `---data was truncated (10240/280217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e52d60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e52d5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e52d6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c1f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c1f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c1f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c1f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e52cf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e52cf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e52cdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e5298ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e5298ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c1f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c1f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c1f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e5298aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (1490 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056500a734eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056500a731e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056500a73562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f3f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f3f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f3f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f3f803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056500a6cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056500a6caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056500a6af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056500a35ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056500a35eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f3f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f3f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f3f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056500a35ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (1491 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612b791ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612b7919e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612b791d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c44e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c44e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c44e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c44e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612b78b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612b78b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612b78978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612b7546e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612b7546b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c44e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c44e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c44e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612b7546a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1492 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559125440eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055912543de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055912544162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b3b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b3b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b3b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b3b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591253d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591253d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591253bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055912506ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055912506ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b3b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b3b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b3b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055912506aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (1493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (1494 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056496cc84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056496cc81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056496cc8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf6ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf6ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf6ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf6ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056496cc1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056496cc1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056496cbff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056496c8aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056496c8aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf6ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf6ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf6ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056496c8aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (1495 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c06300feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c06300ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c06301062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8b9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8b918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8b9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8b911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c062fa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c062fa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c062f8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c062c39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c062c39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8b911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8b911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8b911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c062c39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (1496 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2eae86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2eae83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2eae8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc87e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc87e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc87e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc87e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2eae1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2eae1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2eae018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2eaab0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2eaab0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc87e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc87e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc87e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2eaab0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (1497 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556a261beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556a2618e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556a261c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bf8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bf875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bf8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bf86ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556a25b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556a25b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556a25968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556a2245e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556a2245b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bf86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bf86ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bf86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556a2245a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (1499 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556420b2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556420b2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556420b3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb86801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8680725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb86801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb868003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556420ac5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556420ac5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556420aaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556420759e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556420759b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb868004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8680050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8680050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556420759a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1501 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d3715beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d37158e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d3715c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ddeb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ddeb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ddeb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ddeaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d370f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d370f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d370d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d36d85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d36d85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ddeaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ddeaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ddeaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d36d85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (1502 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5922f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5922f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5922f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8356533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f835658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8356533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f835651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f59228bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f59228ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5922708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f591f1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f591f1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f835651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f835651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f835651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f591f1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (1503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056226174feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056226174ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056226175062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84c7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622616e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622616e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622616ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562261379e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562261379b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562261379a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/cx-complex-range-real.c (1504 of 27910) ******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %mul.rl = fmul float %a.real, %0 # | %mul.il = fmul float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.il, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul.rl = fmul float %.real, %0 # | %mul.il = fmul float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %mul.rl, ptr %.realp1, align 4 # | store float %mul.il, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %a.addr = alloca float, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul.rl = fmul float %0, %b.real # | %mul.ir = fmul float %0, %b.imag # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.ir, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = fdiv float %a.real, %0 # | %2 = fdiv float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %1, ptr %retval.realp, align 4 # | store float %2, ptr %retval.imagp, align 4 # | %3 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %2 = fdiv float %.real, %0 # | %3 = fdiv float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %2, ptr %.realp1, align 4 # | store float %3, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | store double %b, ptr %b.addr, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load double, ptr %a.imagp, align 8 # | %2 = load double, ptr %b.addr, align 8 # | %3 = fdiv double %a.real, %2 # | %4 = fdiv double %a.imag, %2 # | %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1 # | store double %3, ptr %retval.realp, align 8 # | store double %4, ptr %retval.imagp, align 8 # | %5 = load { double, double }, ptr %retval, align 8 # | ret { double, double } %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { double, double }, align 8 # | %a.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %1, align 8 # | store double %a, ptr %a.addr, align 8 # | %2 = load double, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | %b.real = load double, ptr %b.realp, align 8 # | %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | %b.imag = load double, ptr %b.imagp, align 8 # | %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2 # | %3 = extractvalue { double, double } %call, 0 # | %4 = extractvalue { double, double } %call, 1 # | %conv = fptrunc double %3 to float # | %conv1 = fptrunc double %4 to float # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %conv, ptr %retval.realp, align 4 # | store float %conv1, ptr %retval.imagp, align 4 # | %5 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %5 # | } # | # | declare { double, double } @__divdc3(double, double, double, double) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca double, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load double, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.real = load double, ptr %.realp, align 8 # | %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | %.imag = load double, ptr %.imagp, align 8 # | %2 = fdiv double %.real, %0 # | %3 = fdiv double %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | store double %2, ptr %.realp1, align 8 # | store double %3, ptr %.imagp2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 { # | entry: # | %retval = alloca { x86_fp80, x86_fp80 }, align 16 # | %b.addr = alloca x86_fp80, align 16 # | store x86_fp80 %b, ptr %b.addr, align 16 # | %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0 # | %a.real = load x86_fp80, ptr %a.realp, align 16 # | %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1 # | %a.imag = load x86_fp80, ptr %a.imagp, align 16 # | %0 = load x86_fp80, ptr %b.addr, align 16 # | %1 = fdiv x86_fp80 %a.real, %0 # | %2 = fdiv x86_fp80 %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1 # | store x86_fp80 %1, ptr %retval.realp, align 16 # | store x86_fp80 %2, ptr %retval.imagp, align 16 # | %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16 # | ret { x86_fp80, x86_fp80 } %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 { # | entry: # | %a.addr # | ... # `---data was truncated (10240/11567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055e707ddeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e707ddbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e707ddf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e38849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e388a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e38849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e38831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e707d74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e707d74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e707d598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e707a08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e707a08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e38832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e388330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e388330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e707a08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (1505 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f36e15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f36e12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f36e1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a28905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a2895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a28905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a288ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f36dabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f36daba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f36d908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f36a3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f36a3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a288eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a288ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a288ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f36a3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1506 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = fneg <8 x half> %1 # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = fneg <4 x float> %1 # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %c, ptr %c.addr, align 2 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = mul <8 x i16> %0, %.splat # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = add <8 x i16> %2, %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i32 %c, ptr %c.addr, align 4 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = mul <4 x i32> %0, %.splat # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = add <4 x i32> %2, %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, ali # | ... # `---data was truncated (10240/60411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055759c7d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055759c7d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055759c7d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb64741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6474725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb64741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb647403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055759c76cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055759c76ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055759c7518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055759c400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055759c400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb647404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6474050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6474050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055759c400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (1507 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, al # | ... # `---data was truncated (10240/28866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a42800eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a427fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a4280162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9468649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9468649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9468631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a42796bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a42796a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a4277b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a4242ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a4242ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9468632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94686330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a4242aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (1508 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7f33b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7f33ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7f33b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa511b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa511b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa511b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa511b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7f3346bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7f3346a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7f332b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7f2fdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7f2fdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa511b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa511b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa511b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7f2fdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (1509 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksed1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4f315feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4f315ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4f316062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd78bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd78bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4f30f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c4f30f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4f30da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4f2d89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4f2d89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd78bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4f2d89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (1510 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559507060eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055950705de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055950706162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd117b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd117b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd117b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd117b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559506ff6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559506ff6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559506fdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559506c8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559506c8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd117b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd117b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd117b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559506c8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (1511 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efe476deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055efe476ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055efe476e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f981c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f981c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f981c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f981c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efe4703bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055efe4703a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055efe46e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055efe4397e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055efe4397b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f981c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f981c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f981c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efe4397a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1512 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (1513 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559124583eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559124580e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055912458462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa401133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa40118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa401133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa40111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559124519bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559124519a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591244fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591241ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591241adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa40111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa40111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa40111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591241ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (1514 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619b8e85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619b8e82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619b8e8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f295f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f295f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f295f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f295f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619b8e1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619b8e1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619b8e008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619b8aafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619b8aafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f295f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f295f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f295f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619b8aafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (1515 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa89b7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa89b7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa89b7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8ae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8ae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8ae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8ae231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa89b13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa89b13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa89af88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa897a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa897a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8ae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8ae2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8ae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa897a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (1516 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec74d57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec74d54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec74d5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd43db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd43db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd43db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd43db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec74cedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec74ceda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec74cd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec74981e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec74981b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd43db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd43db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd43db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec74981a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (1517 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, al # | ... # `---data was truncated (10240/223137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d0aa3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d0aa3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d0aa3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c4c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c4c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c4c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c4c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d0a9d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d0a9d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d0a9b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d0a667e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d0a667b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c4c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c4c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c4c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d0a667a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (1518 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f58f77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f58f74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f58f7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ccbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ccbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ccbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ccbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f58f0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f58f0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f58ef28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f58ba1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f58ba1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ccbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ccbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ccbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f58ba1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (1519 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (1520 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562afaf53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562afaf50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562afaf5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08fd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562afaee9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562afaee9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562afaece8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562afab7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562afab7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562afab7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1521 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1522 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c1b688eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c1b685e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c1b68962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1031c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1031ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1031c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1031c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c1b61ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c1b61ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c1b6038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c1b2b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c1b2b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1031c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1031c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1031c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c1b2b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1523 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (1524 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586688eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586688e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586688ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d7fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d7fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d7fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d7fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558668882bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558668882a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586688678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558668516e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558668516b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d7fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d7fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d7fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558668516a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (1525 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595c7ea7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595c7ea4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595c7ea862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb364c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb364ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb364c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb364c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595c7e3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595c7e3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595c7e228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595c7ad1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595c7ad1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb364c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb364c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb364c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595c7ad1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1526 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e83c188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e83c185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e83c18962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd05f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd05f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd05f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd05f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e83c11ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e83c11ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e83c1038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e83bdb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e83bdb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd05f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd05f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd05f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e83bdb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1527 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2, align 8 # | %extract = extractelement <1 x double> %5, i32 0 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.fma.f64(double, double, double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <2 x double>, ptr %__s2, align 16 # | %extract = extractelement <2 x double> %5, i32 1 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret_443 = alloca float, align 4 # | %__s0_443 = alloca float, align 4 # | %__s1_443 = alloca float, align 4 # | %__s2_443 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_443, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1_443, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2_443, align 8 # | %3 = load float, ptr %__s0_443, align 4 # | store float %3, ptr %__s0, align 4 # | %4 = load float, ptr %__s1_443, align 4 # | %fneg = fneg float %4 # | store float %fneg, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2_443, align 8 # | store <2 x float> %5, ptr %__s2, align 8 # | %6 = load float, ptr %__s0, align 4 # | %7 = load float, ptr %__s1, align 4 # | %8 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %8, i32 1 # | %9 = call float @llvm.fma.f32(float %7, float %extract, float %6) # | store float %9, ptr %ref.tmp, align 4 # | %10 = load float, ptr %ref.tmp, align 4 # | store float %10, ptr %__ret, align 4 # | %11 = load float, ptr %__ret, align 4 # | store float %11, ptr %tmp, align 4 # | %12 = load float, ptr %tmp, align 4 # | store float %12, ptr %__ret_443, align 4 # | %13 = load float, ptr %__ret_443, align 4 # | store float %13, ptr %tmp1, align 4 # | %14 = load float, ptr %tmp1, align 4 # | ret float %14 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.fma.f32(float, float, float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret_449 = alloca <1 x double>, align 8 # | %__s0_449 = alloca <1 x double>, align 8 # | %__s1_449 = alloca <1 x double>, align 8 # | %__s2_449 = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | %tmp3 = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0_449, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_449, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2_449, align 8 # | %3 = load <1 x double>, ptr %__s0_449, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s1_449, align 8 # | %fneg = fneg <1 x double> %4 # | store <1 x double> %fneg, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2_449, align 8 # | store <1 x double> %5, ptr %__s2, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = load <8 x i8>, ptr %__s1, align 8 # | %8 = load <8 x i8>, ptr %__s2, align 8 # | %9 = bitcast <8 x i8> %8 to <1 x double> # | %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %7 to <1 x double> # | %fmla1 = bitcast <8 x i8> %6 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %10 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %10, ptr %__ret, align 8 # | %11 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %11, ptr %tmp, align 8 # | %12 = load <1 x double>, ptr %tmp, align 8 # | store <1 x double> %12, ptr %__ret_449, align 8 # | %13 = load <1 x double>, ptr %__ret_449, align 8 # | store <1 x double> %13, ptr %tmp3, align 8 # | %14 = load <1 x double>, ptr %tmp3, align 8 # | ret <1 x double> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret_460 = alloca <1 x double>, align 8 # | %__s0_460 = alloca <1 x double>, align 8 # | %__s1_460 = alloca <1 x double>, align 8 # | %__s2_460 = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %_ # | ... # `---data was truncated (10240/12799) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557394c04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557394c01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557394c0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cc5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cc58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cc5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cc5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557394b9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557394b9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557394b7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055739482ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055739482eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cc5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cc58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cc58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055739482ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (1528 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561dbed7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561dbed7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561dbed8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad98849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad988a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad98849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad98831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dbed15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561dbed15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561dbecfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561dbe9a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561dbe9a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad98832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad988330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad988330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dbe9a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (1529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643a14c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643a14bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643a14c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f401c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f401c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f401c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f401c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643a1458bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643a1458a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643a143d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643a10ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643a10ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f401c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f401c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f401c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643a10eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (1530 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618f55dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618f55d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618f55dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5b021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5b02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5b021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5b0203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618f5571bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618f5571a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618f55568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618f5205e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618f5205b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5b0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5b02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5b02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618f5205a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (1531 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a468b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a468b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a468b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f910df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f910df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f910df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f910df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4684ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4684ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a468338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a464e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a464e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f910df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f910df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f910df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a464e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-vst.c (1532 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <4 x i16> # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x3_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0 # | store [3 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %4 = bitcast <8 x i8> %1 to <4 x i16> # | %5 = bitcast <8 x i8> %2 to <4 x i16> # | %6 = bitcast <8 x i8> %3 to <4 x i16> # | call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x4_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0 # | store [4 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3 # | %4 = load <8 x i8>, ptr %arrayidx6, align 8 # | %5 = bitcast <8 x i8> %1 to <4 x i16> # | %6 = bitcast <8 x i8> %2 to <4 x i16> # | %7 = bitcast <8 x i8> %3 to <4 x i16> # | %8 = bitcast <8 x i8> %4 to <4 x i16> # | call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float32x2x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <2 x float> # | %4 = bitcast <8 x i8> %2 to <2 x float> # | call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %s # | ... # `---data was truncated (10240/108866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f33c58beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f33c588e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f33c58c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4552849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45528a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4552849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4552831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f33c521bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f33c521a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f33c5068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f33c1b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f33c1b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4552832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45528330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45528330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f33c1b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (1533 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/63169) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648b8934eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648b8931e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648b893562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60eaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60eaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60eaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60eaa03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648b88cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648b88caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648b88af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648b855ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648b855eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60eaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60eaa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60eaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648b855ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1534 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (1535 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562997aa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562997aa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562997aa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff351933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff35198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff351933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff35191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562997a3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562997a3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562997a218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629976d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629976d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff35191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff35191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff35191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629976d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (1536 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64es(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64esm(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe2c490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe2c48de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe2c49162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fcb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fcb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fcb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fcb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe2c426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe2c426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe2c40b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe2c0bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe2c0bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fcb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fcb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fcb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe2c0baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (1537 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1920c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1920bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1920c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6a7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6a7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6a7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6a7c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a192056bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a192056a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a19203b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a191ceae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a191ceab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6a7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6a7c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6a7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a191ceaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (1538 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578892e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578892e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578892ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3d9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3d96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3d9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3d9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055788927fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055788927fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578892648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557888f13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557888f13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3d9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3d96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3d96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557888f13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (1539 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bb395eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560bb395be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560bb395f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fd4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fd478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fd4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fd471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bb38f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560bb38f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560bb38d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560bb3588e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560bb3588b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fd471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fd471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fd471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bb3588a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (1540 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %w.addr = alloca float, align 4 # | store float %w, ptr %w.addr, align 4 # | %0 = load float, ptr %w.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %1, i32 0 # | %2 = load float, ptr %__p0.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1 # | %3 = load float, ptr %__p0.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2 # | %4 = load float, ptr %__p0.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %5 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | store <4 x float> %5, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 { # | entry: # | %V.addr = alloca <1 x double>, align 8 # | %__ret_379 = alloca <2 x double>, align 16 # | %__s0_379 = alloca <1 x double>, align 8 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | %tmp1 = alloca <2 x double>, align 16 # | store <1 x double> %V, ptr %V.addr, align 8 # | %0 = load <1 x double>, ptr %V.addr, align 8 # | store <1 x double> %0, ptr %__s0_379, align 8 # | %1 = load <1 x double>, ptr %__s0_379, align 8 # | store <1 x double> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer # | store <2 x double> %lane, ptr %ref.tmp, align 16 # | %4 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %4, ptr %__ret, align 16 # | %5 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %5, ptr %tmp, align 16 # | %6 = load <2 x double>, ptr %tmp, align 16 # | store <2 x double> %6, ptr %__ret_379, align 16 # | %7 = load <2 x double>, ptr %__ret_379, align 16 # | store <2 x double> %7, ptr %tmp1, align 16 # | %8 = load <2 x double>, ptr %tmp1, align 16 # | ret <2 x double> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %6 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %6, ptr %__ret, align 8 # | %7 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %7, ptr %tmp, align 8 # | %8 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3 # | %6 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4 # | %7 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5 # | %8 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6 # | %9 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %10 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %10, ptr %__ret, align 16 # | %11 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %11, ptr %tmp, align 16 # | %12 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %12 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e33af67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e33af64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e33af6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc05e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc05ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc05e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc05e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e33aefdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e33aefda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e33aee28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e33ab91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e33ab91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc05e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc05e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc05e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e33ab91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (1541 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # | #0 0x0000564410a26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564410a23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564410a2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2bcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2bcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2bcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2bcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644109bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644109bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644109a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564410650e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564410650b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2bcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2bcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2bcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564410650a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (1542 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/41659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcf564ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcf5649e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcf564d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa5ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa5ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa5ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa5ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcf55e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcf55e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcf55c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcf5276e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcf5276b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa5ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa5ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa5ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcf5276a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (1543 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055875d836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055875d833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055875d83762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5949d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5949d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5949d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5949d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055875d7ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055875d7cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055875d7b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055875d460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055875d460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5949d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5949d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5949d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055875d460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (1544 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <16 x i8> %2, %3 # | store <16 x i8> %sub.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <8 x i16> %2, %3 # | store <8 x i16> %sub.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <4 x i32> %2, %3 # | store <4 x i32> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | store <1 x i64> %v2, ptr %v2.addr, align 8 # | %0 = load <1 x i64>, ptr %v1.addr, align 8 # | %1 = load <1 x i64>, ptr %v2.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <1 x i64> %2, %3 # | store <1 x i64> %sub.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v1.addr = alloca <2 x i64>, align 16 # | %v2.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %v1, ptr %v1.addr, align 16 # | store <2 x i64> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x i64>, ptr %v1.addr, align 16 # | %1 = load <2 x i64>, ptr %v2.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <2 x i64> %2, %3 # | store <2 x i64> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | # | ... # `---data was truncated (10240/170019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055bca3294eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bca3291e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bca329562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f415ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f415ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f415ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f415feed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bca322abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bca322aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bca320f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bca2ebee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bca2ebeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f415feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f415feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f415feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bca2ebea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (1545 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056304d520eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056304d51de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056304d52162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5a8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5a8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5a8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5a8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056304d4b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056304d4b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056304d49b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056304d14ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056304d14ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5a8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5a8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5a8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056304d14aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (1546 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (1547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (1548 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab77f25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab77f22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab77f2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb08249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb082a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb08249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb08231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab77ebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab77ebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab77ea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab77b4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab77b4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb08232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb082330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb082330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab77b4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (1549 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642fef89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642fef86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642fef8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa053249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa053249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa053231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642fef1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642fef1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642fef048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642febb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642febb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa053232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0532330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642febb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (1550 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da3757aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da37577e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da3757b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cba049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cba0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cba049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cba031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da37510bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da37510a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da374f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da371a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da371a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3cba032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cba0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cba0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da371a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1551 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (1552 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc90400eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc903fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc9040162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc56b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc56b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc56b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc56b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc90396bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc90396a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc9037b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc9002ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc9002ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc56b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc56b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc56b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc9002aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (1553 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c377ba6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c377ba3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c377ba762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d12105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d1215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d12105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d120ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c377b3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c377b3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c377b218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3777d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3777d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d120eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d120ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d120ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3777d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (1554 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603b618aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603b6187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603b618b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f489d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f489d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f489d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f489d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603b6120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603b6120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603b61058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603b5db4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603b5db4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f489d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f489d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f489d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603b5db4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (1555 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560866478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560866475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056086647962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb207f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb207f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb207f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb207f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056086640ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056086640ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608663f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608660a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608660a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb207f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb207f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb207f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608660a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (1556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, # | ... # `---data was truncated (10240/30874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629435d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629435d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629435d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ae1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ae12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ae1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ae1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056294356bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056294356ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629435508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629431ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629431ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ae1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ae12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ae12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629431ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (1557 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.addr = al # | ... # `---data was truncated (10240/41670) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad49c2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad49c2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad49c2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f3b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f3b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f3b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f3b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad49bc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad49bc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad49ba98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad49858e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad49858b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f3b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f3b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f3b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad49858a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (1558 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store # | ... # `---data was truncated (10240/79497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c49a12aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c49a127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c49a12b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8265b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8265b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8265b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8265b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c49a0c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c49a0c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c49a0a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c499d54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c499d54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8265b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8265b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8265b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c499d54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (1559 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (1560 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vsqaddb_u8() #0 { # | entry: # | %__p0.addr.i = alloca i8, align 1 # | %__p1.addr.i = alloca i8, align 1 # | %__ret.i = alloca i8, align 1 # | %ref.tmp.i = alloca i8, align 1 # | store i8 1, ptr %__p0.addr.i, align 1 # | store i8 -1, ptr %__p1.addr.i, align 1 # | %0 = load i8, ptr %__p0.addr.i, align 1 # | %1 = load i8, ptr %__p1.addr.i, align 1 # | %2 = insertelement <8 x i8> poison, i8 %0, i64 0 # | %3 = insertelement <8 x i8> poison, i8 %1, i64 0 # | %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3) # | %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0 # | store i8 %4, ptr %ref.tmp.i, align 1 # | %5 = load i8, ptr %ref.tmp.i, align 1 # | store i8 %5, ptr %__ret.i, align 1 # | %6 = load i8, ptr %__ret.i, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vsqaddh_u16() #0 { # | entry: # | %__p0.addr.i = alloca i16, align 2 # | %__p1.addr.i = alloca i16, align 2 # | %__ret.i = alloca i16, align 2 # | %ref.tmp.i = alloca i16, align 2 # | store i16 1, ptr %__p0.addr.i, align 2 # | store i16 -1, ptr %__p1.addr.i, align 2 # | %0 = load i16, ptr %__p0.addr.i, align 2 # | %1 = load i16, ptr %__p1.addr.i, align 2 # | %2 = insertelement <4 x i16> poison, i16 %0, i64 0 # | %3 = insertelement <4 x i16> poison, i16 %1, i64 0 # | %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3) # | %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0 # | store i16 %4, ptr %ref.tmp.i, align 2 # | %5 = load i16, ptr %ref.tmp.i, align 2 # | store i16 %5, ptr %__ret.i, align 2 # | %6 = load i16, ptr %__ret.i, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vsqadds_u32() #0 { # | entry: # | %__p0.addr.i = alloca i32, align 4 # | %__p1.addr.i = alloca i32, align 4 # | %__ret.i = alloca i32, align 4 # | %ref.tmp.i = alloca i32, align 4 # | store i32 1, ptr %__p0.addr.i, align 4 # | store i32 -1, ptr %__p1.addr.i, align 4 # | %0 = load i32, ptr %__p0.addr.i, align 4 # | %1 = load i32, ptr %__p1.addr.i, align 4 # | %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1) # | store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4 # | %2 = load i32, ptr %ref.tmp.i, align 4 # | store i32 %2, ptr %__ret.i, align 4 # | %3 = load i32, ptr %__ret.i, align 4 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vsqaddd_u64() #0 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i64, align 8 # | %ref.tmp.i = alloca i64, align 8 # | store i64 1, ptr %__p0.addr.i, align 8 # | store i64 -1, ptr %__p1.addr.i, align 8 # | %0 = load i64, ptr %__p0.addr.i, align 8 # | %1 = load i64, ptr %__p1.addr.i, align 8 # | %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1) # | store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8 # | %2 = load i64, ptr %ref.tmp.i, align 8 # | store i64 %2, ptr %__ret.i, align 8 # | %3 = load i64, ptr %__ret.i, align 8 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # | #0 0x00005557df989eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557df986e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557df98a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f340fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f340faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f340fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f340fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557df91fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557df91fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557df9048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557df5b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557df5b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f340fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f340fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f340fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557df5b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (1561 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558761c9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558761c9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558761c9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82d9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82d9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82d9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82d9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558761c34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558761c34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558761c198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587618c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587618c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82d9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82d9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82d9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587618c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (1562 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564686614eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564686611e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056468661562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecf2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecf238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecf2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecf231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646865aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646865aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056468658f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056468623ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056468623eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecf231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecf231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecf231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056468623ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (1563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563446bbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563446bbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563446bbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ba3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ba38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ba3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ba3831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563446b54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563446b54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563446b398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634467e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634467e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ba3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ba38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ba38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634467e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (1564 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0a7ceceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0a7ce9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0a7ced62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b0c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b0c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b0c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b0c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0a7c82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0a7c82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0a7c678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0a7916e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0a7916b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b0c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b0c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b0c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0a7916a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (1565 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (1566 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8da170eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8da16de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8da17162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3996c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3996c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3996c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3996c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8da106bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8da106a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8da0eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8d9d9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8d9d9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3996c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3996c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3996c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8d9d9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (1567 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9347efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9347ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9347f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f616c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f616c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f616c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f616c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a934785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a934785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a93476a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a934419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a934419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f616c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f616c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f616c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a934419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (1568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e3702aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e37027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e3702b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd620e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd620ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd620e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd620e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e36fc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e36fc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e36fa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e36c54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e36c54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd620e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd620e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd620e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e36c54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (1569 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/68255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ba962beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ba9628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ba962c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5206a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5206aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5206a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5206a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ba95c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ba95c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ba95a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ba9255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ba9255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5206a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5206a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5206a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ba9255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (1570 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x half> # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x float> # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 { # | entry: # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 { # | entry: # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x00005602a9495eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602a9492e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602a949662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b60133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b6018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b60133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b6011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602a942bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602a942ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602a94108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602a90bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602a90bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b6011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b6011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b6011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602a90bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (1571 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (1572 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d423f7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d423f78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d423f7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d47d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d47d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d47d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d47d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d423f11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d423f11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d423ef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d423ba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d423ba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d47d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d47d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d47d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d423ba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (1573 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (1574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = # | ... # `---data was truncated (10240/26564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d3341aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d33417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d3341b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0620c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0620ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0620c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0620c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d333b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d333b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d333958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d33044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d33044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0620c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0620c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0620c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d33044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (1575 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (1576 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1577 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, pt # | ... # `---data was truncated (10240/73955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572beb02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572beaffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572beb0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ebfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ebfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ebfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ebfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572bea98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572bea98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572bea7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572be72ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572be72cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ebfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ebfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ebfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572be72ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (1578 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (1579 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a71282feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a71282ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a71283062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddc0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddc08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddc0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddc0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7127c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7127c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7127aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a712459e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a712459b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddc0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddc08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddc08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a712459a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (1580 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fad1089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fad1086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fad108a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43c881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43c88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43c881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43c8803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fad101fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fad101fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fad10048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fad0cb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fad0cb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43c8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43c88050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43c88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fad0cb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1581 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ffd4e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ffd4dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ffd4e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3ecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3ecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3ecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3ecd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ffd477bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ffd477a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ffd45c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ffd10be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ffd10bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3ecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3ecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3ecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ffd10ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (1582 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bdb9feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bdb9fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bdb9ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e02849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e02849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e02831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bdb994bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bdb994a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bdb9798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bdb628e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bdb628b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e02832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e028330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bdb628a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (1583 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/100960) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f659732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f65972fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f65973362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff390249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3902a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff390249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff390231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6596c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6596c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6596ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f65935ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f65935cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff390232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3902330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3902330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65935ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (1584 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (1585 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2fc438eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2fc435e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2fc43962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b48e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b48e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b48e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b48e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2fc3cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2fc3cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2fc3b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2fc062e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2fc062b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b48e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b48e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b48e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2fc062a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (1586 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.a # | ... # `---data was truncated (10240/33190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f84790eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f8478de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f8479162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d5b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d5b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d5b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d5b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f84726bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f84726a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f8470b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f843bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f843bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d5b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d5b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d5b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f843baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (1587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c358fb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c358faee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c358fb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0642049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0642049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0642031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c358f47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c358f47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c358f2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c358bdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c358bdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0642032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06420330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c358bdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (1588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563054b87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563054b84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563054b8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ca6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ca678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ca6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ca671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563054b1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563054b1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563054b028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630547b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630547b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ca671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ca671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ca671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630547b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (1589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (1590 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (1591 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff. # | ... # `---data was truncated (10240/78156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b85028ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b850289e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b85028d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff51b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff51b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff51b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff51b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b850222bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b850222a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8502078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b84feb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b84feb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff51b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff51b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff51b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b84feb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (1592 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (1593 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a34af87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a34af84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a34af8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8057849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8057849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8057831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a34af1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a34af1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a34af028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a34abb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a34abb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8057832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a34abb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (1594 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (1595 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cfedcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cfedc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cfedcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb49c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb49c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb49c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb49c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cfed60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560cfed60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560cfed458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560cfe9f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560cfe9f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb49c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb49c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb49c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cfe9f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (1596 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649027e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649027dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649027e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43e4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43e40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43e4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43e4031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564902777bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564902777a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056490275c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056490240be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056490240bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43e4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43e40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43e40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056490240ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (1597 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (1598 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrffr( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | call void @llvm.aarch64.sve.wrffr( %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.wrffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563e71041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e7103ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e7104262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91dba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91dbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91dba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91dba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e70fd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e70fd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e70fbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e70c6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e70c6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91dba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91dba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91dba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e70c6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (1599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (1600 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c780179eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c780176e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c78017a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33fef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33fef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33fef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33feeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c78010fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c78010fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7800f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c77fda3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c77fda3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33feeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33feeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33feeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c77fda3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1601 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566452dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566452d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566452dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0780a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0780a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0780a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0780a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556645272bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556645272a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566452578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556644f06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556644f06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0780a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0780a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0780a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556644f06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (1602 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (1603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofre # | ... # `---data was truncated (10240/183431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559be8b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559be8b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559be8b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f457e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f457e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f457e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f457e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559be8ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559be8ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559be8a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559be8749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559be8749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f457e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f457e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f457e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559be8749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (1604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cf3826eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cf3823e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cf382762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f143af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f143af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f143af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f143af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cf37bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cf37bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cf37a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cf3450e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cf3450b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f143af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f143af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f143af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cf3450a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (1605 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (1606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5e4038eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5e4035e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5e403962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc458505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc45855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc458505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4584ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5e3fcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a5e3fcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5e3fb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5e3c62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5e3c62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4584eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4584ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4584ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5e3c62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (1607 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559c0726aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c07267e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c0726b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb34cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb34cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb34cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb34cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c07200bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c07200a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c071e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c06e94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c06e94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb34cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb34cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb34cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c06e94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (1608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056076c65feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056076c65ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056076c66062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e43249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e432a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e43249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e43231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056076c5f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056076c5f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056076c5da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056076c289e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056076c289b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e43232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e432330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e432330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056076c289a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (1609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559571c0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559571c07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559571c0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e4eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e4eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e4eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e4eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559571ba0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559571ba0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559571b858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559571834e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559571834b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e4eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e4eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e4eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559571834a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (1610 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2d9f3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2d9f3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2d9f3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4150b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4150b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4150b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4150b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2d9ed3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2d9ed3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2d9eb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2d9b67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2d9b67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4150b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4150b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4150b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2d9b67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (1611 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fb8148eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fb8145e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fb814962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f893cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f893cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f893cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f893cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fb80debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fb80dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fb80c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fb7d72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fb7d72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f893cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f893cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f893cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fb7d72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (1612 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c48b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c48b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c48b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba73533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba7358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba73533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba7351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c48aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c48aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c48a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c48739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c48739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba7351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba7351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba7351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c48739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (1613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9cb7eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9cb7e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9cb7eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce26533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce2658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce26533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce2651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9cb780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9cb780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9cb7658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9cb414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9cb414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce2651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce2651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce2651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9cb414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (1614 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1f74f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1f74f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1f74f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53c0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53c02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53c0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53c0231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1f748bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1f748ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1f74708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1f711fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1f711fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53c0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53c02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53c02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1f711fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (1615 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # | #0 0x000055afc5c14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afc5c11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afc5c1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50f7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50f74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50f7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50f7431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afc5baabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afc5baaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afc5b8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afc583ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afc583eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50f7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50f74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50f74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afc583ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aac44deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559aac44ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559aac44e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7bf81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7bf8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7bf81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7bf803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aac3e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559aac3e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559aac3c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559aac077e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559aac077b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7bf804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7bf8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7bf8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559aac077a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (1617 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (1618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615e209ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615e2099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615e209d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0be6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0be638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0be6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0be631b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615e2032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615e2032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615e20178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615e1cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615e1cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0be631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0be631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0be631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615e1cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (1619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %v # | ... # `---data was truncated (10240/142327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f89972eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f8996fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f8997362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb5301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb530725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb5301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb53003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f89908bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f89908a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f898ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f8959ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f8959cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb53004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb530050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb530050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f8959ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (1620 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f8d06beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f8d068e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f8d06c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0327333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f032738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0327333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f032731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f8d001bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f8d001a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f8cfe68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f8cc95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f8cc95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f032731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f032731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f032731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f8cc95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (1621 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605874f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605874efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605874f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1c6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1c6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1c6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1c6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560587488bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560587488a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056058746d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056058711ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056058711cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1c6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1c6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1c6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056058711ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (1622 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba6036aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba60367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba6036b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9be133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9be18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9be133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9be11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba60300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba60300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba602e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba5ff94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba5ff94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9be11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9be11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9be11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba5ff94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (1623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/80648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fe7cedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fe7ceae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fe7cee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab13d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab13d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab13d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab13d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fe7c83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fe7c83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fe7c688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fe7917e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fe7917b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab13d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab13d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab13d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fe7917a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (1624 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562173ff7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562173ff4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562173ff862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe594249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5942a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe594249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe594231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562173f8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562173f8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562173f728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562173c21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562173c21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe594232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5942330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5942330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562173c21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (1625 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c690cbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c690cbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c690cbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d97849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d97849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d97831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c690c53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c690c53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c690c388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6908e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6908e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d97832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d978330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6908e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (1626 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559357a7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559357a78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559357a7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f246eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f246eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f246eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f246eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559357a11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559357a11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593579f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593576a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593576a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f246eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f246eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f246eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593576a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (1627 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644b8d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644b8d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644b8d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe638a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe638aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe638a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe638a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644b8cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644b8cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644b8cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644b8969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644b8969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe638a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe638a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe638a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644b8969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (1628 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/29136) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f4f10ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f4f109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f4f10d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1090649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1090649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1090631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f4f0a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f4f0a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f4f0878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f4ed36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f4ed36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1090632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10906330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f4ed36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (1629 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %v # | ... # `---data was truncated (10240/23064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055faced11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faced0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faced1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2e8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2e80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2e8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2e8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faceca7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faceca7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055facec8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055face93be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055face93bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2e8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2e80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2e80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055face93ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (1630 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569bc130eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569bc12de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569bc13162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f957b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f957b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f957b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f957b031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569bc0c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569bc0c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569bc0ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569bbd5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569bbd5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f957b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f957b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f957b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569bbd5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (1631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612ef4dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612ef4d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612ef4dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29e5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612ef472bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612ef472a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612ef4578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612ef106e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612ef106b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612ef106a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (1632 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efaeb2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055efaeb28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055efaeb2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9104e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9104ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9104e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9104e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efaeac1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055efaeac1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055efaeaa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055efae755e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055efae755b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9104e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9104e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9104e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efae755a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (1633 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056193c3fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056193c3f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056193c3fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2734d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2734d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2734d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2734d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056193c392bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056193c392a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056193c3778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056193c026e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056193c026b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2734d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2734d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2734d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056193c026a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (1634 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/68133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0fe88feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0fe88ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0fe89062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadc341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadc34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadc341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadc3403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0fe825bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0fe825a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0fe80a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0fe4b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0fe4b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadc3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadc34050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadc34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0fe4b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (1635 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ddf890eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ddf88de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ddf89162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4780649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4780649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4780631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ddf826bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ddf826a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ddf80b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ddf4bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ddf4bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4780632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47806330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ddf4baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (1636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (1637 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fffcc18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fffcc15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fffcc1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f890ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f890ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f890ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f890ce03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fffcbaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fffcbaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fffcb938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fffc842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fffc842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f890ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f890ce050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f890ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fffc842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (1638 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (1639 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d4cbadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d4cbaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d4cbae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa8581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa858725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa8581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa85803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d4cb43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d4cb43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d4cb288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d4c7d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d4c7d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa85804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa858050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa858050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d4c7d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (1640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056543d989eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056543d986e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056543d98a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f024b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f024b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f024b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f024b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056543d91fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056543d91fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056543d9048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056543d5b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056543d5b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f024b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f024b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f024b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056543d5b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (1641 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (1642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055daddf9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055daddf98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055daddf9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe55d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe55d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe55d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe55d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055daddf31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055daddf31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055daddf168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055daddbc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055daddbc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe55d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe55d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe55d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055daddbc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (1643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556c59eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556c59ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556c59ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea29533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea2958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea29533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea2951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556c5984bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556c5984a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556c59698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556c5618e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556c5618b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea2951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea2951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea2951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556c5618a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (1644 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627f5f48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627f5f45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627f5f4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb707e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb707ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb707e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb707e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627f5edebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627f5edea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627f5ec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627f5b72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627f5b72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb707e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb707e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb707e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627f5b72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (1645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f164884eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f164881e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f16488562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa861933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa86198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa861933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa86191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f16481abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f16481aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1647ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1644aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1644aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa86191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa86191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa86191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1644aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (1646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056358633feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056358633ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056358634062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7b5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7b56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7b5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7b5631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635862d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635862d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635862ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563585f69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563585f69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc7b5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7b56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7b56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563585f69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (1647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/148020) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056175c40feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056175c40ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056175c41062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5204a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5204a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5204a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5204a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056175c3a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056175c3a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056175c38a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056175c039e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056175c039b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5204a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5204a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5204a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056175c039a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1648 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624e7b13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624e7b10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624e7b1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb926449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb926449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb926431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624e7aa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624e7aa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624e7a8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624e773de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624e773db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb926432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624e773da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (1649 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsa # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564374f9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564374f98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564374f9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ae741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ae74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ae741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ae7403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564374f31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564374f31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564374f168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564374bc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564374bc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ae7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ae74050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ae74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564374bc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (1650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561770514eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561770511e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056177051562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52afe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52afea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52afe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52afe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617704aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617704aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056177048f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056177013ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056177013eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52afe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52afe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52afe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056177013ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (1651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (1652 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558348caceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558348ca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558348cad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f370c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f370c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f370c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f370c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558348c42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558348c42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558348c278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583488d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583488d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f370c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f370c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f370c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583488d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (1653 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056346062feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056346062ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056346063062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f562ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f562eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f562ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f562ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634605c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634605c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634605aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563460259e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563460259b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f562ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f562ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f562ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563460259a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (1654 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/150649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557533cc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557533cbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557533cc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2eca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2eca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2eca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2eca03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557533c56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557533c56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557533c3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575338eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575338eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2eca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2eca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2eca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575338eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (1655 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601acc3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601acc3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601acc3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd91b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd91b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd91b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd91b231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601acbd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601acbd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601acbb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601ac867e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601ac867b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd91b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd91b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd91b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601ac867a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (1656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (1657 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dab51ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560dab519e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560dab51d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f964f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f964f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f964f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f964f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dab4b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560dab4b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560dab4978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560dab146e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560dab146b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f964f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f964f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f964f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dab146a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (1658 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a49609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a49606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4960a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc140e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc140e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc140e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc140e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4959fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4959fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a495848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a49233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a49233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc140e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc140e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc140e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a49233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (1659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641ba808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641ba805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641ba80962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fbc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fbc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fbc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fbc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641ba79ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641ba79ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641ba7838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641ba432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641ba432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fbc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fbc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fbc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641ba432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (1660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559897685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559897682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055989768662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e7ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e7cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e7ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e7ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055989761bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055989761ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598976008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598972afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598972afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e7ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e7ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e7ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598972afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (1661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, # | ... # `---data was truncated (10240/211231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9ad596eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9ad593e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9ad59762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8485533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f848558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8485533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f848551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9ad52cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9ad52ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9ad5118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9ad1c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9ad1c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f848551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f848551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f848551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9ad1c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (1662 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (1663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcf31edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fcf31eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fcf31ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0117249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0117249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0117231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcf3183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fcf3183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fcf31688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fcf2e17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fcf2e17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0117232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01172330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcf2e17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (1664 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557074d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557074d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557074d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5da0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5da00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5da0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5da0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557074cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557074cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557074cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557074969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557074969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5da0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5da00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5da00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557074969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (1665 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (1666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (1667 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (1668 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f173626eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f173623e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f17362762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a9db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a9db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a9db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a9db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1735bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1735bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1735a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f173250e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f173250b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a9db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a9db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a9db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f173250a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (1669 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = loa # | ... # `---data was truncated (10240/18917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f8a97beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f8a978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f8a97c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f38b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f38b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f38b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f38b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f8a911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f8a911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f8a8f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f8a5a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f8a5a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f38b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f38b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f38b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f8a5a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1670 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %vext, ptr %ref.tmp, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %4, ptr %__ret, align 8 # | %5 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %5, ptr %tmp, align 8 # | %6 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | %5 = bitcast <8 x i8> %3 to <4 x i16> # | %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> # | store <4 x i16> %vext, ptr %ref.tmp, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %6, ptr %__ret, align 8 # | %7 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %7, ptr %tmp, align 8 # | %8 = load <4 x i16>, ptr %tmp, align 8 # | ret <4 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %__s1 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <2 x i32> # | %5 = bitcast <8 x i8> %3 to <2 x i32> # | %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> # | store <2 x i32> %vext, ptr %ref.tmp, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %6, ptr %__ret, align 8 # | %7 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %7, ptr %tmp, align 8 # | %8 = load <2 x i32>, ptr %tmp, align 8 # | ret <2 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer # | store <1 x i64> %vext, ptr %ref.tmp, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %6, ptr %__ret, align 8 # | %7 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %7, ptr %tmp, align 8 # | %8 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca <16 x i8>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %vext, ptr %ref.tmp, align 16 # | %4 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %4, ptr %__ret, align 16 # | %5 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %5, ptr %tmp, align 16 # | %6 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x i16> # | %5 = bitcast <16 x i8> %3 to <8 x i16> # | %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> # | store <8 x i16> %vext, ptr %ref.tmp, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %6, ptr %__ret, align 16 # | %7 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %7, ptr %tmp, align 16 # | %8 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <4 x i32> # | %5 = bitcast <16 x i8> %3 to <4 x i32> # | %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> # | store <4 x i32> %vext, ptr %ref.tmp, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %6, ptr %__ret, align 16 # | %7 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %7, ptr %tmp, align 16 # | %8 = load <4 x i32>, ptr %tmp, align 16 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> # | store <2 x i64> %vext, ptr %ref.tmp, align 16 # | %6 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %6, ptr %__ret, align 16 # | %7 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %7, ptr %tmp, align 16 # | %8 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> # | ... # `---data was truncated (10240/29598) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005651fa9a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005651fa9a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005651fa9a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7a1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7a12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7a1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7a1231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651fa93cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651fa93ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651fa9218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651fa5d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651fa5d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7a1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7a12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7a12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651fa5d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (1671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (1672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (1673 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561881483eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561881480e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056188148462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedc7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedc7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedc7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedc7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561881419bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561881419a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618813fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618810ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618810adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fedc7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedc7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedc7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618810ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (1674 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (1675 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642a4ecfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642a4ecce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642a4ed062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f543d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f543d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f543d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f543d403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642a4e65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642a4e65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642a4e4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642a4af9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642a4af9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f543d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f543d4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f543d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642a4af9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (1676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056344c2c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056344c2c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056344c2c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d48c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d48ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d48c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d48c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056344c259bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056344c259a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056344c23e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056344beede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056344beedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d48c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d48c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d48c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056344beeda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558958299eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558958296e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055895829a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf02133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf0218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf02133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf0211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055895822fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055895822fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589582148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558957ec3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558957ec3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf0211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf0211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf0211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558957ec3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (1678 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ea6f0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ea6f0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ea6f0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1562a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1562aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1562a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1562a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ea6ea3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ea6ea3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ea6e888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ea6b37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ea6b37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1562a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1562a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1562a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ea6b37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (1679 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/78164) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055846e640eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055846e63de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055846e64162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc35a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc35a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc35a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc35a403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055846e5d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055846e5d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055846e5bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055846e26ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055846e26ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc35a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc35a4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc35a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055846e26aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (1680 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd12c3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd12c39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd12c3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97fb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97fb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97fb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97fb231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd12bd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd12bd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd12bb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd12866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd12866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97fb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97fb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97fb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd12866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (1681 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (1682 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (1683 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618dc30ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618dc309e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618dc30d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1001a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1001aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1001a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1001a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618dc2a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618dc2a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618dc2878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618dbf36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618dbf36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1001a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1001a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1001a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618dbf36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (1685 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b04406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b04403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b0440762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff35449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff35449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff35431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b0439cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b0439ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b043818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b04030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b04030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff35432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff354330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b04030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (1686 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d5ecd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d5ecd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d5ecd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2eac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2eaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2eac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2eac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d5ec6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d5ec6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d5ec538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d5e902e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d5e902b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2eac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2eac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2eac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d5e902a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (1687 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f9a390eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f9a38de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f9a39162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5988d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5988d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5988d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5988ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f9a326bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f9a326a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f9a30b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f99fbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f99fbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5988ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5988cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5988cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f99fbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (1688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (1689 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7f063eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7f063be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7f063f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d24049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d240a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d24049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d24031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7f05d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7f05d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7f05b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7f0268e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7f0268b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d24032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d240330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d240330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7f0268a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (1690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055668e1c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055668e1c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055668e1c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbef71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055668e15bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055668e15ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055668e1408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055668ddefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055668ddefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbef71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055668ddefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (1691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (1692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557217a2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557217a2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557217a2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5737d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5737d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5737d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5737d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572179c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572179c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572179a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557217657e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557217657b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5737d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5737d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5737d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557217657a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (1693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfs # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639e8e65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639e8e62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639e8e6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f180a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f180a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f180a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f180a431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639e8dfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639e8dfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639e8de08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639e8a8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639e8a8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f180a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f180a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f180a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639e8a8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (1694 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd22e41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd22e3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd22e4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe07c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe07c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe07c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe07c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd22dd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd22dd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd22dbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd22a6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd22a6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe07c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe07c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe07c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd22a6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (1695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (1696 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b824a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b824a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b824a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98d7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98d7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98d7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98d7aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b82439bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b82439a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b8241e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b820cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b820cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98d7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98d7aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98d7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b820cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (1697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055814ea9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055814ea9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055814ea9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb1b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb1b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb1b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb1b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055814ea33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055814ea33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055814ea188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055814e6c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055814e6c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb1b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb1b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb1b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055814e6c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (1698 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (1699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572a4f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572a4f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572a4f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e0fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e0faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e0fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e0fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572a4ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572a4ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572a4ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572a4b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572a4b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e0fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e0fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e0fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572a4b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (1700 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl.i = bitcast <8 x i8> %3 to <4 x i16> # | %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16> # | %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16> # | %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <4 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <4 x i16> %6, %vbsl2.i # | %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <4 x i16> %vbsl5.i to <4 x half> # | store <4 x half> %7, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbsl.i = bitcast <16 x i8> %3 to <8 x i16> # | %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16> # | %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16> # | %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <8 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <8 x i16> %6, %vbsl2.i # | %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <8 x i16> %vbsl5.i to <8 x half> # | store <8 x half> %7, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef # | ... # `---data was truncated (10240/31986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005596668b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596668b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596668b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f06049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f060a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f06049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f06031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055966684abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055966684aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055966682f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596664dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596664deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f06032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f060330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f060330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596664dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (1701 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @orc_b_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @ctz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cpop_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctpop.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.orc.b.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctpop.i32(i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c820f5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c820f5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c820f5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08fb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08fb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08fb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08fb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c820ef4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c820ef4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c820ed98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c820b88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c820b88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08fb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08fb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08fb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c820b88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (1702 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572da886eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572da883e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572da88762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff921d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff921d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff921d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff921d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572da81cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572da81ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572da8018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572da4b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572da4b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff921d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff921d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff921d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572da4b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (1703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (1704 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff89660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff8965de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff8966162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cbd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cbd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cbd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cbd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff895f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff895f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff895db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff8928ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff8928ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cbd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cbd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cbd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff8928aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (1705 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2c521ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2c5219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2c521d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a74533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a7458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a74533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a7451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2c51b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2c51b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2c51978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2c4e46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2c4e46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a7451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a7451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a7451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2c4e46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (1706 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c45739eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c45736e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c4573a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ef3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ef3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ef3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ef3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c456cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c456cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c456b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c45363e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c45363b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ef3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ef3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ef3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c45363a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (1707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618d850eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618d850be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618d850f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdecd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdecd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdecd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdecd031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618d84a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618d84a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618d84898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618d8138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618d8138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdecd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdecd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdecd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618d8138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (1708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556145aadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556145aaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556145aae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf09e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf09ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf09e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf09e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556145a43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556145a43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556145a288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561456d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561456d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf09e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf09e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf09e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561456d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (1709 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561afb237eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561afb234e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561afb23862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3360849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33608a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3360849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3360831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561afb1cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561afb1cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561afb1b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561afae61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561afae61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3360832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33608330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33608330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561afae61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (1710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9565abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9565a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9565ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87eae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87eaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87eae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87eae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a956541bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a956541a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9565268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9561d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9561d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87eae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87eae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87eae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9561d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (1711 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/12644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603dac13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603dac10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603dac1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf90d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf90d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf90d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf90d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603daba9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603daba9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603dab8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603da83de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603da83db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf90d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf90d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf90d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603da83da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (1712 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_ # | ... # `---data was truncated (10240/35087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591e5a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591e5a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591e5a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f650a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f650a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f650a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f650a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591e5a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591e5a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591e5a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591e56b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591e56b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f650a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f650a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f650a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591e56b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (1713 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592b3790eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592b378de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592b379162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba53333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba5338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba53333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba5331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592b3726bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592b3726a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592b370b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592b33bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592b33bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba5331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba5331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba5331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592b33baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1714 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | # | ... # `---data was truncated (10240/223129) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc184b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc184b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc184ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff04f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff04f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff04f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff04f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc1844fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc1844fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc184348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc180e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc180e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff04f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff04f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff04f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc180e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (1715 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (1716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | ... # `---data was truncated (10240/12958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056427a3f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056427a3f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056427a3f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28c691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056427a38bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056427a38ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056427a3708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056427a01fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056427a01fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28c691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056427a01fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (1717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3973eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3973ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3973ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d22249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d222a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d22249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d22231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e397384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e397384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3973698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e397018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e397018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d22232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d222330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d222330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e397018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (1718 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a95491eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a9548ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a9549262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96c2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96c278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96c2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96c271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a95427bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a95427a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a9540c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a950bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a950bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96c271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96c271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96c271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a950bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (1719 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca # | ... # `---data was truncated (10240/43515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b6eda5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b6eda2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b6eda662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d37105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d3715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d37105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d370ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b6ed3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b6ed3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b6ed208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b6e9cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b6e9cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d370eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d370ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d370ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b6e9cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (1720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561446c6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561446c68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561446c6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f658e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f658e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f658e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f658e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561446c01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561446c01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561446be68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561446895e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561446895b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f658e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f658e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f658e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561446895a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (1721 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c2af57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c2af54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c2af5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5663733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f566378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5663733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f566371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c2aeedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c2aeeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c2aed28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c2ab81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c2ab81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f566371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f566371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f566371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c2ab81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (1722 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0) # | r # | ... # `---data was truncated (10240/43005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561159e9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561159e9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561159e9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6860449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68604a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6860449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6860431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561159e33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561159e33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561159e188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561159ac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561159ac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6860432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68604330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68604330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561159ac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (1723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa9af89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa9af86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa9af8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d12831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa9af1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa9af1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa9af048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa9abb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa9abb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d128330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa9abb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (1724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a962be5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a962be2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a962be662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90d2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90d2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90d2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90d2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a962b7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a962b7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a962b608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a96280fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a96280fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90d2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90d2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90d2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a96280fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (1725 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/176535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b134cbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b134cb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b134cbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fbd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fbd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fbd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fbd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b134c52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b134c52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b134c378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1348e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1348e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fbd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fbd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fbd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1348e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (1726 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (1727 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055641a0cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055641a0cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055641a0ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fb1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fb1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fb1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fb1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055641a063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055641a063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055641a0488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556419cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556419cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fb1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fb1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fb1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556419cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (1728 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (1729 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractva # | ... # `---data was truncated (10240/22708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056262d84deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056262d84ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056262d84e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c26f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c26f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c26f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c26f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262d7e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056262d7e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056262d7c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056262d477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056262d477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c26f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c26f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c26f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262d477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (1730 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (1731 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (1732 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca # | ... # `---data was truncated (10240/97514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626ff4fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626ff4f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626ff4fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fbf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fbf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fbf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fbf431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626ff491bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626ff491a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626ff4768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626ff125e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626ff125b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fbf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fbf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fbf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626ff125a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (1733 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562218e1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562218e1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562218e2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc125649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1256a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc125649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc125631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562218db5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562218db5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562218d9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562218a49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562218a49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc125632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1256330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1256330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562218a49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (1734 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564669686eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564669683e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056466968762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb64333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb6438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb64333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb6431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056466961cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056466961ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646696018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646692b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646692b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb6431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb6431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb6431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646692b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (1735 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nx # | ... # `---data was truncated (10240/25567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650c4c97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005650c4c94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005650c4c9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5fcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5fcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5fcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5fcb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650c4c2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005650c4c2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650c4c128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005650c48c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005650c48c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5fcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5fcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5fcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650c48c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (1736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ff428aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ff4287e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ff428b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02e3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02e34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02e3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02e3431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ff4220bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ff4220a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ff42058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ff3eb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ff3eb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02e3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02e34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02e34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ff3eb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (1737 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (1738 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569ddd36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569ddd33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569ddd3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfa6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfa6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfa6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfa6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569ddcccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569ddccca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569ddcb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569dd960e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569dd960b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfa6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfa6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfa6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569dd960a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (1739 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | # | ... # `---data was truncated (10240/19083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055731809beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557318098e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055731809c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09daa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09daa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09daa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09daa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557318031bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557318031a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573180168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557317cc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557317cc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09daa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09daa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09daa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557317cc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (1740 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559feeb3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559feeb3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559feeb3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ea5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ea538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ea5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ea531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559feead4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559feead4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559feeab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fee768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fee768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ea531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ea531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ea531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fee768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (1741 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559eaaffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559eaafce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559eab0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5343b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5343b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5343b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5343b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559eaa95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559eaa95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559eaa7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559ea729e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559ea729b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5343b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5343b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5343b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559ea729a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (1742 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d44053ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d440539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d44053d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12e4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12e438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12e4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12e431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4404d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4404d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4404b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d440166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d440166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f12e431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12e431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12e431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d440166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (1743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056273451feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056273451ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056273452062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1622849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1622849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1622831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627344b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627344b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056273449a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562734149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562734149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1622832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16228330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562734149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (1744 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f6c961eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f6c95ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f6c96262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f777221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77722725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f777221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7772203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f6c8f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f6c8f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f6c8dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f6c58be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f6c58bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7772204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77722050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77722050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f6c58ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (1745 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b03d753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b03d750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b03d75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47dfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b03d6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b03d6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b03d6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b03d37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b03d37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b03d37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1746 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align # | ... # `---data was truncated (10240/26572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0fc34eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0fc34be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0fc34f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe790e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe790e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe790e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe790e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0fc2e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0fc2e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0fc2c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0fbf78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0fbf78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe790e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe790e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe790e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0fbf78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (1747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (1748 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fe6fcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fe6fcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fe6fd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19c9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19c9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19c9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19c9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fe6f65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fe6f65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fe6f4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fe6bf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fe6bf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19c9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19c9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19c9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fe6bf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (1749 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608a3f16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608a3f13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608a3f1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3df9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3df998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3df9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3df991b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608a3eacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608a3eaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608a3e918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608a3b40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608a3b40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3df991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3df991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3df991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608a3b40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (1750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d06c574eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d06c571e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d06c57562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0ed533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0ed58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0ed533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0ed51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d06c50abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d06c50aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d06c4ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d06c19ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d06c19eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0ed51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0ed51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0ed51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d06c19ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (1751 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 im # | ... # `---data was truncated (10240/78242) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbc1d6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbc1d6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbc1d6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb833333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb83338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb833333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb83331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbc1d04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbc1d04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbc1ce98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbc1998e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbc1998b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb83331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb83331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb83331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbc1998a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (1752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d82f1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d82f17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d82f1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7e9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d82eb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d82eb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d82e958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d82b44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d82b44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d82b44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (1753 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, a # | ... # `---data was truncated (10240/29450) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556312ce1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556312cdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556312ce262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed6c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed6c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed6c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed6c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556312c77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556312c77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556312c5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055631290be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055631290bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed6c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed6c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed6c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055631290ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (1754 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c876a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c876a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c876a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c6c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c6c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c6c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c6c403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c8763dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c8763da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c876228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c872d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c872d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c6c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c6c4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c6c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c872d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1755 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624dacf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624daceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624dacf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6910533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f691058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6910533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f691051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624dac87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624dac87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624dac6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624da91be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624da91bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f691051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f691051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f691051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624da91ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (1756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dbfbc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558dbfbc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558dbfbc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4212449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42124a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4212449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4212431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dbfb5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558dbfb5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558dbfb438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558dbf7f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558dbf7f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4212432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42124330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42124330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dbf7f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (1757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (1758 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e7dc46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e7dc43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e7dc4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e7dbdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e7dbdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e7dbc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e7d870e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e7d870b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15f4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e7d870a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (1759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cab7d81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cab7d7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cab7d8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0fdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cab7d17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cab7d17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cab7cfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cab79abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cab79abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cab79aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (1760 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/76635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563464382eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056346437fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056346438362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff820d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff820d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff820d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff820d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563464318bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563464318a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634642fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563463face46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563463facb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff820d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff820d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff820d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563463faca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (1761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586e307feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586e307ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586e308062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b35d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b35d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b35d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b35d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586e3015bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586e3015a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586e2ffa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586e2ca9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586e2ca9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b35d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b35d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b35d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586e2ca9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (1762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d7e028eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d7e025e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d7e02962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc9df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc9df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc9df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc9df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d7dfbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d7dfbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d7dfa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d7dc52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d7dc52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc9df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc9df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc9df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d7dc52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (1763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb4ef41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb4ef3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb4ef4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d31733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d3178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d31733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d3171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb4eed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb4eed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb4eebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb4eb6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb4eb6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d3171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d3171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d3171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb4eb6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1764 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (1765 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b56fab7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b56fab4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b56fab862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb66705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb6675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb66705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb666ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b56fa4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b56fa4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b56fa328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b56f6e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b56f6e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb666eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb666ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb666ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b56f6e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (1766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056246361ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562463619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056246361d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd855249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8552a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd855249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd855231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624635b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624635b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624635978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562463246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562463246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd855232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8552330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8552330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562463246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (1767 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <8 x i8>, ptr %__promote, align 8 # | store <8 x i8> %1, ptr %__ret, align 8 # | %2 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %2, ptr %tmp, align 8 # | %3 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <8 x i8>, align 8 # | %.compoundliteral.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> # | %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> # | %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> # | %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> # | %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> # | %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> # | %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> # | %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> # | %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> # | store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8 # | %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8 # | store <8 x i8> %9, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <16 x i8>, align 16 # | %.compoundliteral.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> # | %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> # | %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> # | %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> # | %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> # | %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> # | %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> # | %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> # | %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> # | %9 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> # | %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (1768 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557730c0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557730c08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557730c0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e64f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e64f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e64f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e64f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557730ba1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557730ba1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557730b868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557730835e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557730835b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e64f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e64f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e64f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557730835a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (1769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621834a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621834a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621834a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e81333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e8138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e81333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e8131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056218343bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056218343ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621834208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621830cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621830cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e8131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e8131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e8131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621830cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (1770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fe6debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fe6de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fe6dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f915061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91506725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f915061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9150603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fe6d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fe6d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fe6d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fe6a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fe6a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9150604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91506050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91506050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fe6a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (1771 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055797fbf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055797fbf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055797fbf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ba8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ba8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ba8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ba8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055797fb89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055797fb89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055797fb6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055797f81de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055797f81db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ba8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ba8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ba8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055797f81da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (1772 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcd2d0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcd2d07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcd2d0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f655b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f655b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f655b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f655b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcd2ca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcd2ca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcd2c858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcd2934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcd2934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f655b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f655b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f655b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcd2934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (1773 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/30268) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055971ec87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055971ec84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055971ec8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc71b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc71b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc71b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc71b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055971ec1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055971ec1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055971ec028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055971e8b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055971e8b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc71b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc71b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc71b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055971e8b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mfp8.c (1774 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 { # | entry: # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 { # | entry: # | %mfp8.addr = alloca <1 x i8>, align 1 # | %f1n = alloca [10 x <1 x i8>], align 1 # | store <1 x i8> %mfp8, ptr %mfp8.addr, align 1 # | %0 = load <1 x i8>, ptr %mfp8.addr, align 1 # | %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | store <1 x i8> %0, ptr %arrayidx, align 1 # | %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | %1 = load <1 x i8>, ptr %arrayidx1, align 1 # | ret <1 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | ret <1 x i8> %mfp8ext # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | %v.addr = alloca <1 x i8>, align 1 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | store <1 x i8> %v, ptr %v.addr, align 1 # | %0 = load <1 x i8>, ptr %v.addr, align 1 # | %1 = load i32, ptr %i.addr, align 4 # | %2 = load <16 x i8>, ptr %x.addr, align 16 # | %3 = bitcast <1 x i8> %0 to i8 # | %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1 # | store <16 x i8> %vecins, ptr %x.addr, align 16 # | %4 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # | #0 0x000055e1600aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1600a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1600ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e0e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e0e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e0e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e0e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e160042bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e160042a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1600278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e15fcd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e15fcd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e0e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e0e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e0e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e15fcd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (1775 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/273705) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c44550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c4454de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c4455162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52af11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c444e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c444e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c444cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c4417ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c4417ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52af11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c4417aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (1776 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (1777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (1778 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568745e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568745e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568745e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ac105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ac15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ac105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ac0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055687457abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055687457aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055687455f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055687420ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055687420eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3ac0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ac0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ac0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055687420ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (1779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c789716eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c789713e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c78971762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58db049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58db0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58db049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58db031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7896acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7896aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7896918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c789340e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c789340b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58db032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58db0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58db0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c789340a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (1780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cdc5b66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cdc5b63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cdc5b6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e4f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e4f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e4f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e4f031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdc5afcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cdc5afca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cdc5ae18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cdc5790e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cdc5790b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e4f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e4f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e4f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdc5790a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (1781 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync # | ... # `---data was truncated (10240/10618) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f9e8f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f9e8efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f9e8f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb941649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb941649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb941631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f9e888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f9e888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f9e86d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f9e51ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f9e51cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb941632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9416330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f9e51ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (1782 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572a1116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572a1113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572a111762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadbfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadbfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadbfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadbfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572a10acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572a10aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572a10918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572a0d40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572a0d40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadbfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadbfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadbfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572a0d40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (1783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2a4667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2a4664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2a466862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1edbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1edbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1edbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1edbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2a45fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2a45fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2a45e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2a4291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2a4291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1edbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1edbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1edbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2a4291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (1784 of 27910) ******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %class.Foo = type { i8 } # | %class.HasTrivialDestructor = type { i8 } # | %struct.Data = type { ptr } # | %struct.HasNonTrivialCopyConstructor = type { i8 } # | %struct.HasNonTrivialCopyConstructor2 = type { i8 } # | %struct.LargeWithCopyConstructor = type { [32 x i8] } # | %class.anon = type { i8 } # | # | $_Z12TemplateFuncIiET_S0_ = comdat any # | # | $_Z6Func10IiEii = comdat any # | # | $_Z6Func12IiET_S0_ = comdat any # | # | @pmf = global { i64, i64 } zeroinitializer, align 8 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 { # | entry: # | %retval = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %entry # | %1 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1) # | ret i32 %call # | # | 2: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | if.else: ; preds = %entry # | %3 = load i32, ptr %x.addr, align 4 # | %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3) # | ret i32 %call1 # | # | 4: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %4, %2 # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | declare noundef i32 @_Z3Bari(i32 noundef) #1 # | # | declare noundef i32 @_Z3Bazi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z3Bari(i32 noundef %0) # | %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call) # | ret i32 %call1 # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.Foo, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local void @_Z5Func5v() #0 { # | entry: # | musttail call void @_Z11ReturnsVoidv() # | ret void # | # | 0: ; No predecessors! # | ret void # | } # | # | declare void @_Z11ReturnsVoidv() #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.HasTrivialDestructor, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 { # | entry: # | %data.addr = alloca ptr, align 8 # | store ptr %data, ptr %data.addr, align 8 # | %0 = load ptr, ptr %data.addr, align 8 # | %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %fptr, align 8 # | %2 = load ptr, ptr %data.addr, align 8 # | %call = musttail call noundef i32 %1(ptr noundef %2) # | ret i32 %call # | # | 3: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat { # | entry: # | %.addr = alloca i32, align 4 # | store i32 %0, ptr %.addr, align 4 # | ret i32 5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | %t = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 { # | entry: # | %x.ad # | ... # `---data was truncated (10240/18685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # | #0 0x00005627fcbe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627fcbe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627fcbe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f478c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f478c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f478c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f478c831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627fcb7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627fcb7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627fcb618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627fc810e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627fc810b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f478c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f478c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f478c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627fc810a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (1785 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558222c0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558222c0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558222c0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a40e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a40ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a40e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a40e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558222ba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558222ba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558222b888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558222837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558222837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a40e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a40e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a40e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558222837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (1786 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = or <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = or <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = or <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = or <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, al # | ... # `---data was truncated (10240/11056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562eac666eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562eac663e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562eac66762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb619933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb61998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb619933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb61991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562eac5fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562eac5fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562eac5e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562eac290e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562eac290b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb61991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb61991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb61991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562eac290a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (1787 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (1788 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e98477eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e98474e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e9847862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb97ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb97eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb97ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb97ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e9840dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e9840da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e983f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e980a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e980a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb97ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb97ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb97ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e980a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1789 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e8baa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e8baa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e8baaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8616249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8616249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8616231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e8ba3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e8ba3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e8ba248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e8b6d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e8b6d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8616232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86162330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e8b6d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (1790 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7349cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7349c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7349cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe431a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe431aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe431a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe431a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d734962bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d734962a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7349478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7345f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7345f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe431a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe431a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe431a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7345f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (1791 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2c5bc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2c5bc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2c5bc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff4361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff436725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff4361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff43603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2c5b5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2c5b5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2c5b418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2c57f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2c57f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff43604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff436050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff436050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2c57f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (1792 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (1793 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (1794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584a5793eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584a5790e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584a579462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46d2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46d26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46d2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46d2631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584a5729bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584a5729a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584a570e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584a53bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584a53bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46d2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46d26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46d26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584a53bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (1795 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function # | ... # `---data was truncated (10240/200802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f12816ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f128169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f12816d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f858f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f858f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f858f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f858f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f128102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f128102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1280e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f127d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f127d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f858f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f858f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f858f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f127d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (1796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (1797 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.r # | ... # `---data was truncated (10240/33423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055addcab3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055addcab0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055addcab462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff272c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff272c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff272c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff272c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055addca49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055addca49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055addca2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055addc6dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055addc6ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff272c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff272c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff272c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055addc6dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (1798 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559829c47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559829c44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559829c4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e59e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e59ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e59e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e59e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559829bddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559829bdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559829bc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559829871e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559829871b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e59e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e59e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e59e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559829871a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (1799 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (1800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | s # | ... # `---data was truncated (10240/69534) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be08050eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be0804de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be0805162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc78c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc78c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc78c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc78c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be07fe6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be07fe6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be07fcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be07c7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be07c7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc78c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc78c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc78c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be07c7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (1801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588d3445eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588d3442e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588d344662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff880049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8800a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff880049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff880031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588d33dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588d33dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588d33c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588d306fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588d306fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff880032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8800330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8800330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588d306fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (1802 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a18819eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a18816e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a1881a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f028661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02866725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f028661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0286603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a187afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a187afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a187948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a18443e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a18443b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0286604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02866050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02866050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a18443a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (1803 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055706b2a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055706b2a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055706b2aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5846933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f584698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5846933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f584691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055706b23fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055706b23fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055706b2248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055706aed3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055706aed3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f584691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f584691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f584691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055706aed3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (1804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (1805 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055919bf21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055919bf1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055919bf2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d2e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d2e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d2e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d2e203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055919beb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055919beb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055919be9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055919bb4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055919bb4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d2e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d2e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d2e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055919bb4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (1806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e889d2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e889d29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e889d2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99da249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99da2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99da249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99da231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e889cc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e889cc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e889ca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e889956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e889956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99da232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99da2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99da2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e889956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (1807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/68073) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f38585eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f38582e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f3858662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e70e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e70ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e70e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e70e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f3851bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f3851ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f385008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f381afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f381afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e70e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e70e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e70e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f381afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (1808 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559dfaafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559dfaace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559dfab062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f932b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f932b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f932b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f932b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559dfa45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559dfa45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559dfa2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559df6d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559df6d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f932b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f932b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f932b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559df6d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be907b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be907b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be907b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f647a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f647a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f647a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f647a803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be9074dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be9074da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be907328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be903e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be903e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f647a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f647a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f647a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be903e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (1810 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2a14d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2a14d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2a14d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63a8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63a8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63a8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63a8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2a1469bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2a1469a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2a144e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2a10fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2a10fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63a8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63a8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63a8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2a10fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (1811 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (1812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e544edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e544eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e544ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd25e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd25ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd25e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd25e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e54483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e54483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e544688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e54117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e54117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd25e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd25e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd25e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e54117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (1813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aab7767eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aab7764e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aab776862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2a211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aab76fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aab76fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aab76e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aab7391e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aab7391b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2a211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aab7391a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (1814 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616050d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616050d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616050d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9e1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9e118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9e1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9e111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160506abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056160506aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056160504f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561604cfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561604cfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9e111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9e111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9e111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561604cfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (1815 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbb9bc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbb9bbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbb9bc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f052fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f052faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f052fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f052fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbb9b58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbb9b58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbb9b3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbb97ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbb97ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f052fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f052fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f052fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbb97eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (1817 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560783e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560783e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560783e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbe5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbe558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbe5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbe551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560783d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560783d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560783d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560783a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560783a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbe551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbe551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbe551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560783a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1818 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632f7a5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632f7a58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632f7a5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53a671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632f79f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632f79f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632f79d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632f7685e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632f7685b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53a671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632f7685a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (1819 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558daf22aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558daf227e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558daf22b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87a0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87a098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87a0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87a091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558daf1c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558daf1c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558daf1a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558daee54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558daee54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87a091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87a091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87a091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558daee54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/SystemZ/zvector.c (1820 of 27910) ******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c" # | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" # | target triple = "s390x-unknown-linux-gnu" # | # | @sc2 = global <16 x i8> zeroinitializer, align 8 # | @sc = global <16 x i8> zeroinitializer, align 8 # | @uc2 = global <16 x i8> zeroinitializer, align 8 # | @uc = global <16 x i8> zeroinitializer, align 8 # | @ss2 = global <8 x i16> zeroinitializer, align 8 # | @ss = global <8 x i16> zeroinitializer, align 8 # | @us2 = global <8 x i16> zeroinitializer, align 8 # | @us = global <8 x i16> zeroinitializer, align 8 # | @si2 = global <4 x i32> zeroinitializer, align 8 # | @si = global <4 x i32> zeroinitializer, align 8 # | @ui2 = global <4 x i32> zeroinitializer, align 8 # | @ui = global <4 x i32> zeroinitializer, align 8 # | @sl2 = global <2 x i64> zeroinitializer, align 8 # | @sl = global <2 x i64> zeroinitializer, align 8 # | @ul2 = global <2 x i64> zeroinitializer, align 8 # | @ul = global <2 x i64> zeroinitializer, align 8 # | @slll2 = global <1 x i128> zeroinitializer, align 8 # | @slll = global <1 x i128> zeroinitializer, align 8 # | @ulll2 = global <1 x i128> zeroinitializer, align 8 # | @ulll = global <1 x i128> zeroinitializer, align 8 # | @fd2 = global <2 x double> zeroinitializer, align 8 # | @fd = global <2 x double> zeroinitializer, align 8 # | @bc2 = global <16 x i8> zeroinitializer, align 8 # | @bc = global <16 x i8> zeroinitializer, align 8 # | @bs2 = global <8 x i16> zeroinitializer, align 8 # | @bs = global <8 x i16> zeroinitializer, align 8 # | @bi2 = global <4 x i32> zeroinitializer, align 8 # | @bi = global <4 x i32> zeroinitializer, align 8 # | @bl2 = global <2 x i64> zeroinitializer, align 8 # | @bl = global <2 x i64> zeroinitializer, align 8 # | @blll2 = global <1 x i128> zeroinitializer, align 8 # | @blll = global <1 x i128> zeroinitializer, align 8 # | @cnt = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_assign() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_pos() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_neg() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %sub = sub <16 x i8> zeroinitializer, %0 # | store volatile <16 x i8> %sub, ptr @sc, align 8 # | %1 = load volatile <8 x i16>, ptr @ss2, align 8 # | %sub1 = sub <8 x i16> zeroinitializer, %1 # | store volatile <8 x i16> %sub1, ptr @ss, align 8 # | %2 = load volatile <4 x i32>, ptr @si2, align 8 # | %sub2 = sub <4 x i32> zeroinitializer, %2 # | store volatile <4 x i32> %sub2, ptr @si, align 8 # | %3 = load volatile <2 x i64>, ptr @sl2, align 8 # | %sub3 = sub <2 x i64> zeroinitializer, %3 # | store volatile <2 x i64> %sub3, ptr @sl, align 8 # | %4 = load volatile <1 x i128>, ptr @slll2, align 8 # | %sub4 = sub <1 x i128> zeroinitializer, %4 # | store volatile <1 x i128> %sub4, ptr @slll, align 8 # | %5 = load volatile <2 x double>, ptr @fd2, align 8 # | %fneg = fneg <2 x double> %5 # | store volatile <2 x double> %fneg, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_preinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_postinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_predec() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %dec = add <16 x i8> %0, splat (i8 -1) # | store volatile <16 x i8> %dec, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %dec1 = add <16 x i8> %1, splat (i8 -1) # | store volatile <16 x i8> %dec1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %dec2 = add <8 x i16> %2, splat (i16 -1) # | store volatile <8 x i16> %dec2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %dec3 = add <8 x i16> %3, splat (i16 -1) # | store volatile <8 x i16> %dec3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %dec4 = add <4 x i32> %4, splat (i32 -1) # | store volatile <4 x i32> %dec4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %dec5 = add <4 x i32> %5, splat (i32 -1) # | store volatile <4 x i32> %dec5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %dec6 = add <2 x i64> %6, splat (i64 -1) # | store volatile <2 x i64> %dec6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %dec7 = add <2 x i64> %7, splat (i64 -1) # | store volatile <2 x i64> %dec7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %dec8 = add <1 x i128> %8, splat (i128 -1) # | store volatile <1 x i128> %dec8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %dec # | ... # `---data was truncated (10240/152876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0b3db4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0b3db1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0b3db562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe425505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe42555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe425505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4254ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0b3d4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0b3d4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0b3d2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0b39dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0b39deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4254eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4254ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4254ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0b39dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (1821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (1822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %ba # | ... # `---data was truncated (10240/24100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056213a5a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056213a5a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056213a5a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f274c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f274c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f274c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f274c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056213a539bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056213a539a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056213a51e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056213a1cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056213a1cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f274c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f274c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f274c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056213a1cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (1823 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/15203) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056123fdf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056123fdf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056123fdf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa63e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa63ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa63e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa63e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056123fd89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056123fd89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056123fd6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056123fa1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056123fa1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa63e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa63e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa63e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056123fa1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (1824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbd4e84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbd4e81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbd4e8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe320249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3202a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe320249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe320231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbd4e1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbd4e1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbd4dff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbd4aaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbd4aaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe320232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3202330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3202330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbd4aaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (1825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a517e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a517e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a517e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9148449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9148449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9148431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a5177cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a5177ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a517618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a51410e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a51410b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9148432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91484330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a51410a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (1826 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nou # | ... # `---data was truncated (10240/25034) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055942ed85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055942ed82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055942ed8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4ece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4ecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4ece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4ece31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055942ed1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055942ed1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055942ed008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055942e9afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055942e9afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4ece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4ece330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4ece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055942e9afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (1827 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1828 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (1829 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (1830 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5bb01eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5bb01be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5bb01f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f334ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f334eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f334ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f334ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5bafb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5bafb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5baf998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5bac48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5bac48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f334ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f334ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f334ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5bac48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (1831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b99432eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b9942fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b9943362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ec1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ec155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ec1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ec14ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b993c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b993c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b993ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b9905ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b9905cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ec14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ec14ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ec14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b9905ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (1832 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/51751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598532d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598532d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598532da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f972ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f972ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f972ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f972ac03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055985326fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055985326fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598532548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559852f03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559852f03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f972ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f972ac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f972ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559852f03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (1833 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646d1194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646d1191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646d119562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c80449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c80449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c80431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646d112abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646d112aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646d110f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646d0dbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646d0dbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c80432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c804330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646d0dbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (1834 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055791534ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557915349e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055791534d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e7e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e7e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e7e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e7e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579152e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579152e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579152c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557914f76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557914f76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e7e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e7e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e7e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557914f76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (1835 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/48385) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe461c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe461c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe461c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f705a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f705a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f705a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f705a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe4615dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe4615da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe461428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe45df1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe45df1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f705a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f705a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f705a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe45df1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (1836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, # | ... # `---data was truncated (10240/29443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0c94a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0c949fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0c94a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6516049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6516049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6516031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0c9438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0c9438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0c941d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0c90cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0c90ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6516032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65160330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0c90cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (1837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/126436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564d6af6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564d6af3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564d6af762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a91c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a91ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a91c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a91c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564d6a8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564d6a8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564d6a718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564d6720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564d6720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a91c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a91c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a91c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564d6720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tupl # | ... # `---data was truncated (10240/88444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e43297beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e432978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e43297c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd12d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd12d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd12d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd12d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e432911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e432911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4328f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4325a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4325a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd12d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd12d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd12d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4325a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (1839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (1840 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (1841 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (1842 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c5dad8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c5dad5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c5dad962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1ab533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1ab58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1ab533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1ab51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c5da6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c5da6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c5da538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c5d702e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c5d702b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1ab51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1ab51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1ab51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c5d702a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (1843 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca # | ... # `---data was truncated (10240/124506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a726a44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a726a41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a726a4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bf2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bf238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bf2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bf231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7269dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7269daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7269bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a72666ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a72666eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0bf231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bf231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bf231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a72666ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (1844 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d00611eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d0060ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d0061262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc1f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc1f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc1f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc1f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d005a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d005a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d0058c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d0023be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d0023bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc1f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc1f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc1f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d0023ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (1845 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (1846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (1847 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/98581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cfa714eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563cfa711e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563cfa71562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff645905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff64595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff645905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6458ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cfa6aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563cfa6aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563cfa68f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563cfa33ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563cfa33eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6458eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6458ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6458ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cfa33ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (1848 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce97f96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce97f93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce97f9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b54c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b54ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b54c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b54c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce97f2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce97f2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce97f118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce97bc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce97bc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b54c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b54c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b54c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce97bc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (1849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, a # | ... # `---data was truncated (10240/28358) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565062c15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565062c12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565062c1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f736e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f736e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f736e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f736e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565062babbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565062baba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565062b908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056506283fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056506283fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f736e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f736e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f736e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056506283fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (1850 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (1851 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b6d4fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b6d4f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b6d4fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72aa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72aa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72aa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72aa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b6d492bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b6d492a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b6d4778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b6d126e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b6d126b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f72aa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72aa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72aa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b6d126a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (1852 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (1853 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4a572eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4a572be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4a572f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f888c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f888c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f888c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f888c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4a56c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4a56c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4a56a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4a5358e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4a5358b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f888c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f888c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f888c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4a5358a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (1854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6b94e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6b94dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6b94e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6ddb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6b9477bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6b9477a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6b945c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6b910be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6b910bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6b910ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (1855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf47ef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf47eefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf47ef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe128f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe128f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe128f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe128f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf47e88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf47e88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf47e6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf47b1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf47b1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe128f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe128f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe128f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf47b1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (1856 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (1857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | # | ... # `---data was truncated (10240/23255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d2e51feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d2e51ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d2e52062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e45933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e4598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e45933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e4591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d2e4b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d2e4b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d2e49a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d2e149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d2e149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e4591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e4591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e4591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d2e149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (1858 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056187de59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056187de56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056187de5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa796333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa79638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa796333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa79631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056187ddefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056187ddefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056187ddd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056187da83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056187da83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa79631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa79631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa79631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056187da83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (1859 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056160c613eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056160c610e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056160c61462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f580d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f580d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f580d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f580d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160c5a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056160c5a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056160c58e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056160c23de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056160c23db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f580d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f580d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f580d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056160c23da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (1860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (1861 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # | #0 0x0000564d687c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d687bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d687c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f441ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f441aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f441ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f441ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d68757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d68757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d6873c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d683ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d683ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f441ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f441ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f441ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d683eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (1862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebed93eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebed93be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebed93f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b30449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b304a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b30449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b30431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebed8d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebed8d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebed8b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebed568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebed568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b30432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b304330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b304330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebed568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (1863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560c6589eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560c6586e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560c658a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1717133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f171718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1717133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f171711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560c651fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560c651fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560c65048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560c61b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560c61b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f171711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f171711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f171711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560c61b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (1864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, # | ... # `---data was truncated (10240/28354) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ba4e41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ba4e3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ba4e4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a84c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a84c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a84c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a84c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ba4dd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ba4dd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ba4dbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ba4a6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ba4a6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a84c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a84c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a84c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ba4a6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (1865 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630ea663eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630ea660e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630ea66462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbcd505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbcd55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbcd505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbcd4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630ea5f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630ea5f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630ea5de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630ea28de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630ea28db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbcd4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbcd4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbcd4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630ea28da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (1866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1eb3f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1eb3eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1eb3f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7e7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7e7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7e7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7e7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1eb387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1eb387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1eb36c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1eb01be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1eb01bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7e7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7e7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7e7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1eb01ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (1867 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26b318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c26b315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c26b31962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecdcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecdcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecdcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecdcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c26b2aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c26b2aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c26b2938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c26af42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c26af42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecdcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecdcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecdcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26af42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (1868 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618e254deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618e254ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618e254e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f8ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f8ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f8ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f8ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618e24e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618e24e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618e24c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618e2177e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618e2177b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f8ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f8ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f8ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618e2177a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (1869 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1ca45deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1ca45ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1ca45e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1385049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13850a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1385049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1385031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1ca3f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1ca3f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1ca3d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1ca087e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1ca087b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1385032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13850330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13850330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1ca087a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (1870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (1871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0ae07beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0ae078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0ae07c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40c9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40c915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40c9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40c90ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0ae011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0ae011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0adff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0adca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0adca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40c90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40c90ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40c90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0adca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (1872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561141360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056114135de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056114136162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e71c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e71ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e71c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e71c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611412f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611412f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611412db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561140f8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561140f8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e71c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e71c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e71c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561140f8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (1873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592c8228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592c8225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592c822962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff840305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff84035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff840305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8402ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c81bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592c81bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592c81a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592c7e52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592c7e52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8402eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8402ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8402ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c7e52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (1874 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a4a8f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a4a8f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a4a8f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5902e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5902ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5902e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5902e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a4a88dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a4a88da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a4a8728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a4a521e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a4a521b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5902e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5902e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5902e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a4a521a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (1875 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/110070) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634be95deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634be95ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634be95e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d2af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d2af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d2af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d2aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634be8f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634be8f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634be8d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634be587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634be587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d2aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d2aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d2aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634be587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (1876 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7d68c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7d68c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7d68c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1104d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1104d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1104d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1104d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7d685bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7d685ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7d68408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7d64efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7d64efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1104d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1104d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1104d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7d64efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (1877 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056309d992eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056309d98fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056309d99362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe23b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe23b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe23b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe23b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056309d928bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056309d928a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056309d90d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056309d5bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056309d5bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe23b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe23b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe23b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056309d5bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (1878 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 # | ... # `---data was truncated (10240/15508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f0d1baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f0d1b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f0d1bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec0bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec0bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec0bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec0bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f0d150bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f0d150a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f0d1358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f0cde4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f0cde4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec0bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec0bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec0bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f0cde4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (1879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc72e3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc72e39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc72e3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faec4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faec46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faec4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faec4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc72dd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc72dd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc72db78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc72a66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc72a66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faec4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faec46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faec46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc72a66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (1880 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | ret <8 x half> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 { # | entry: # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | ret <4 x float> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca half, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store half %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %3, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store float %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %3, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, # | ... # `---data was truncated (10240/17297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055b7d7865eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7d7862e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7d786662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fdd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fdd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fdd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fdd431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7d77fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7d77fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7d77e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7d748fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7d748fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fdd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fdd4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fdd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7d748fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (1881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559401549eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559401546e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055940154a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f789001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78900725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f789001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7890003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594014dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594014dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594014c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559401173e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559401173b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7890004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78900050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78900050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559401173a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (1882 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7bb224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7bb221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7bb22562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d69849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d69849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d69831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7bb1babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7bb1baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7bb19f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7bae4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7bae4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d69832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d698330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7bae4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (1883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579d3212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579d320fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579d321362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5da049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5da0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5da049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5da031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579d31a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579d31a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579d318d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579d2e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579d2e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5da032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5da0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5da0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579d2e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (1884 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570acea8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570acea5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570acea962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3849d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3849d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3849d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3849ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570ace3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570ace3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570ace238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570acad2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570acad2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3849ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3849cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3849cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570acad2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (1885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563242c4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563242c4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563242c4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb140e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb140ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb140e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb140e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563242be3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563242be3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563242bc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563242877e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563242877b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb140e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb140e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb140e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563242877a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (1886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf4x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf4x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf4x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf4x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf4x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf4x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf2x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf2x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf2x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf2x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m1x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m1x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m1x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16m1x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16m1x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16m1x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16m1x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563111576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563111573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056311157762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96cec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056311150cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056311150ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631114f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631111a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631111a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96cec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631111a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (1887 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstrid # | ... # `---data was truncated (10240/17118) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f38833eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f38833be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f38833f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8dfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8dfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8dfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8dfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3882d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3882d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3882b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f387f68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f387f68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8dfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8dfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8dfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f387f68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643e4863eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643e4860e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643e486462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9dd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9dd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9dd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9dd2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643e47f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643e47f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643e47de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643e448de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643e448db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9dd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9dd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9dd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643e448da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (1889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e11879eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e11876e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e1187a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3a771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e1180fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e1180fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e117f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e114a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e114a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3a771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e114a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (1890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (1891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (1892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (1893 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558ac34aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558ac347e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558ac34b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f932f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f932f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f932f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f932f603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558ac2e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558ac2e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558ac2c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558abf74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558abf74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f932f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f932f6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f932f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558abf74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (1894 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b8( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.vector.reverse.nxv16i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b16( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b32( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b64( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8bf16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056314d0fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056314d0f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056314d0fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda55449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda55449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda55431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056314d092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056314d092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056314d0778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056314cd26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056314cd26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda55432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda554330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056314cd26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (1895 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a96e95beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a96e958e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a96e95c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb27f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb27f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb27f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb27f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a96e8f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a96e8f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a96e8d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a96e585e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a96e585b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb27f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb27f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb27f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a96e585a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (1896 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9f4903eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9f4900e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9f490462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe080d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe080d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe080d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe080d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9f4899bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9f4899a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9f487e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9f452de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9f452db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe080d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe080d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe080d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9f452da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (1897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614fc550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614fc54de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614fc55162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faca0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faca0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faca0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faca0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614fc4e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614fc4e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614fc4cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614fc17ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614fc17ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faca0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faca0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faca0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614fc17aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (1898 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (1899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2a5b3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2a5b3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2a5b3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb1841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb184725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb1841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb18403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2a5ad3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2a5ad3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2a5ab88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2a5767e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2a5767b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb18404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb184050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb184050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2a5767a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (1900 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/83080) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602d34c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602d34c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602d34c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3166b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3166b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3166b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3166b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602d345dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602d345da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602d34428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602d30f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602d30f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3166b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3166b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3166b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602d30f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (1901 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f5acf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f5acf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f5acfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f191eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f191eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f191eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f191eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f5ac8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f5ac8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f5ac748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f5a923e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f5a923b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f191eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f191eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f191eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f5a923a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (1902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i64 immar # | ... # `---data was truncated (10240/14780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3be6e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3be6e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3be6e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3be67bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3be67ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3be6608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3be30fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3be30fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3be30fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d9ebf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d9ebf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d9ebf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91cb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91cb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91cb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91cb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d9eb8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d9eb8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d9eb718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d9e820e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d9e820b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91cb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91cb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91cb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d9e820a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (1904 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635ad14beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635ad148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635ad14c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f514e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f514e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f514e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f514e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635ad0e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635ad0e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635ad0c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635acd75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635acd75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f514e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f514e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f514e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635acd75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (1905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e013dc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e013dc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e013dc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0972249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0972249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0972231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e013d59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e013d59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e013d3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0139ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0139edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0972232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09722330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0139eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (1906 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1907 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca targe # | ... # `---data was truncated (10240/53556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607f067beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607f0678e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607f067c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fbac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fbaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fbac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fbac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607f0611bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607f0611a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607f05f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607f02a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607f02a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fbac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fbac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fbac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607f02a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (1908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3e0049eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3e0046e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3e004a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecb5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecb56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecb5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecb5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3dffdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3dffdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3dffc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3dfc73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3dfc73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecb5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecb56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecb56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3dfc73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (1909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576062b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576062b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576062b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5852449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5852449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5852431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055760624ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055760624ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576062338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557605ee2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557605ee2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5852432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58524330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557605ee2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (1910 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/136489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cb3755eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cb3752e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cb375662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cb36ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cb36eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cb36d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cb337fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cb337fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3d2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cb337fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (1911 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572bff02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572bfeffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572bff0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86ffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86ffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86ffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86ffa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572bfe98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572bfe98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572bfe7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572bfb2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572bfb2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86ffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86ffa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86ffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572bfb2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (1912 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (1913 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636bb9e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636bb9e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636bb9e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaf8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaf8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaf8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaf8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636bb979bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636bb979a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636bb95e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636bb60de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636bb60db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaf8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaf8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaf8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636bb60da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (1914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vs # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de50608eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de50605e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de5060962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbea1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbea118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbea1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbea111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de5059ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de5059ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de505838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de50232e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de50232b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbea111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbea111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbea111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de50232a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (1915 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 # | ... # `---data was truncated (10240/32570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584a8438eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584a8435e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584a843962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ac8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ac8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ac8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ac8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584a83cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584a83cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584a83b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584a8062e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584a8062b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ac8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ac8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ac8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584a8062a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (1916 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a936aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a936a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a936ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5146d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5146d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5146d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5146d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a93640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a93640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a936258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a932d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a932d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5146d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5146d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5146d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a932d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (1917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e6571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646e656ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646e657262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d9a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d9a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d9a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d9a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e6507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646e6507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646e64ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646e619be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646e619bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d9a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d9a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d9a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e619ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (1918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa440faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa440f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa440fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e19049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e190a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e19049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e19031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa44090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa44090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa440758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa43d24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa43d24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e19032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e190330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e190330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa43d24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (1919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (1920 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (1921 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, a # | ... # `---data was truncated (10240/13410) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556889aa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556889a9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556889aa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5995533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f599558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5995533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f599551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556889a36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556889a36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556889a1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568896cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568896cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f599551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f599551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f599551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568896caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (1922 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, # | ... # `---data was truncated (10240/27986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055739b67deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055739b67ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055739b67e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16d6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055739b613bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055739b613a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055739b5f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055739b2a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055739b2a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055739b2a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1923 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055590a622eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055590a61fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055590a62362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff46ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff46baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff46ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff46ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055590a5b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055590a5b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055590a59d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055590a24ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055590a24cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff46ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff46ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff46ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055590a24ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (1924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb6618beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb66188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb6618c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8abfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8abfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8abfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8abfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb66121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb66121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb661068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb65db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb65db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8abfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8abfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8abfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb65db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (1925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e795b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e795ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e795b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0464249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04642a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0464249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0464231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e79546bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e79546a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e7952b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e791dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e791dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0464232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04642330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04642330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e791daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (1926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/65883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b6982feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b6982ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b6983062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaae933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaae98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaae933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaae91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b697c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b697c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b697aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b69459e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b69459b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaae91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaae91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaae91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b69459a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1927 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv1f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv2f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m1_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv4f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv16f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m8_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv32f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32mf2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv1f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m1_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m4_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv8f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m8_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv16f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m1_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv1f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m2_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m4_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv4f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m8_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv8f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055adabaa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055adaba9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055adabaa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d65f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d65f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d65f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d65f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adaba37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055adaba37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055adaba1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055adab6cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055adab6cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d65f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d65f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d65f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adab6cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (1928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4bea0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4bea08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4bea0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef02e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef02e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef02e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef02e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4be9a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4be9a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4be9868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4be635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4be635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef02e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef02e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef02e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4be635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (1929 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7829eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7829e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7829ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff272e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff272e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff272e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff272e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b782982bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b782982a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7829678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b782616e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b782616b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff272e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff272e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff272e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b782616a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (1930 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa22f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa22f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa22f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85c8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85c8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85c8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85c8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa22ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa22ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa22ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa22b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa22b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85c8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85c8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85c8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa22b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (1931 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (1932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5de27ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5de279e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5de27d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe63a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe63a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe63a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe63a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5de212bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5de212a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5de1f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5ddea6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5ddea6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe63a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe63a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe63a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5ddea6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (1933 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | ... # `---data was truncated (10240/66298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616039d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616039d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616039d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6faa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160396cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056160396ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616039518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561603600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561603600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe6faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6faa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561603600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (1934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bc008deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bc008ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bc008e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f155b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f155b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f155b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f155b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bc0023bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bc0023a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bc00088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bbfcb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bbfcb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f155b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f155b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f155b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bbfcb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = e # | ... # `---data was truncated (10240/100513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055564c2e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055564c2dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055564c2e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f353de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f353de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f353de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f353de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055564c277bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055564c277a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055564c25c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055564bf0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055564bf0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f353de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f353de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f353de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055564bf0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (1936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b7b8aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b7b8a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b7b8ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9efa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9efaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9efa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9efa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b7b842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b7b842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b7b8278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b7b4d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b7b4d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9efa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9efa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9efa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b7b4d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (1937 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0d3583eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0d3580e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0d358462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87af61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87af6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87af61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87af603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0d3519bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0d3519a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0d34fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0d31ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0d31adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87af604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87af6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87af6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0d31ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (1938 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d32dc4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d32dc49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d32dc4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76d5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76d58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76d5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76d5831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d32dbe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d32dbe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d32dbc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d32d876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d32d876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76d5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76d58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76d58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d32d876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (1939 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/71955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a80d52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a80d4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a80d5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3706b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3706b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3706b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3706b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a80ce8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a80ce8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a80ccd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a8097ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a8097cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3706b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3706b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3706b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a8097ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (1940 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a9ba52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a9ba4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a9ba5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8f1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8f14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8f1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8f1431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a9b9e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a9b9e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a9b9cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a9b67ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a9b67cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8f1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8f14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8f14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a9b67ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (1941 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/39578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffd0c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ffd0c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ffd0c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc28c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc28c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc28c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc28c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffd0be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ffd0be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ffd0bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ffd0874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ffd0874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc28c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc28c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc28c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffd0874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (1942 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (1943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c849237eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c849234e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c84923862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87bb031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8491cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8491cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8491b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c848e61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c848e61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87bb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c848e61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (1944 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i16 # | ... # `---data was truncated (10240/84971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615f0c26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615f0c23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615f0c2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6bf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6bf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6bf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6bf631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615f0bbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615f0bbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615f0ba18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615f0850e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615f0850b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6bf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6bf6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6bf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615f0850a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (1946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577db228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577db225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577db22962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd18f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd18f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd18f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd18f603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577db1bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577db1bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577db1a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577dae52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577dae52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd18f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd18f6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd18f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577dae52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (1947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578484b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578484b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578484b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a38133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a3818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a38133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a3811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055784844dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055784844da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578484328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578480e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578480e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a3811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a3811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a3811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578480e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3280a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3280a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3280a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49bd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49bd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49bd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49bd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f32803abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f32803aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f32801f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f327ccee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f327cceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49bd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49bd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49bd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f327ccea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (1949 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed50a46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed50a43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed50a4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd28c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd28c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd28c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd28c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed509dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed509dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed509c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed50670e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed50670b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd28c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd28c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd28c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed50670a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (1950 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ce49a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ce49a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ce49aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe920505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe92055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe920505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9204ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ce493fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ce493fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ce49248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ce45d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ce45d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9204eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9204ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9204ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ce45d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (1951 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637ffc2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637ffc27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637ffc2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a45933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a4598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a45933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a4591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637ffbc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637ffbc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637ffba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637ff854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637ff854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a4591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a4591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a4591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637ff854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (1952 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055655741ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556557419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055655741d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78dc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78dc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78dc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78dc031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565573b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565573b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565573978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556557046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556557046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78dc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78dc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78dc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556557046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (1953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (1954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558baf14feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558baf14ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558baf15062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f0ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f0aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f0ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f0ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558baf0e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558baf0e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558baf0ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558baed79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558baed79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f0ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f0ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f0ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558baed79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (1955 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562aebf04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562aebf01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562aebf0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7eec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7eec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7eec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7eec03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aebe9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562aebe9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562aebe7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562aebb2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562aebb2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7eec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7eec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7eec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aebb2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-shifts.c (1956 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"apcs-gnu"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fde9f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fde9f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fde9f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe11f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe11f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe11f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe11f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fde98bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fde98ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fde9708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fde61fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fde61fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe11f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe11f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe11f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fde61fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (1957 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5c72daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5c72d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5c72db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00de733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00de78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00de733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00de71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5c7270bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5c7270a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5c72558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5c6f04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5c6f04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f00de71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00de71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00de71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5c6f04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (1958 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b821e33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b821e30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b821e3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3beaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3beaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3beaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3beaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b821dc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b821dc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b821dae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b821a5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b821a5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3beaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3beaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3beaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b821a5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (1959 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612eaef9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612eaef6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612eaefa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8aa0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8aa08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8aa0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8aa0831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612eae8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612eae8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612eae748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612eab23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612eab23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8aa0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8aa08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8aa08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612eab23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (1960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2295d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2295d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2295d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f187af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f187af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f187af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f187af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22956dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a22956da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2295528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a229201e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a229201b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f187af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f187af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f187af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a229201a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (1961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564622608eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564622605e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056462260962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056462259ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056462259ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646225838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564622232e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564622232b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ce4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564622232a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (1962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (1963 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (1964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564b4426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564b4423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564b442762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1f6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1f6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1f6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1f6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564b43bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564b43bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564b43a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564b4050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564b4050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1f6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1f6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1f6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564b4050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (1965 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp ule <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp sle <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp ule <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbae220eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbae21de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbae22162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa91d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa91d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa91d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa91d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbae1b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbae1b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbae19b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbade4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbade4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa91d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa91d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa91d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbade4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (1966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596a71a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596a71a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596a71a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa687333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa68738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa687333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa68731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596a713cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596a713ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596a71218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596a6dd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596a6dd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa68731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa68731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa68731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596a6dd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (1967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/26976) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e666266eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e666263e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e66626762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dbef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dbef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dbef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dbef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6661fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6661fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6661e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e665e90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e665e90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1dbef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dbef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dbef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e665e90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (1968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (1969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560999707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560999704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056099970862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb80a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb80a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb80a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb80a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056099969dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056099969da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609996828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560999331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560999331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb80a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb80a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb80a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560999331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (1970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx. # | ... # `---data was truncated (10240/28427) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055579bf3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055579bf38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055579bf3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1b2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1b26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1b2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1b2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055579bed1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055579bed1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055579beb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055579bb65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055579bb65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1b2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1b26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1b26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055579bb65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (1971 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638edbebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005638edbe8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005638edbec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a0771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638edb81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638edb81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638edb668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005638ed815e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005638ed815b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a0771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638ed815a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (1972 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (1973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , flo # | ... # `---data was truncated (10240/34773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055954fb23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055954fb20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055954fb2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49c7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055954fab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055954fab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055954fa9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055954f74de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055954f74db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055954f74da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (1974 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055787cea6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055787cea3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055787cea762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f938fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f938fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f938fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f938fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055787ce3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055787ce3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055787ce218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055787cad0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055787cad0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f938fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f938fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f938fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055787cad0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (1975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e709d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e709d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e709d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3687733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f368778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3687733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f368771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e7096dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e7096da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e709528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e70601e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e70601b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f368771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f368771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f368771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e70601a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (1976 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617ceea7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617ceea4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617ceea862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75cc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75cc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75cc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75cc71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617cee3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617cee3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617cee228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617cead1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617cead1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75cc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75cc71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75cc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617cead1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (1977 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load ptr, ptr %carry.addr, align 4 # | %4 = load i32, ptr %3, align 4 # | %5 = shl i32 %4, 29 # | %6 = load i16, ptr %p.addr, align 2 # | %7 = zext i16 %6 to i32 # | %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7) # | %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8) # | %10 = extractvalue { <4 x i32>, i32 } %9, 1 # | %11 = lshr i32 %10, 29 # | %12 = and i32 1, %11 # | store i32 %12, ptr %3, align 4 # | %13 = extractvalue { <4 x i32>, i32 } %9, 0 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, # | ... # `---data was truncated (10240/14775) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559594ff2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559594fefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559594ff362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d31f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d31f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d31f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d31f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559594f88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559594f88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559594f6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559594c1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559594c1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d31f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d31f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d31f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559594c1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (1978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcbbe84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcbbe81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcbbe8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6042733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f604278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6042733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f604271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcbbe1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcbbe1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcbbdff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcbbaaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcbbaaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f604271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f604271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f604271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcbbaaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (1979 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558219225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558219222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055821922662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d37133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d3718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d37133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d3711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582191bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582191bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582191a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558218e4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558218e4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d3711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d3711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d3711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558218e4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (1980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e09682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e0967fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e0968362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff32af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff32af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff32af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff32af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e09618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e09618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e095fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e092ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e092acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff32af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff32af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff32af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e092aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (1981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d940f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d940f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d940f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c6c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c6c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c6c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c6c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d9408ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d9408ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d940738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d93d22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d93d22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c6c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c6c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c6c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d93d22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (1982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561230be5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561230be2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561230be662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0cc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0cc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0cc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0cc431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561230b7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561230b7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561230b608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056123080fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056123080fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0cc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0cc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0cc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056123080fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (1983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/40411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559271651eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055927164ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055927165262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a19333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a1938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a19333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a1931b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592715e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592715e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592715cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055927127be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055927127bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a1931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a1931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a1931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055927127ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (1984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd3b244eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd3b241e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd3b24562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dc6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dc618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dc6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dc611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd3b1dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd3b1daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd3b1bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd3ae6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd3ae6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dc611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dc611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dc611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd3ae6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (1985 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (1986 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/18925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff61871eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff6186ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff6187262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff86d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff86d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff86d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff86d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff61807bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff61807a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff617ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff6149be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff6149bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff86d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff86d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff86d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff6149ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (1987 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (1988 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565ee2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565ee2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565ee2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff242449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff242449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff242431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565ee254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565ee254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565ee2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565edee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565edee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff242432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2424330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565edee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (1989 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , # | ... # `---data was truncated (10240/154207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b082283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b082280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b08228462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ca9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ca958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ca9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ca951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b082219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b082219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0821fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b081eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b081eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ca951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ca951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ca951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b081eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (1990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1bd44feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1bd44ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1bd45062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bfbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bfbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bfbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bfbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1bd3e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1bd3e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1bd3ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1bd079e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1bd079b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bfbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bfbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bfbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1bd079a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (1991 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a13552eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a1354fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a1355362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f89d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f89d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f89d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f89d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a134e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a134e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a134cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a1317ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a1317cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f89d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f89d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f89d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a1317ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (1992 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fc13fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fc13f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fc13fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d54733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d5478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d54733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d5471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fc1392bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fc1392a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fc13778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fc1026e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fc1026b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d5471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d5471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d5471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fc1026a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (1993 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (1994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback # | ... # `---data was truncated (10240/15245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca8f37eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca8f37be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca8f37f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec3c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec3c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec3c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec3c2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca8f314bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca8f314a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca8f2f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca8efa8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca8efa8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec3c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec3c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec3c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca8efa8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (1995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb4f453eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb4f450e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb4f45462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda9a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda9a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda9a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda9a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb4f3e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb4f3e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb4f3ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb4f07de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb4f07db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda9a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda9a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda9a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb4f07da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (1996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/134744) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056204e6deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056204e6dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056204e6df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5e9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056204e674bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056204e674a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056204e6598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056204e308e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056204e308b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056204e308a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (1997 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20139) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564296cb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564296cb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564296cba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa96849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa96849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa96831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564296c4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564296c4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564296c348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642968e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642968e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa96832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642968e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (1998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/77062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568bf7c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568bf7bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568bf7c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11dfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11dfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11dfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11dfc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568bf757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568bf757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568bf73c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568bf3ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568bf3ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f11dfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11dfc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11dfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568bf3eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (1999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f4e07eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f4e07be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f4e07f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54f7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f4e014bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f4e014a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f4dff98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f4dca8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f4dca8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f4dca8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (2000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfe3539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfe3536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfe353a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7d971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfe34cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfe34cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfe34b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfe3163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfe3163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7d971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfe3163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (2001 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/13593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a57119feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a57119ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5711a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39fa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39fa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39fa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39fa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a571135bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a571135a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a57111a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a570dc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a570dc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39fa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39fa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39fa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a570dc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (2002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed4eb2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed4eb28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed4eb2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda27733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda2778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda27733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda2771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed4eac1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed4eac1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed4eaa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed4e755e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed4e755b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda2771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda2771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda2771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed4e755a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (2003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d7183eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d7183be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d7183f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5a603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d717d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d717d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d717b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d71468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d71468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f5a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5a6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d71468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (2004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (2005 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/26996) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d17cfbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d17cfbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d17cfbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0646a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0646a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0646a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0646a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d17cf53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d17cf53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d17cf388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d17cbe7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d17cbe7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0646a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0646a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0646a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d17cbe7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (2006 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, pt # | ... # `---data was truncated (10240/174721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c540a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c540a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c540a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fbd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fbd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fbd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fbd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c5403dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c5403da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c540228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c53cd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c53cd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fbd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fbd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fbd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c53cd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (2007 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d75f05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d75f02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d75f0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb62b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb62b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb62b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb62b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d75e9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d75e9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d75e808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d75b2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d75b2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb62b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb62b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb62b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d75b2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (2008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556475a2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556475a28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556475a2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8832d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8832d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8832d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8832d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564759c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005564759c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564759a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556475655e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556475655b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8832d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8832d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8832d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556475655a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (2009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8819d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8819cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8819d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f517c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f517c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f517c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f517c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b881968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b881968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b88194d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8815fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8815fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f517c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f517c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f517c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8815fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (2010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | # | ... # `---data was truncated (10240/25279) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562be20efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562be20ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562be20f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3db049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3db0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3db049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3db031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562be2085bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562be2085a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562be206a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562be1d19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562be1d19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3db032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3db0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3db0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562be1d19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (2011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560515e32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560515e2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560515e3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee82933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee8298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee82933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee8291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560515dc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560515dc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560515dad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560515a5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560515a5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee8291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee8291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee8291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560515a5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (2012 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/11851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1696c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1696c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1696ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb209049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb209049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb209031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c16965fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c16965fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1696448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1692f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1692f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb209032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2090330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1692f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (2013 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (2014 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575b6c6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575b6c6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575b6c7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effd5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effd558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effd5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effd551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575b6c05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575b6c05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575b6bea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575b6899e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575b6899b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effd551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effd551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effd551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575b6899a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (2015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, alig # | ... # `---data was truncated (10240/150641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af162f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af162ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af162f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0004333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f000438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0004333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f000431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af16286bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af16286a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af1626b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af15f1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af15f1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f000431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f000431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f000431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af15f1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (2016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a5197eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a5197be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a5197f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4d2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4d218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4d2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4d211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a51914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a51914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a518f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a515a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a515a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4d211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4d211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4d211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a515a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (2017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca # | ... # `---data was truncated (10240/22898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac9ab5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bac9ab2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bac9ab662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67d731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac9a4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bac9a4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bac9a308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bac96dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bac96dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67d731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac96dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (2018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceaacd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ceaaccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ceaacd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7a9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceaac66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ceaac66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ceaac4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ceaa8fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ceaa8fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceaa8faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (2019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, # | ... # `---data was truncated (10240/24959) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6b7c62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6b7c5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6b7c6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1eb431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6b7bf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6b7bf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6b7bdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6b788ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6b788cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1eb4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6b788ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (2020 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (2021 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (2022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612511c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612511c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612511c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe968849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe968849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe968831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056125115dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056125115da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612511428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561250df1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561250df1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe968832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9688330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561250df1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (2023 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcb4231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcb422ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcb423262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6596449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65964a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6596449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6596431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcb41c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcb41c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcb41ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcb3e5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcb3e5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6596432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65964330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65964330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcb3e5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2024 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cb6128eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cb6125e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cb612962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75c1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75c1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75c1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75c1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cb60bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cb60bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cb60a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cb5d52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cb5d52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75c1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75c1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75c1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cb5d52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (2025 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c582f85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c582f82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c582f8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff090105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff09015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff090105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0900ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c582f1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c582f1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c582f008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c582bafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c582bafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0900eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0900ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0900ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c582bafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (2026 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, p # | ... # `---data was truncated (10240/33198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df251eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df251e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df251eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb117449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb117449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb117431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df25180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df25180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df251658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df24e14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df24e14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb117432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1174330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df24e14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (2027 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 # | ... # `---data was truncated (10240/11237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e60b3e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e60b3e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e60b3e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f1e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e60b37cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e60b37ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e60b3618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e60b010e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e60b010b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e60b010a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-misc.c (2028 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = icmp sge <8 x i8> %1, zeroinitializer # | %vcgez.i = sext <8 x i1> %2 to <8 x i8> # | store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8 # | %3 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %3, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %3 = icmp sge <4 x i16> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %3 = icmp sge <2 x i32> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x i64> # | %3 = icmp sge <1 x i64> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = icmp sge <16 x i8> %1, zeroinitializer # | %vcgez.i = sext <16 x i1> %2 to <16 x i8> # | store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16 # | %3 = load <16 x i8>, ptr %ref.tmp.i, align 16 # | store <16 x i8> %3, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x i16> # | %3 = icmp sge <8 x i16> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x i32> # | %3 = icmp sge <4 x i32> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x i64> # | %3 = icmp sge <2 x i64> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x float> # | %3 = fcmp oge <2 x float> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x double> # | %3 = fcmp oge <1 x double> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fcmp oge <4 x float> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %3 = fcmp oge <2 x double> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, ali # | ... # `---data was truncated (10240/217310) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561c2b89aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c2b897e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c2b89b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f91f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f91f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f91f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f91f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c2b830bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c2b830a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c2b8158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c2b4c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c2b4c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f91f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f91f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f91f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c2b4c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (2029 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x # | ... # `---data was truncated (10240/18674) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f4decceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f4dec9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f4decd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1448505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f144855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1448505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14484ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f4de62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f4de62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f4de478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f4daf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f4daf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14484eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14484ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14484ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f4daf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (2030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593a4afceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593a4af9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593a4afd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f2cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f2cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f2cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f2cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593a4a92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593a4a92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593a4a778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593a4726e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593a4726b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f2cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f2cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f2cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593a4726a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (2031 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056067c580eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056067c57de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056067c58162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f426bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f426bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f426bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f426bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056067c516bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056067c516a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056067c4fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056067c1aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056067c1aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f426bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f426bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f426bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056067c1aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (2032 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619e7afbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619e7af8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619e7afc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b3cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619e7a91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619e7a91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619e7a768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619e7725e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619e7725b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b3cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619e7725a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (2033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f1a2d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f1a2d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f1a2d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfe6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfe658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfe6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfe651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f1a26cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f1a26ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f1a2518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f19f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f19f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfe651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfe651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfe651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f19f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (2034 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056272d655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056272d652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056272d65662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda40333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda4038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda40333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda4031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056272d5ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056272d5eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056272d5d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056272d27fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056272d27fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda4031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda4031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda4031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056272d27fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (2035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618cf136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618cf133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618cf13762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe776d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe776d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe776d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe776ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618cf0ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618cf0cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618cf0b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618ced60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618ced60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe776ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe776cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe776cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618ced60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (2036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570f343aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570f3437e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570f343b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff839333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff83938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff839333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff83931b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570f33d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570f33d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570f33b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570f3064e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570f3064b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff83931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff83931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff83931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570f3064a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (2037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d3c07feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d3c07ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d3c08062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1906649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19066a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1906649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1906631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d3c015bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d3c015a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d3bffa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d3bca9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d3bca9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1906632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19066330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19066330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d3bca9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (2038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (2039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (2040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (2041 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fa5d9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fa5d9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fa5d9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bd6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bd6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bd6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bd6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fa5d34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fa5d34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fa5d198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fa59c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fa59c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bd6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bd6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bd6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fa59c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (2042 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dd21d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559dd21d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559dd21d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8dc831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dd216dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559dd216da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559dd21528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559dd1e01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559dd1e01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8dc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dd1e01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (2043 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636c3966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636c3963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636c396762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdde0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdde038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdde0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdde031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636c38fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636c38fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636c38e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636c3590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636c3590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdde031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdde031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdde031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636c3590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (2044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/18641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a405017eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a405014e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a40501862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7e5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a404fadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a404fada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a404f928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a404c41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a404c41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a404c41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (2045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3595faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3595f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3595fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5534105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f553415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5534105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55340ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e359590bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e359590a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3595758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e359224e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e359224b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55340eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55340ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55340ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e359224a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (2046 of 27910) ******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type { ptr, ptr, %struct.A } # | %struct.A = type { i32 } # | # | $_ZTV1B = comdat any # | # | $_ZTI1B = comdat any # | # | $_ZTS1B = comdat any # | # | $_ZTI1A = comdat any # | # | $_ZTS1A = comdat any # | # | @y = local_unnamed_addr global i8 2, align 1 # | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8 # | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8 # | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8 # | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr] # | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1 # | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8 # | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr] # | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000055d7fabbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7fabb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7fabbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1caa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1caaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1caa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1caa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7fab52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7fab52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7fab378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7fa7e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7fa7e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1caa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1caa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1caa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7fa7e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (2047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (2048 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e173f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e173f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e173f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a23305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a2335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a23305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a232ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e17389bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e17389a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e1736e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e1701de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e1701db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a232eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a232ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a232ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e1701da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (2049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | % # | ... # `---data was truncated (10240/13690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056336fe40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056336fe3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056336fe4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0594649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05946a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0594649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0594631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056336fdd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056336fdd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056336fdbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056336fa6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056336fa6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0594632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05946330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05946330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056336fa6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (2050 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fd6e91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fd6e8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fd6e9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0a2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0a2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0a2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0a2e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fd6e27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fd6e27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fd6e0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fd6abbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fd6abbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0a2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0a2e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0a2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fd6abba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (2051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66314) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056198be3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056198be39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056198be3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4cad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056198bdd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056198bdd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056198bdb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056198ba66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056198ba66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056198ba66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (2052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056160d28beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056160d288e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056160d28c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6772849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67728a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6772849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6772831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160d221bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056160d221a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056160d2068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056160ceb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056160ceb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6772832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67728330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67728330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056160ceb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (2053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564304579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564304576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056430457a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff806249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff806249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff806231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056430450fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056430450fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643044f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643041a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643041a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff806232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8062330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643041a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (2054 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd4245eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd4245be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd4245f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde74e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde74ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde74e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde74e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd423f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd423f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd423d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd42088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd42088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde74e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde74e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde74e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd42088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (2055 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577f3363eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577f3360e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577f336462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4122e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4122ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4122e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4122e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577f32f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577f32f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577f32de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577f2f8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577f2f8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4122e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4122e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4122e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577f2f8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (2056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab7b34aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab7b347e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab7b34b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a3a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a3a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a3a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a3a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab7b2e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab7b2e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab7b2c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab7af74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab7af74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a3a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a3a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a3a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab7af74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (2057 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (2058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (2059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a031c99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a031c96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a031c9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d02a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d02a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d02a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d02a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a031c2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a031c2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a031c148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0318c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0318c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d02a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d02a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d02a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0318c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (2060 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055802147eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055802147be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055802147f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d83d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d83d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d83d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d83ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558021414bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558021414a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580213f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580210a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580210a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d83ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d83cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d83cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580210a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (2061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | # | ... # `---data was truncated (10240/11938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bffa43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557bffa40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557bffa4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5795d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5795d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5795d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5795d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bff9d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557bff9d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557bff9be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557bff66de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557bff66db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5795d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5795d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5795d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bff66da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (2062 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055702ff52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055702ff4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055702ff5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feec1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feec12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feec1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feec1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055702fee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055702fee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055702fecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055702fb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055702fb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feec1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feec12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feec12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055702fb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (2064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %bas # | ... # `---data was truncated (10240/29817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622df778eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622df775e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622df77962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f149fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f149fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f149fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f149fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622df70ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622df70ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622df6f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622df3a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622df3a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f149fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f149fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f149fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622df3a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (2065 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a3e4f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a3e4f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a3e4f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc715e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc715ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc715e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc715e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a3e489bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a3e489a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a3e46e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a3e11de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a3e11db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc715e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc715e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc715e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a3e11da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (2066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056014ef5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056014ef58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056014ef5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38fc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38fc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38fc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38fc231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056014eef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056014eef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056014eed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056014eb85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056014eb85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38fc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38fc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38fc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056014eb85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563056af3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563056af0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563056af462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9129f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9129f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9129f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9129f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563056a89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563056a89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563056a6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056305671de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056305671db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9129f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9129f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9129f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056305671da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (2068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (2069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612013a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056120139fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612013a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f020ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f020baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f020ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f020ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561201338bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561201338a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056120131d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561200fcce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561200fccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f020ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f020ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f020ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561200fcca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (2070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e9dbf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e9dbf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e9dbf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc196049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1960a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc196049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc196031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e9db8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e9db8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e9db738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e9d822e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e9d822b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc196032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1960330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1960330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e9d822a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3df308eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3df305e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3df30962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe14861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1486725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe14861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe148603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3df29ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3df29ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3df2838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3def32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3def32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe148604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1486050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1486050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3def32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2072 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d46379eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d46376e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d4637a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c62333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c6238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c62333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c6231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d4630fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d4630fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d462f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d45fa3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d45fa3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c6231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c6231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c6231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d45fa3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (2073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f95995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f95992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f9599662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde19649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde196a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde19649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde19631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f9592bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f9592ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f959108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f955bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f955bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde19632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde196330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde196330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f955bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (2074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056507ac0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056507ac0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056507ac0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87b2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87b238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87b2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87b231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056507aba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056507aba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056507ab888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056507a837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056507a837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87b231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87b231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87b231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056507a837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (2075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset, i64 no # | ... # `---data was truncated (10240/287205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597e0680eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597e067de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597e068162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca85f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca85f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca85f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca85eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597e0616bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597e0616a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597e05fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597e02aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597e02aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca85eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca85eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca85eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597e02aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (2076 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cc3e5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cc3e5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cc3e5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12a8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12a8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12a8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12a8c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc3df3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cc3df3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cc3dd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cc3a87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cc3a87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f12a8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12a8c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12a8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc3a87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (2077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ec0fc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ec0fc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ec0fc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efef001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efef00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efef001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efef0003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ec0f5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ec0f5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ec0f418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ec0bf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ec0bf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efef0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efef00050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efef00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ec0bf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (2078 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056352249eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056352249be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056352249f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8193933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f819398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8193933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f819391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563522434bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563522434a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635224198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635220c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635220c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f819391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f819391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f819391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635220c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (2079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1f298beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1f2988e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1f298c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f662ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f662ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f662ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f662ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1f2921bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1f2921a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1f29068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1f25b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1f25b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f662ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f662ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f662ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1f25b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv64i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv64i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_ # | ... # `---data was truncated (10240/15323) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560340a92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560340a8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560340a9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f081e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f081e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f081e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f081e203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560340a28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560340a28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560340a0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603406bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603406bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f081e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f081e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f081e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603406bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (2081 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647c81b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647c81b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647c81b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbab4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbab478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbab4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbab471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647c814bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647c814ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647c81308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647c7ddfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647c7ddfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbab471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbab471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbab471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647c7ddfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (2082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb5e62deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb5e62ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb5e62e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ed5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ed5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ed5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ed5c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb5e5c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb5e5c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb5e5a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb5e257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb5e257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ed5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ed5c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ed5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb5e257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (2083 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaa # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056408ae11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056408ae0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056408ae1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb60f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb60f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb60f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb60f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056408ada7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056408ada7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056408ad8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056408aa3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056408aa3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb60f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb60f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb60f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056408aa3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/cx-complex-range.c (2084 of 27910) ******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %coerce.real, ptr %retval.realp, align 4 # | store float %coerce.imag, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__divsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %coerce.real, ptr %.realp1, align 4 # | store float %coerce.imag, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul_ac = fmul float %a.real, %b.real # | %mul_bd = fmul float %a.imag, %b.imag # | %mul_ad = fmul float %a.real, %b.imag # | %mul_bc = fmul float %a.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %real_mul_phi, ptr %retval.realp, align 4 # | store float %imag_mul_phi, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__mulsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul_ac = fmul float %.real, %b.real # | %mul_bd = fmul float %.imag, %b.imag # | %mul_ad = fmul float %.real, %b.imag # | %mul_bc = fmul float %.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %real_mul_phi, ptr %.realp2, align 4 # | store float %imag_mul_phi, ptr %.imagp3, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b = alloca { double, double }, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %2, align 8 # | %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %3, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load doub # | ... # `---data was truncated (10240/29171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055bfd3b27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfd3b24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfd3b2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd41c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd41c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd41c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd41c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfd3abdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfd3abda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfd3aa28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfd3751e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfd3751b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd41c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd41c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd41c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfd3751a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (2085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dba6f19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dba6f16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dba6f1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff104f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff104f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff104f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff104f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dba6eafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dba6eafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dba6e948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dba6b43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dba6b43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff104f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff104f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff104f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dba6b43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (2086 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557df496aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557df4967e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557df496b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe263f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe263f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe263f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe263f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557df4900bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557df4900a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557df48e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557df4594e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557df4594b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe263f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe263f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe263f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557df4594a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, # | ... # `---data was truncated (10240/29451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056320cc5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056320cc5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056320cc5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04cd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056320cbf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056320cbf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056320cbd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056320c887e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056320c887b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056320c887a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (2088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056251819aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562518197e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056251819b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50aea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50aea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50aea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50aea03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562518130bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562518130a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625181158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562517dc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562517dc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50aea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50aea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50aea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562517dc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2089 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603a3916eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603a3913e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603a391762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f2e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f2e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f2e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f2e031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603a38acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603a38aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603a38918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603a3540e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603a3540b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f2e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f2e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f2e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603a3540a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (2090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555864047eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555864044e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055586404862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa09a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa09a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa09a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa09a603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555863fddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555863fdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555863fc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555863c71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555863c71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa09a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa09a6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa09a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555863c71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (2091 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 # | ... # `---data was truncated (10240/29175) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d881e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d881e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d881ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4577649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45776a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4577649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4577631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d8817fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d8817fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d881648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d87e13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d87e13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4577632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45776330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45776330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d87e13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (2092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd78866eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd78863e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd7886762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcea91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd787fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd787fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd787e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd78490e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd78490b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efcea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcea91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd78490a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (2093 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3) # | %5 = and <8 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3) # | %5 = and <4 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3) # | %5 = and <2 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3) # | %5 = and <16 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = xor i16 %0, -1 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = load <8 x half>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = load <4 x float>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <2 x i64>, ptr %a.addr, align 8 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | %5 = load <2 x i64>, ptr %b.addr, align 8 # | %6 = bitcast <2 x i64> %5 to <4 x i32> # | %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6 # | %8 = bitcast <4 x i32> %7 to <2 x i64> # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, ali # | ... # `---data was truncated (10240/13928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000556c40641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c4063ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c4064262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aaaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aaaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aaaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aaaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c405d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c405d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c405bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c4026be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c4026bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9aaaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aaaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aaaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c4026ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (2094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdd9f91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdd9f8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdd9f9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f216ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f216ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f216ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdd9f27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdd9f27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdd9f0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdd9bbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdd9bbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f216ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f216ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f216ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdd9bbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (2095 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624826c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624826c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624826c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87f6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87f6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87f6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87f6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562482659bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562482659a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056248263e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624822ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624822edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87f6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87f6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87f6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624822eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (2096 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f4ab22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f4ab1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f4ab2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f4aab8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f4aab8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f4aa9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f4a74ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f4a74cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15f9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f4a74ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (2097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (2098 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d1f47beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d1f478e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d1f47c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bb8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bb858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bb8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bb851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d1f411bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d1f411a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d1f3f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d1f0a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d1f0a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0bb851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bb851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bb851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d1f0a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (2099 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad2cb01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad2cafee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad2cb0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cf9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cf92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cf9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cf9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad2ca97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad2ca97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad2ca7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad2c72be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad2c72bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cf9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cf92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cf92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad2c72ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (2100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (2101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcf049feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcf049ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcf04a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd25e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd25e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd25e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd25e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcf0435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcf0435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcf041a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcf00c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcf00c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd25e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd25e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd25e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcf00c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (2102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613851adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613851aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613851ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e81a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e81aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e81a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e81a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561385143bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561385143a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613851288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561384dd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561384dd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e81a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e81a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e81a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561384dd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (2103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/11969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556bb86ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556bb869e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556bb86d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa175305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa17535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa175305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1752ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556bb802bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556bb802a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556bb7e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556bb496e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556bb496b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1752eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1752ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1752ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556bb496a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (2104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608aa689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608aa686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608aa68a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb339533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb33958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb339533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb33951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608aa61fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608aa61fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608aa6048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608aa2b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608aa2b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb33951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb33951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb33951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608aa2b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (2105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (2106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb071bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb071b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb071bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddbdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddbdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddbdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddbdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb07152bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb07152a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb071378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb06de6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb06de6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddbdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddbdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddbdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb06de6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (2107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (2108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe7bdf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe7bdf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe7bdf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ca7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ca72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ca7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ca7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe7bd8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe7bd8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe7bd728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe7ba21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe7ba21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ca7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ca72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ca72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe7ba21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (2109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615235aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615235a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615235ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc51dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc51dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc51dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc51dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561523542bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561523542a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615235278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615231d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615231d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc51dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc51dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc51dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615231d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (2110 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e62a29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e62a26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e62a2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a62f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a62f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a62f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a62f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e629bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e629bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e629a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e62653e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e62653b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a62f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a62f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a62f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e62653a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c5aa74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c5aa71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c5aa7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f77b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f77b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f77b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f77b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c5aa0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c5aa0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c5a9ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c5a69ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c5a69eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f77b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f77b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f77b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c5a69ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (2112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056422811beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564228118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056422811c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc385849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc385849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc385831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642280b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642280b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642280968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564227d45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564227d45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc385832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3858330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564227d45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (2113 of 27910) ******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load bfloat, ptr %a.addr, align 2 # | %fpext = fpext bfloat %0 to float # | %fptrunc = fptrunc float %fpext to half # | ret half %fptrunc # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %fpext = fpext half %0 to float # | %fptrunc = fptrunc float %fpext to bfloat # | ret bfloat %fptrunc # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592c20abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592c20a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592c20ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6323533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f632358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6323533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f632351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c2041bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592c2041a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592c20268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592c1cd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592c1cd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f632351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f632351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f632351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c1cd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (2114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fce2e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fce2e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fce2e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29f4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29f48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29f4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29f4831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fce27abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fce27aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fce25f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fcdf0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fcdf0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29f4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29f48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29f48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fcdf0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (2115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560af3d7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560af3d7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560af3d7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1124133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f112418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1124133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f112411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560af3d13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560af3d13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560af3cf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560af39a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560af39a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f112411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f112411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f112411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560af39a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (2116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6ebbafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6ebbace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6ebbb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febfb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febfb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febfb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febfb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6ebb45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6ebb45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6ebb2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6eb7d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6eb7d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febfb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febfb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febfb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6eb7d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2117 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp ule <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp ule <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp ule <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645321a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645321a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645321a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f660721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66072725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f660721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6607203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056453213bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056453213ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645321208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564531dcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564531dcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6607204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66072050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66072050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564531dcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (2118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv. # | ... # `---data was truncated (10240/17879) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2cd0e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2cd0e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2cd0e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4098e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4098ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4098e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4098e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2cd07abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2cd07aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2cd05f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2ccd0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2ccd0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4098e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4098e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4098e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2ccd0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-neon-fma.c (2119 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-none-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %accum.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %accum, ptr %accum.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %accum.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %accum.addr = alloca <4 x float>, align 8 # | %lhs.addr = alloca <4 x float>, align 8 # | %rhs.addr = alloca <4 x float>, align 8 # | store <4 x float> %accum, ptr %accum.addr, align 8 # | store <4 x float> %lhs, ptr %lhs.addr, align 8 # | store <4 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x float>, ptr %accum.addr, align 8 # | %1 = load <4 x float>, ptr %lhs.addr, align 8 # | %2 = load <4 x float>, ptr %rhs.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store <4 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %10, ptr %__ret.i, align 8 # | %11 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <2 x float>, align 8 # | %__p1.addr.i.i = alloca <2 x float>, align 8 # | %__p2.addr.i.i = alloca <2 x float>, align 8 # | %__ret.i.i = alloca <2 x float>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | store <2 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <2 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <2 x float> %7, ptr %__p2.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %11 = bitcast <8 x i8> %8 to <2 x float> # | %12 = bitcast <8 x i8> %9 to <2 x float> # | %13 = bitcast <8 x i8> %10 to <2 x float> # | %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11) # | store <2 x float> %14, ptr %ref.tmp.i.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8 # | store <2 x float> %15, ptr %__ret.i.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i.i, align 8 # | store <2 x float> %16, ptr %__ret.i, align 8 # | %17 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x float>, align 8 # | %__p1.addr.i.i = alloca <4 x float>, align 8 # | %__p2.addr.i.i = alloca <4 x float>, align 8 # | %__ret.i.i = alloca <4 x float>, align 8 # | %ref.tmp.i.i = alloca <16 x i8>, align 8 # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 8 # | %.compoundliteral.i = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 8 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <4 x float> %9, ptr %__p2.addr.i.i, align 8 # | %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8 # | %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8 # | %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8 # | %13 = bitcast <16 x i8> %10 to <4 x float> # | %14 = bitcast <16 x i8> %11 to <4 x float> # | %15 = bitcast <16 x i8> %12 to <4 x float> # | %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13) # | store <4 x float> %16, ptr %ref.tmp.i.i, align 8 # | %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8 # | store <4 x float> %17, ptr %__ret.i.i, align 8 # | %18 = load <4 x float>, ptr %__ret.i.i, align 8 # | store <4 x float> %18, ptr %__ret.i, align 8 # | %19 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %19 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055cbf22a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbf22a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbf22a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f576d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f576d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbf223bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbf223ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbf22208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbf1ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbf1ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f576d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbf1ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (2120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056084f838eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056084f835e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056084f83962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9abf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9abf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9abf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9abf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056084f7cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056084f7cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056084f7b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056084f462e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056084f462b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9abf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9abf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9abf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084f462a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (2121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29128) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f288c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f288c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f288c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e13c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e13c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e13c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e13c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f2885abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f2885aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f2883f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f284eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f284eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e13c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e13c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e13c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f284eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (2122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a29d8aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a29d8abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a29d8af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f6be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f6bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f6be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f6be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a29d844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a29d844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a29d8298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a29d4d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a29d4d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f6be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f6be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f6be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a29d4d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (2123 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp uge <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp uge <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp uge <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5d7c50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5d7c4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5d7c5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6c951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5d7be6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a5d7be6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5d7bcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5d787ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5d787ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6c951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5d787aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2124 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -252) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 -243) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 195) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 8978432) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 { # | entry: # | ret <8 x i16> splat (i16 27391) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 { # | entry: # | ret <4 x i32> splat (i32 -5570561) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 { # | entry: # | ret <8 x i16> splat (i16 -18689) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 { # | entry: # | ret <4 x i32> splat (i32 1023410175) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -11265) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -13893633) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -37) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -1644167169) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 13568) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 654311424) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 175) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 89) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %inactive.addr, align 8 # | %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> % # | ... # `---data was truncated (10240/13125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590d6fc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005590d6fc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005590d6fc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b7ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b7ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b7ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b7eeed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590d6f59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005590d6f59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590d6f3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005590d6bede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005590d6bedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b7eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b7eeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b7eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590d6beda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (2125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/26984) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cae179ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cae1799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cae179d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52ea705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52ea75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52ea705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52ea6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cae1732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cae1732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cae17178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cae13c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cae13c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52ea6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52ea6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52ea6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cae13c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2ae318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2ae315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2ae31962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7ba21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7ba2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7ba21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7ba203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2ae2aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2ae2aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2ae2938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2adf42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2adf42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7ba204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7ba2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7ba2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2adf42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (2127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bd0fbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bd0fb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bd0fbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe64b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe64b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe64b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe64b231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bd0f51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bd0f51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bd0f368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bd0be5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bd0be5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe64b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe64b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe64b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bd0be5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (2128 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 # | ... # `---data was truncated (10240/35980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055ef0a277eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef0a274e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef0a27862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6e2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6e2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6e2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6e2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef0a20dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef0a20da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef0a1f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef09ea1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef09ea1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6e2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6e2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6e2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef09ea1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (2129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575afe71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575afe6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575afe7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f764a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f764a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f764a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f764a003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575afe07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575afe07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575afdec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575afa9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575afa9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f764a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f764a0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f764a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575afa9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (2130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560d7402eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560d73ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560d740362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f928361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92836725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f928361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9283603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560d7398bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560d7398a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560d737d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560d702ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560d702cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9283604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92836050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92836050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560d702ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (2131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (2132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/126428) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbfc5c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbfc5bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbfc5c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e44d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e44d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e44d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e44d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbfc556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbfc556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbfc53b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbfc1eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbfc1eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e44d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e44d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e44d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbfc1eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (2133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055863d587eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055863d584e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055863d58862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd129849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd129849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd129831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055863d51dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055863d51da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055863d5028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055863d1b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055863d1b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd129832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1298330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055863d1b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2134 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c215117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c215114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c21511862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2218449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22184a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2218449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2218431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2150adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2150ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2150928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c214d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c214d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2218432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22184330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22184330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c214d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (2135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d6e78deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d6e78ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d6e78e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1eaaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1eaaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1eaaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1eaaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d6e723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d6e723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d6e7088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d6e3b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d6e3b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1eaaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1eaaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1eaaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d6e3b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (2136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e5e786eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e5e783e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e5e78762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f503ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f503aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f503ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f503ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e5e71cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e5e71ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e5e7018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e5e3b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e5e3b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f503ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f503ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f503ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e5e3b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (2137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr % # | ... # `---data was truncated (10240/29809) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d9e016eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d9e013e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d9e01762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2a831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d9dfacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d9dfaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d9df918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d9dc40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d9dc40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe2a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2a831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d9dc40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (2138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (2139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv # | ... # `---data was truncated (10240/83637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586aa3f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586aa3eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586aa3f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1bc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1bc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1bc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1bc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586aa387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586aa387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586aa36c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586aa01be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586aa01bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1bc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1bc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1bc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586aa01ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (2140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559793fa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559793fa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559793faa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2138533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f213858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2138533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f213851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559793f3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559793f3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559793f248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559793bd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559793bd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f213851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f213851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f213851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559793bd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2141 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560190a6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560190a67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560190a6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f5d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f5d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f5d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f5d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560190a00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560190a00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601909e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560190694e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560190694b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f5d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f5d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f5d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560190694a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (2142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559344b63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559344b60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559344b6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7076133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f707618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7076133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f707611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559344af9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559344af9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559344ade8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055934478de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055934478db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f707611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f707611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f707611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055934478da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (2143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637755f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637755f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637755f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71a971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056377558cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056377558ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637755718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563775220e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563775220b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71a971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563775220a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (2144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6020a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a60209ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6020a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f053e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f053e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f053e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f053e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a602037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a602037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a60201c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a601ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a601ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f053e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f053e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f053e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a601ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (2145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560339090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056033908de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056033909162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa929533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa92958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa929533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa92951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560339026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560339026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056033900b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560338cbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560338cbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa92951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa92951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa92951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560338cbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (2146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (2147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9b30daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9b30d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9b30db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30c6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30c6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30c6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30c6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9b3070bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9b3070a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9b30558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9b2d04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9b2d04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f30c6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30c6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30c6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9b2d04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (2148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598dbb26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598dbb23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598dbb2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2d4631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598dbabcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598dbabca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598dbaa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598db750e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598db750b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2d46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598db750a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (2149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562850bbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562850bb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562850bbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56fa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56fa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56fa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56fa51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562850b51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562850b51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562850b368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628507e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628507e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56fa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56fa51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56fa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628507e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (2150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llv # | ... # `---data was truncated (10240/20513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055793cb0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055793cb0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055793cb0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f571b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f571b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f571b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f571b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055793caa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055793caa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055793ca898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055793c738e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055793c738b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f571b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f571b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f571b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055793c738a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628d4f80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628d4f7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628d4f8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9a3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9a3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9a3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9a3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628d4f16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628d4f16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628d4efb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628d4baae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628d4baab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9a3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9a3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9a3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628d4baaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (2152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3e3118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3e3115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3e311962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83c001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83c00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83c001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83c0003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3e30aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3e30aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3e30938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3e2d42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3e2d42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83c0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83c00050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83c00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3e2d42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (2153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616f275ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616f2759e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616f275d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e38f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616f26f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616f26f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616f26d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616f2386e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616f2386b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616f2386a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/packed-structure.c (2154 of 27910) ******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | %struct.s0 = type { i32, i32 } # | %struct.s1 = type { i32, i32 } # | %struct.s2 = type { i32, i32 } # | %struct.s3 = type <{ i16, i32, [10 x i8] }> # | # | @s0_align_x = global i32 4, align 4 # | @s0_align_y = global i32 1, align 4 # | @s0_align = global i32 4, align 4 # | @s1_align_x = global i32 1, align 4 # | @s1_align_y = global i32 1, align 4 # | @s1_align = global i32 1, align 4 # | @s2_align_x = global i32 2, align 4 # | @s2_align_y = global i32 2, align 4 # | @s2_align = global i32 2, align 4 # | @s3_1 = global i32 1, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @test3(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %anInt, align 2 # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # | #0 0x0000556d98f73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d98f70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d98f7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bc1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bc1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bc1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bc1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d98f09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d98f09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d98eee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d98b9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d98b9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bc1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bc1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bc1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d98b9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (2155 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af997e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af997dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af997e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7490d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7490d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7490d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7490d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af99776bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af99776a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af9975b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af9940ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af9940ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7490d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7490d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7490d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9940aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (2156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (2157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect # | ... # `---data was truncated (10240/32932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056249c838eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056249c835e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056249c83962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ac9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ac9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ac9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ac9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056249c7cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056249c7cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056249c7b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056249c462e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056249c462b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ac9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ac9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ac9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056249c462a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (2158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575a9e8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575a9e8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575a9e8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0417533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f041758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0417533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f041751b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575a9e23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575a9e23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575a9e088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575a9ab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575a9ab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f041751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f041751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f041751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575a9ab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (2159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b780ef3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b780ef0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b780ef462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6836449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6836449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6836431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b780e89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b780e89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b780e6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b780b1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b780b1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6836432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b780b1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (2160 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9d525deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9d525ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9d525e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10b3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10b3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10b3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10b3eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9d51f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9d51f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9d51d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9d4e87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9d4e87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10b3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10b3eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10b3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9d4e87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (2161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/13581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b14624eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b14621e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b1462562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b82133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b8218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b82133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b8211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b145babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b145baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b1459f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b1424ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b1424eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b8211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b8211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b8211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b1424ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (2162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577afe2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577afe2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577afe3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f545a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f545a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f545a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f545a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577afdc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577afdc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577afdaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577afa59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577afa59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f545a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f545a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f545a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577afa59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (2163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577b2cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577b2ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577b2cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e33649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e336a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e33649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e33631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577b2c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577b2c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577b2c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577b28fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577b28fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e33632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e336330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e336330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577b28faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056268ce83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056268ce80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056268ce8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb666e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb666ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb666e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb666e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056268ce19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056268ce19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056268cdfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056268caade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056268caadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb666e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb666e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb666e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056268caada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (2166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/135345) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556930eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556930e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556930ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8500105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f850015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8500105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85000ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555693082bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555693082a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556930678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555692d16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555692d16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85000eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85000ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85000ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555692d16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (2167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561505927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561505924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056150592862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe218933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe21898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe218933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe21891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615058bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615058bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615058a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561505551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561505551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe21891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe21891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe21891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561505551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (2168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (2169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee4c2e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee4c2dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee4c2e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b58249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b58249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b58231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee4c276bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee4c276a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee4c25b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee4bf0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee4bf0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b58232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b582330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee4bf0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (2170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (2171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597a55e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597a55e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597a55e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f546d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f546d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f546d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f546d631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597a557abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597a557aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597a555f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597a520ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597a520eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f546d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f546d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f546d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597a520ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a243ecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a243ecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a243ece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feff8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feff8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feff8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feff8ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a243e63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a243e63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a243e488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a243af7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a243af7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feff8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feff8cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feff8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a243af7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c564bbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c564bb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c564bbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8800e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8800ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8800e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8800e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c564b51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c564b51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c564b368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5647e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5647e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8800e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8800e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8800e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5647e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (2174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dbfbbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555dbfbbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555dbfbc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25fb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25fb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25fb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25fb603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dbfb55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555dbfb55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555dbfb3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dbf7e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dbf7e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25fb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25fb6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25fb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dbf7e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (2175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056515999eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056515999be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056515999f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ef0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ef018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ef0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ef011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565159934bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565159934a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651599198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651595c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651595c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ef011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ef011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ef011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651595c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (2176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6846d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6846d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6846da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e9cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e9cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e9cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e9cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d68466fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d68466fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6846548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d684303e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d684303b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e9cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e9cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e9cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d684303a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (2177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae006bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae006b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae006bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a28f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a28f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a28f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a28eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae00651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae00651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae006368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae002e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae002e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a28eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a28eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a28eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae002e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (2178 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055713a6b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055713a6b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055713a6ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5907a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5907aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5907a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5907a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055713a64fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055713a64fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055713a6348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055713a2e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055713a2e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5907a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5907a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5907a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055713a2e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (2180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056404a07ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056404a079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056404a07d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f381cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f381cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f381cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f381cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056404a012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056404a012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564049ff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564049ca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564049ca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f381cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f381cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f381cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564049ca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (2181 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056089b698eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056089b695e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056089b69962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33a7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33a70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33a7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33a7031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056089b62ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056089b62ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056089b6138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056089b2c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056089b2c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33a7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33a70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33a70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056089b2c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (2182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c099b68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c099b65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c099b6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cb2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cb238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cb2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cb231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c099afebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c099afea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c099ae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c099792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c099792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cb231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cb231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cb231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c099792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (2183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639b707ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639b7079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639b707d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17b5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17b598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17b5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17b591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639b7012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639b7012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639b6ff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639b6ca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639b6ca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17b591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17b591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17b591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639b6ca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (2184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4dbbedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4dbbeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4dbbee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7cc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7cc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7cc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7cc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4dbb83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4dbb83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4dbb688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4db817e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4db817b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7cc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7cc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7cc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4db817a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (2185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0fdcc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0fdcc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0fdcc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b27e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b27ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b27e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b27e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0fdc5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0fdc5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0fdc408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0fd8efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0fd8efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b27e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b27e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b27e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0fd8efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (2186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (2187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d0c3ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d0c3dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d0c3de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5af8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5af838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5af8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5af831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d0c373bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d0c373a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d0c3588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d0c007e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d0c007b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5af831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5af831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5af831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d0c007a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (2188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055720845feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055720845ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055720846062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f819a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f819a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f819a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f819a431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572083f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572083f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572083da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557208089e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557208089b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f819a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f819a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f819a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557208089a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (2189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6a217feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6a217ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6a218062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f053f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f053f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f053f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f053f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6a2115bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6a2115a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6a20fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6a1da9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6a1da9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f053f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f053f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f053f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6a1da9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (2190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.a # | ... # `---data was truncated (10240/63518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616b07e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616b07e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616b07e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9567f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9567f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9567f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9567f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616b077cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616b077ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616b07618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616b0410e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616b0410b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9567f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9567f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9567f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616b0410a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (2191 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | # | ... # `---data was truncated (10240/19123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d35f356eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d35f353e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d35f35762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0062e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0062e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0062e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0062e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d35f2ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d35f2eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d35f2d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d35ef80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d35ef80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0062e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0062e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0062e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d35ef80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (2192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2eb7c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2eb7c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2eb7c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4919533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f491958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4919533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f491951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2eb75cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2eb75ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2eb7418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2eb3f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2eb3f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f491951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f491951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f491951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2eb3f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (2193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (2194 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580f7087eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580f7084e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580f708862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfd8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfd88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfd8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfd8831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580f701dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005580f701da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580f70028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580f6cb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580f6cb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfd8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfd88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfd88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580f6cb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (2195 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8dce4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d8dce48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8dce4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fa8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fa898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fa8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fa891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8dcde1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8dcde1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8dcdc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8dca75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8dca75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fa891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fa891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fa891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8dca75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (2196 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568e43adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568e43aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568e43ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f09733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f0978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f09733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f0971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568e4343bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568e4343a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568e43288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568e3fd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568e3fd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f0971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f0971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f0971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568e3fd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (2197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b6d739eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b6d736e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b6d73a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4028b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4028b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4028b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4028b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b6d6cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b6d6cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b6d6b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b6d363e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b6d363b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4028b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4028b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4028b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b6d363a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (2198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d6cde7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d6cde4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d6cde862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f917901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91790725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f917901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9179003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d6cd7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d6cd7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d6cd628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d6ca11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d6ca11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9179004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91790050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91790050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d6ca11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647c7df2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647c7defe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647c7df362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb744b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb744b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb744b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb744b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647c7d88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647c7d88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647c7d6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647c7a1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647c7a1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb744b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb744b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb744b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647c7a1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2200 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b9eb0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b9eb0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b9eb0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3359b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3359b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3359b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3359b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b9eaa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b9eaa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b9ea898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b9e738e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b9e738b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3359b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3359b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3359b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b9e738a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (2201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcaa1a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcaa1a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcaa1a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe962933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe96298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe962933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe96291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcaa13bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcaa13ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcaa1208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dca9dcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dca9dcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe96291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe96291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe96291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dca9dcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (2202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c82f2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c82f2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c82f2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac92849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac928a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac92849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac92831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c82ec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c82ec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c82ea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c82b57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c82b57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac92832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac928330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac928330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c82b57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (2203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue # | ... # `---data was truncated (10240/81764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba6386aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba63867e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba6386b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f16b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f16b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f16b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f16b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba63800bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba63800a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba637e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba63494e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba63494b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f16b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f16b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f16b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba63494a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (2204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640a21fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640a21f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640a21fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32ecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32ecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32ecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32ecc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640a2191bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640a2191a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640a21768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640a1e25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640a1e25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32ecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32ecc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32ecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640a1e25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2205 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.1a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %c.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | %2 = load <8 x i16>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | store <8 x i16> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %6, ptr %__ret.i, align 16 # | %7 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %c.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | %2 = load <4 x i32>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | store <4 x i32> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32> # | %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32> # | %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32> # | %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i) # | %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | %__ret_140 = alloca <4 x i16>, align 8 # | %__s0_140 = alloca <4 x i16>, align 8 # | %__s1_140 = alloca <4 x i16>, align 8 # | %__s2_140 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_140, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_140, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %2, ptr %__s2_140, align 8 # | %3 = load <4 x i16>, ptr %__s0_140, align 8 # | %4 = load <4 x i16>, ptr %__s1_140, align 8 # | %5 = load <4 x i16>, ptr %__s2_140, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_140, align 8 # | %16 = load <4 x i16>, ptr %__ret_140, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr # | ... # `---data was truncated (10240/38786) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x000055b4becffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4becfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4bed0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc31d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4bec95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4bec95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4bec7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4be929e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4be929b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4be929a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (2206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fa5fcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fa5fcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fa5fce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f95b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f95b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f95b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f95b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fa5f63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fa5f63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fa5f488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fa5bf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fa5bf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f95b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f95b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f95b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fa5bf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (2207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ca823aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ca8237e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ca823b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd711533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd71158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd711533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd71151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ca81d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ca81d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ca81b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ca7e64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ca7e64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd71151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd71151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd71151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ca7e64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (2208 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578c8a45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578c8a42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578c8a4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578c89dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578c89dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578c89c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578c866fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578c866fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578c866fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (2209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557708ee8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557708ee5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557708ee962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f293a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f293a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f293a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f293a431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557708e7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557708e7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557708e638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557708b12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557708b12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f293a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f293a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f293a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557708b12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (2210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556672121eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055667211ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055667212262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddd6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddd62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddd6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddd6231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566720b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566720b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055667209c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556671d4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556671d4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddd6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddd62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddd62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556671d4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (2211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call < # | ... # `---data was truncated (10240/66998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055665c444eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055665c441e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055665c44562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8690933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f869098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8690933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f869091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055665c3dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055665c3daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055665c3bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055665c06ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055665c06eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f869091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f869091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f869091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055665c06ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (2212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vas # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fb01b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fb01aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fb01b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8536d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8536d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8536d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8536ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fb0147bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fb0147a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fb012c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fafddbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fafddbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8536ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8536cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8536cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fafddba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (2213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , al # | ... # `---data was truncated (10240/13263) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565ff00aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565ff007e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565ff00b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f390d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f390d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f390d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f390d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565fefa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565fefa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565fef858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565fec34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565fec34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f390d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f390d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f390d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565fec34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (2214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7230f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7230f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7230f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78c4705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78c475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78c4705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78c46ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a72308dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a72308da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7230728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a722d21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a722d21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78c46eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78c46ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78c46ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a722d21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (2215 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b777cb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b777cade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b777cb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8498333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f849838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8498333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f849831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b777c46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b777c46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b777c2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7778dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7778dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f849831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f849831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f849831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7778daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (2216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbaadc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbaadbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbaadc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9c6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9c6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9c6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9c6a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbaad57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbaad57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbaad3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbaa9ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbaa9ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9c6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9c6a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9c6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbaa9eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (2217 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056262bd53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056262bd50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056262bd5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9837849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98378a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9837849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9837831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262bce9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056262bce9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056262bcce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056262b97de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056262b97db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9837832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98378330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98378330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262b97da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (2219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e3cf04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e3cf01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e3cf0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa38b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa38b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa38b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa38b403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e3ce9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e3ce9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e3ce7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e3cb2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e3cb2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa38b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa38b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa38b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e3cb2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (2220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | ... # `---data was truncated (10240/30866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631d3a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631d3a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631d3a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f96249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f96249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f96231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631d3a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631d3a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631d3a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631d36b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631d36b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f96232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f962330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631d36b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (2221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op # | ... # `---data was truncated (10240/154517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056290190eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056290190be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056290190f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaeec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaeeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaeec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaeec31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629018a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629018a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629018898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562901538e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562901538b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaeec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaeec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaeec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562901538a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (2222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556daa26eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556daa26be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556daa26f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76d0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556daa204bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556daa204a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556daa1e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556da9e98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556da9e98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556da9e98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (2223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056203d8aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056203d8abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056203d8af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba9f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba9f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba9f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba9f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056203d844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056203d844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056203d8298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056203d4d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056203d4d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba9f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba9f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba9f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056203d4d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (2224 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x half>, ptr %0, align 2 # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x float>, ptr %0, align 4 # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i8>, ptr %0, align 1 # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i8>, ptr %0, align 1 # | %2 = sext <4 x i8> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = a # | ... # `---data was truncated (10240/50873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b9dfdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b9dfdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b9dfe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22ff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22ff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22ff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22ff31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b9df75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b9df75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b9df5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b9dc09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b9dc09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22ff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22ff31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22ff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b9dc09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (2225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558272923eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558272920e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055827292462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06f2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06f278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06f2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06f271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582728b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582728b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055827289e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055827254de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055827254db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06f271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06f271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06f271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055827254da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (2226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("risc # | ... # `---data was truncated (10240/14659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652ab581eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652ab57ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652ab58262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2131e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2131ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2131e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2131e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652ab517bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652ab517a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652ab4fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652ab1abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652ab1abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2131e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2131e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2131e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652ab1aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (2227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055921dffeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055921dffbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055921dfff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8282533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f828258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8282533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f828251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055921df94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055921df94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055921df798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055921dc28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055921dc28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f828251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f828251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f828251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055921dc28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (2228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c186146eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c186143e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c18614762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e0c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e0c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e0c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e0c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1860dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1860dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1860c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c185d70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c185d70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e0c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e0c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e0c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c185d70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (2229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7a9927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7a9924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7a992862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e6c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e6c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e6c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e6c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7a98bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7a98bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7a98a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7a9551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7a9551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e6c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e6c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e6c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7a9551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (2230 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nounwind } # | attributes #2 = { nounwind memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f64146eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f64143e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f6414762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ab7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ab798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ab7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ab791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f640dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f640dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f640c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f63d70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f63d70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ab791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ab791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ab791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f63d70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (2231 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5) # | %7 = extractvalue { i32, <4 x i32> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <4 x i32> } %6, 1 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | # | ... # `---data was truncated (10240/11454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056416ad65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056416ad62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056416ad6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf88f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf88f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf88f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf88f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056416acfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056416acfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056416ace08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056416a98fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056416a98fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf88f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf88f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf88f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056416a98fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fd1d5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fd1d5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fd1d5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde3d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde3d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde3d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde3d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fd1cf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fd1cf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fd1cd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fd1987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fd1987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde3d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde3d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde3d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fd1987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (2233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (2234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load < # | ... # `---data was truncated (10240/84810) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d260f61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d260f5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d260f6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae7951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d260ef7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d260ef7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d260edc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d260b8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d260b8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae7951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d260b8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (2235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622862b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622862afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622862b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8393333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f839338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8393333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f839331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562286248bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562286248a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056228622d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562285edce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562285edcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f839331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f839331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f839331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562285edca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (2236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6064bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6064bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6064c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff08ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c606455bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c606455a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c60643a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6060e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6060e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ff08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff08ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6060e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (2237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c674aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c674a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c674ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb77ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb77eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb77ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb77ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c67440bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c67440a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c674258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c670d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c670d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb77ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb77ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb77ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c670d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d446e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d446e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d446e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47c571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d4467dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d4467da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d446628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d44311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d44311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47c571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d44311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (2239 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fda61a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fda61a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fda61aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd482449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4824a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd482449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd482431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fda613fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fda613fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fda61248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fda5dd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fda5dd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd482432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4824330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4824330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fda5dd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2241 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f74a8e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f74a8e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f74a8e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16f5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16f5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16f5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16f5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f74a87bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f74a87ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f74a8608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f74a50fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f74a50fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16f5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16f5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16f5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f74a50fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (2242 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # | #0 0x00005598b7181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598b717ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598b718262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4226c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4226ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4226c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4226c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598b7117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598b7117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598b70fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598b6dabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598b6dabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4226c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4226c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4226c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598b6daba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (2243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604d48f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005604d48eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005604d48f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe69ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe69ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe69ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe69ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604d4887bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604d4887a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604d486c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604d451be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604d451bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe69ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe69ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe69ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604d451ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (2244 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abd67efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abd67ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abd67f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedab631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abd6785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abd6785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abd676a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abd6419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abd6419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fedab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedab6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abd6419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ca7401eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ca73fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ca740262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe38e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe38e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe38e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe38e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ca7397bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ca7397a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ca737c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ca702be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ca702bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe38e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe38e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe38e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ca702ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (2246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce1a211eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce1a20ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce1a21262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad9dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad9dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad9dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad9dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce1a1a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce1a1a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce1a18c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce19e3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce19e3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad9dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad9dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad9dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce19e3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (2247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556881b0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556881b07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556881b0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04f2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04f238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04f2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04f231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556881aa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556881aa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556881a858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556881734e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556881734b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04f231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04f231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04f231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556881734a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (2248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (2249 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <8 x half> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <4 x float> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ba5c2e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba5c2e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba5c2e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5606933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f560698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5606933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f560691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba5c27ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba5c27ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba5c2638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba5bf12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba5bf12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f560691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f560691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f560691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba5bf12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (2250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b6d7a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b6d7a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b6d7a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9c4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b6d73dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b6d73da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b6d7228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b6d3d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b6d3d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9c4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b6d3d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (2251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fe85fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fe85f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fe85fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0520d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0520d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0520d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0520d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fe8591bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fe8591a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fe85768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fe8225e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fe8225b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0520d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0520d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0520d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fe8225a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (2252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (2253 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560ab52aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560ab527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560ab52b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac74b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac74b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac74b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac74b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560ab4c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560ab4c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560ab4a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560ab154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560ab154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac74b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac74b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac74b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560ab154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (2254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea80eb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea80eb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea80eb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58c1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58c1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58c1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58c1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea80e4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea80e4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea80e308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea80adfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea80adfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58c1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58c1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58c1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea80adfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (2255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d3fa1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d3fa1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d3fa2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feec3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feec34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feec3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feec3431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d3f9b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d3f9b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d3f99a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d3f649e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d3f649b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feec3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feec34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feec34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d3f649a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (2256 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Functi # | ... # `---data was truncated (10240/116949) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cd1136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cd1133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cd113762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e8d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e8d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e8d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e8d603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cd10ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cd10cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cd10b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cd0d60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cd0d60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e8d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e8d6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e8d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cd0d60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (2257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (2258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/164791) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056282f2afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056282f2ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056282f2b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c69333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c6938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c69333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c6931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056282f245bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056282f245a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056282f22a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056282eed9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056282eed9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c6931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c6931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c6931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056282eed9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm_acle.c (2259 of 27910) ******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dmb() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dsb() #0 { # | entry: # | call void @llvm.arm.dsb(i32 2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_isb() #0 { # | entry: # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pld() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pldx() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pli() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_plix() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 32 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i32, ptr %__x.addr.i, align 4 # | store i32 %4, ptr %retval.i, align 4 # | br label %__ror.exit # | # | if.end.i: ; preds = %entry # | %5 = load i32, ptr %__x.addr.i, align 4 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %shr.i = lshr i32 %5, %6 # | %7 = load i32, ptr %__x.addr.i, align 4 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 32, %8 # | %shl.i = shl i32 %7, %sub.i # | %or.i = or i32 %shr.i, %shl.i # | store i32 %or.i, ptr %retval.i, align 4 # | br label %__ror.exit # | # | __ror.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i32, ptr %retval.i, align 4 # | ret i32 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i.i = alloca i32, align 4 # | %__x.addr.i.i = alloca i32, align 4 # | %__y.addr.i.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | store i32 %2, ptr %__x.addr.i.i, align 4 # | store i32 %3, ptr %__y.addr.i.i, align 4 # | %4 = load i32, ptr %__y.addr.i.i, align 4 # | %rem.i.i = urem i32 %4, 32 # | store i32 %rem.i.i, ptr %__y.addr.i.i, align 4 # | %5 = load i32, ptr %__y.addr.i.i, align 4 # | %cmp.i.i = icmp eq i32 %5, 0 # | br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i # | # | if.then.i.i: ; preds = %entry # | %6 = load i32, ptr %__x.addr.i.i, align 4 # | store i32 %6, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | if.end.i.i: ; preds = %entry # | %7 = load i32, ptr %__x.addr.i.i, align 4 # | %8 = load i32, ptr %__y.addr.i.i, align 4 # | %shr.i.i = lshr i32 %7, %8 # | %9 = load i32, ptr %__x.addr.i.i, align 4 # | %10 = load i32, ptr %__y.addr.i.i, align 4 # | %sub.i.i = sub i32 32, %10 # | %shl.i.i = shl i32 %9, %sub.i.i # | %or.i.i = or i32 %shr.i.i, %shl.i.i # | store i32 %or.i.i, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | __rorl.exit: ; preds = %if.then.i.i, %if.end.i.i # | %11 = load i32, ptr %retval.i.i, align 4 # | ret i32 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i64, align 8 # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i64, align 8 # | %y.addr = alloca i32, align 4 # | store i64 %x, ptr %x.addr, align 8 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i64, ptr %x.addr, align 8 # | %1 = load i32, ptr %y.addr, align 4 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 64 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i64, ptr %__x.addr.i, align 8 # | store i64 %4, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | if.end.i: ; preds = %entry # | %5 = load i64, ptr %__x.addr.i, align 8 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %sh_prom.i = zext i32 %6 to i64 # | %shr.i = lshr i64 %5, %sh_prom.i # | %7 = load i64, ptr %__x.addr.i, align 8 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 64, %8 # | %sh_prom1.i = zext i32 %sub.i to i64 # | %shl.i = shl i64 %7, %sh_prom1.i # | %or.i = or i64 %shr.i, %shl.i # | store i64 %or.i, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | __rorll.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i64, ptr %retval.i, align 8 # | ret i64 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clz(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzl(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzll(i64 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i64, align 8 # | %t.addr = alloca i64, align 8 # | store i64 %t, ptr %t.addr, align 8 # | %0 = load i64, ptr %t.addr, align 8 # | store i64 %0, ptr %__t.addr.i, align 8 # | %1 = load i64, ptr %__t.addr.i, align 8 # | %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false) # | %3 = trunc i64 %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %cls.i = call i32 @llvm.arm.cls(i32 %1) # | ret i32 %cls.i # | } # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/86891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bbac9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bbac97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bbac9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc157933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc15798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc157933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc15791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bbac30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bbac30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bbac158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bba8c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bba8c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc15791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc15791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc15791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bba8c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (2260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acf51d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acf51cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acf51d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c4e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c4e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c4e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c4e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acf5168bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acf5168a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acf514d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acf4dfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acf4dfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c4e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c4e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c4e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acf4dfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (2261 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fa4f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fa4f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fa4f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa44ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa44eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa44ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa44ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fa4f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fa4f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fa4ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fa4ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fa4ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa44ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa44ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa44ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fa4ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633f32d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633f32d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633f32da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90e8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633f326fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633f326fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633f32548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633f2f03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633f2f03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90e8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633f2f03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (2264 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.brev8.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @zip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.zip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @unzip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.unzip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.brev8.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.zip.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.unzip.i32(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cece14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cece11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cece1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5758649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5758649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5758631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cecdaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560cecdaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560cecd8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ceca3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ceca3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5758632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57586330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ceca3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (2265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkx1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1a89e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1a89e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1a89e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17be231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1a897cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1a897ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1a89618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1a8610e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1a8610b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17be2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1a8610a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (2266 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055728e643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055728e640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055728e64462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1488f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1488f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1488f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1488eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055728e5d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055728e5d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055728e5be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055728e26de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055728e26db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1488eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1488eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1488eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055728e26da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (2267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea5579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dea5576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dea557a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bab831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea550fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dea550fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dea54f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dea51a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dea51a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bab8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea51a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (2268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f9b625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f9b622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f9b62662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cd5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cd578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cd5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cd571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f9b5bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f9b5bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f9b5a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f9b24fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f9b24fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cd571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cd571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cd571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f9b24fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (2269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055602aa9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055602aa97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055602aa9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaac505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaac55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaac505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaac4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055602aa30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055602aa30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055602aa158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055602a6c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055602a6c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaac4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaac4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaac4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055602a6c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (2270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056001ac76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056001ac73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056001ac7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8daf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8daf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8daf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8daf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056001ac0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056001ac0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056001abf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056001a8a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056001a8a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8daf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8daf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8daf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056001a8a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2271 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcafb86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcafb83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcafb8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a7c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a7c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a7c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a7c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcafb1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcafb1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcafb018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcaf7b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcaf7b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a7c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a7c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a7c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcaf7b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (2272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6a6269eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6a6266e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6a626a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c17c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c17ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c17c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c17c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6a61ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6a61ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6a61e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6a5e93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6a5e93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c17c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c17c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c17c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6a5e93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (2273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/17403) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559685190eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055968518de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055968519162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0bd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559685126bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559685126a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055968510b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559684dbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559684dbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559684dbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (2274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24072) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556003d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556003d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556003d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7876c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7876ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7876c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7876c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055560036dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055560036da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556003528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555600001e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555600001b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7876c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7876c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7876c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555600001a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (2275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (2276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577a6f1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577a6f1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577a6f1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34cb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34cb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34cb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34cb831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577a6eb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577a6eb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577a6e988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577a6b47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577a6b47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34cb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34cb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34cb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577a6b47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (2277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/26764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2e835deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2e835ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2e835e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f9d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f9d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f9d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f9d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2e82f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2e82f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2e82d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2e7f87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2e7f87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f9d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f9d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f9d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2e7f87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (2278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff2545ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff25459e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff2545d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f921e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f921e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f921e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f921e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff253f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff253f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff253d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff25086e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff25086b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f921e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f921e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f921e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff25086a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (2279 of 27910) ******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | $__profc__Z6helperi = comdat any # | # | $__llvm_prf_unifcnt__Z6helperi = comdat any # | # | $__profc__Z6kernelPi = comdat any # | # | $__llvm_prf_unifcnt__Z6kernelPi = comdat any # | # | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0 # | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8 # | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8 # | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1 # | @__start___llvm_prf_names = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_names = external hidden addrspace(1) global i8 # | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__start___llvm_prf_data = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_data = external hidden addrspace(1) global i8 # | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__llvm_profile_raw_version = external addrspace(1) constant i64 # | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version } # | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata" # | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %x.addr = alloca i32, align 4, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store i32 %x, ptr %x.addr.ascast, align 4 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load i32, ptr %x.addr.ascast, align 4 # | %add = add nsw i32 %1, 1 # | ret i32 %add # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1) # | br label %po_cont # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone # | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %p = alloca ptr, align 8, addrspace(5) # | %p.addr = alloca ptr, align 8, addrspace(5) # | %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr # | store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8 # | %p1 = load ptr, ptr addrspace(5) %p, align 8 # | store ptr %p1, ptr %p.addr.ascast, align 8 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load ptr, ptr %p.addr.ascast, align 8 # | %2 = load i32, ptr %1, align 4 # | %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4 # | %3 = load ptr, ptr %p.addr.ascast, align 8 # | store i32 %call, ptr %3, align 4 # | ret void # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1) # | br label %po_cont # | } # | # | declare i32 @__llvm_profile_sampling_gpu(i32) # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3 # | # | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64) # | # | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { nounwind } # | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #4 = { convergent nounwind "uniform-work-group-size" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 2, !"EnableValueProfiling", i32 0} # | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # | #0 0x000055fc1ad4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc1ad49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc1ad4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe40a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe40aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe40a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe40a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc1ace2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc1ace2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc1acc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc1a976e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc1a976b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe40a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe40a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe40a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc1a976a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (2280 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = # | ... # `---data was truncated (10240/10936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634f61e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634f61e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634f61ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70fc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70fc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70fc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70fc803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634f617fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634f617fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634f61648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634f5e13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634f5e13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70fc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70fc8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70fc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634f5e13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (2281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %b # | ... # `---data was truncated (10240/38307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654d3cd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654d3cd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654d3cd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87e5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87e5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87e5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87e5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654d3c6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654d3c6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654d3c528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654d3901e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654d3901b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87e5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87e5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87e5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654d3901a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2282 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = al # | ... # `---data was truncated (10240/40137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654e9b75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654e9b72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654e9b7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3976d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3976d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3976d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3976d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654e9b0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654e9b0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654e9af08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654e979fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654e979fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3976d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3976d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3976d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654e979fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (2283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055917eaeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055917eae9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055917eaed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6307d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6307d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6307d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6307d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055917ea82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055917ea82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055917ea678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055917e716e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055917e716b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6307d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6307d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6307d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055917e716a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (2284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615475eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615475e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615475ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32cfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32cfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32cfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32cfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561547582bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561547582a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615475678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561547216e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561547216b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32cfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32cfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32cfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561547216a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (2285 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | # | ... # `---data was truncated (10240/23061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557357993eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557357990e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055735799462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1759e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1759ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1759e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1759e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557357929bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557357929a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055735790e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005573575bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005573575bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1759e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1759e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1759e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573575bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f51050eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f5104de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f5105162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e91f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e91f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e91f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e91f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f50fe6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f50fe6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f50fcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f50c7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f50c7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e91f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e91f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e91f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f50c7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (2287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564df10d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564df10cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564df10d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eaac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eaaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eaac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eaac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564df1067bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564df1067a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564df104c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564df0cfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564df0cfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4eaac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eaac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eaac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564df0cfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (2288 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_zt0() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_zt0() #1 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_zt0() #2 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_zt0() #3 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_zt0() #4 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_za_zt0() #5 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_za_zt0() #6 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_za_zt0() #7 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_za_zt0() #8 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_za_zt0() #9 { # | entry: # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562ecf8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562ecf87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562ecf8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42cd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562ecf20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562ecf20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562ecf058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562ecbb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562ecbb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562ecbb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x0000555e743e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e743e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e743e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccdde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccddea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccdde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccdde31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e74379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e74379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e7435e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e7400de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e7400db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccdde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccdde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccdde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e7400da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (2289 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556a9868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556a9865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556a986962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38bc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38bc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38bc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38bc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556a97febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556a97fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556a97e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556a9492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556a9492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38bc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38bc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38bc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556a9492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (2290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7ea14feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7ea14ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7ea15062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e80933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e8098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e80933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e8091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7ea0e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7ea0e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7ea0ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7e9d79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7e9d79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e8091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e8091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e8091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7e9d79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (2292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635ef8faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635ef8f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635ef8fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4124d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4124d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4124d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4124ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635ef890bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635ef890a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635ef8758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635ef524e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635ef524b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4124ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4124cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4124cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635ef524a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (2293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560d7df3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560d7df0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560d7df462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe756333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe75638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe756333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe75631b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560d7d89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560d7d89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560d7d6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560d7a1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560d7a1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe75631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe75631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe75631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560d7a1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (2294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b89da88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b89da85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b89da8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa850c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa850ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa850c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa850c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b89da1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b89da1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b89da038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b89d6b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b89d6b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa850c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa850c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa850c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b89d6b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (2295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556630589eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556630586e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055663058a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dfe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dfe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dfe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dfe11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055663051fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055663051fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566305048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566301b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566301b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1dfe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dfe11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dfe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566301b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (2296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (2297 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7c08e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7c08e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7c08e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1722249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17222a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1722249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1722231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7c087bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7c087ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7c08608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7c050fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7c050fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1722232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17222330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17222330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7c050fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (2298 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562639530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056263952de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056263953162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f9df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f9df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f9df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f9df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626394c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626394c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626394ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056263915ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056263915ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f9df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f9df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f9df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056263915aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (2299 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/24990) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573d4ae8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005573d4ae5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005573d4ae962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb7f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb7f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb7f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb7f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573d4a7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005573d4a7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573d4a638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005573d4712e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005573d4712b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb7f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb7f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb7f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573d4712a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (2300 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599bc12ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599bc129e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599bc12d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd907d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd907d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd907d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd907d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599bc0c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599bc0c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599bc0a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599bbd56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599bbd56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd907d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd907d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd907d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599bbd56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2301 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/12648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562627661eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056262765ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056262766262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3e9831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626275f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626275f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626275dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056262728be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056262728bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3e98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262728ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (2302 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579f8fe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579f8fe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579f8fea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9235449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9235449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9235431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579f8f7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579f8f7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579f8f648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579f8c13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579f8c13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9235432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92354330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579f8c13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2303 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597f541feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597f541ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597f542062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5f1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5f115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5f1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5f10ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597f53b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597f53b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597f539a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597f5049e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597f5049b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5f10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5f10ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5f10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597f5049a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (2304 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562658d23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562658d20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562658d2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe919133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe91918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe919133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe91911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562658cb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562658cb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562658c9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056265894de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056265894db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe91911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe91911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe91911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056265894da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (2305 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc8aca4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc8aca1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc8aca562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2df61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2df6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2df61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2df603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc8ac3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc8ac3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc8ac1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc8a8cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc8a8ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2df604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2df6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2df6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc8a8cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2306 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/53686) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a360ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a360ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a360ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe39f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe39f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe39f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe39f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a360e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a360e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a360e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a360aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a360aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe39f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe39f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe39f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a360aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (2307 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (2308 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581eeb6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581eeb68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581eeb6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f067b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f067b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f067b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f067b4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581eeb01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581eeb01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581eeae68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581ee795e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581ee795b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f067b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f067b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f067b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581ee795a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (2309 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056457c3a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056457c3a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056457c3a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd57d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd57d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd57d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd57d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056457c33cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056457c33ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056457c3218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056457bfd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056457bfd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd57d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd57d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd57d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056457bfd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (2310 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614d74d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614d74d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614d74d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f499bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f499bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f499bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f499bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614d746cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614d746ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614d74518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614d7100e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614d7100b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f499bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f499bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f499bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614d7100a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (2311 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056332a061eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056332a05ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056332a06262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5c4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5c42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5c4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5c4231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563329ff7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563329ff7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563329fdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563329c8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563329c8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5c4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5c42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5c42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563329c8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (2312 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557259f8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557259f89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557259f8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4647c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4647ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4647c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4647c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557259f22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557259f22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557259f078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557259bb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557259bb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4647c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4647c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4647c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557259bb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-neon-vget.c (2313 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x float> @low_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr # | ... # `---data was truncated (10240/15571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1ddbfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1ddbfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1ddbff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a96f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a96f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a96f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a96f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1ddb94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1ddb94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1ddb798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1dd828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1dd828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a96f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a96f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a96f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1dd828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (2314 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eed8a4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eed8a47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eed8a4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3924733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f392478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3924733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f392471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eed89e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eed89e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eed89c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eed8674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eed8674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f392471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f392471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f392471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eed8674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056119530deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056119530ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056119530e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf61c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf61c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf61c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf61c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611952a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611952a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611952888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561194f37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561194f37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf61c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf61c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf61c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561194f37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (2316 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615caac8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615caac5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615caac962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74d431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615caa5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615caa5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615caa438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615ca6f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615ca6f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74d431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615ca6f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (2317 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561c8a7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561c8a7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561c8a8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f48a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f48aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f48a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f48a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561c8a15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005561c8a15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561c89fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561c86a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561c86a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f48a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f48a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f48a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561c86a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2318 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align # | ... # `---data was truncated (10240/19041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c050faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c050f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c050fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f106d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f106d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f106d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f106d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c05090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c05090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c050758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c04d24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c04d24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f106d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f106d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f106d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c04d24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (2319 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0) # | %2 = extractvalue { <8 x half>, <8 x half> } %1, 0 # | %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0 # | %4 = extractvalue { <8 x half>, <8 x half> } %1, 1 # | %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1 # | ret %struct.float16x8x2_t %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0) # | %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 # | %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0 # | %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 # | %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1 # | %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 # | %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2 # | %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3 # | %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3 # | ret %struct.uint8x16x4_t %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.uint32x4x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.uint32x4x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0 # | store [2 x <4 x i32>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0 # | %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.int8x16x4_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.int8x16x4_t, align 8 # | %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0 # | store [4 x <16 x i8>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false) # | %3 = load %struct.int8x16x4_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.int8x16x4_t %3, 0, 0 # | %5 = extractvalue %struct.int8x16x4_t %3, 0, 1 # | %6 = extractvalue %struct.int8x16x4_t %3, 0, 2 # | %7 = extractvalue %struct.int8x16x4_t %3, 0, 3 # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.float16x8x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.float16x8x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0 # | store [2 x <8 x half>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.float16x8x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.float16x8x2_t %3, 0, 0 # | %5 = extractvalue %struct.float16x8x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %values.addr = alloca ptr, align 4 # | %v = alloca %struct.uint16x8x2_t, align 8 # | %tmp = alloca %struct.uint16x8x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %values, ptr %values.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0) # | %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0 # | %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0 # | %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1 # | %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1 # | store %struct.uint16x8x2_t %5, ptr %tmp, align 8 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false) # | %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0 # | %6 = load <8 x i16>, ptr %arrayidx, align 8 # | %7 = load ptr, ptr %values.addr, align 4 # | %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0 # | store <8 x i16> %6, ptr %arrayidx1, align 8 # | %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1 # | %8 = load <8 x i16>, ptr %arrayidx3, align 8 # | %9 = load ptr, ptr %values.addr, align 4 # | %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1 # | store <8 x i16> %8, ptr %arrayidx4, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %ref.tmp = alloca %struct.int32x4x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0) # | %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0 # | %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1 # | %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1 # | store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8 # | %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0 # | %6 = load <4 x i32>, ptr %arrayidx, align 8 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000563cb81f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563cb81efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563cb81f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb9aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb9aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb9aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb9aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cb8188bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563cb8188a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563cb816d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563cb7e1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563cb7e1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb9aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb9aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb9aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cb7e1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (2320 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2321 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( # | ... # `---data was truncated (10240/51185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e97bebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e97beb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e97bebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f046f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f046f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f046f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f046f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e97be52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e97be52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e97be378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e97bae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e97bae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f046f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f046f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f046f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e97bae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (2322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056312f1cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056312f1cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056312f1ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f877b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f877b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f877b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f877b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056312f163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056312f163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056312f1488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056312edf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056312edf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f877b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f877b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f877b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056312edf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (2323 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625493e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625493dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625493e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f133bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f133bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f133bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f133bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562549377bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562549377a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056254935c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056254900be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056254900bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f133bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f133bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f133bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056254900ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (2324 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cba9bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cba9bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cba9c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faed8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faed8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faed8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faed8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cba955bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cba955a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cba93a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cba5e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cba5e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faed8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faed8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faed8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cba5e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2325 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (2326 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | # | ... # `---data was truncated (10240/17236) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e961dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e961dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e961dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbba1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbba1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbba1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbba1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e961d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e961d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e961d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9619fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9619fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbba1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbba1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbba1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9619fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (2327 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563a9bd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563a9bd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563a9bd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bb4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bb4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bb4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bb4aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563a9b6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563a9b6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563a9b538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563a9802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563a9802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bb4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bb4aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bb4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563a9802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (2328 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056315b58deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056315b58ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056315b58e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cc6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cc6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cc6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cc6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056315b523bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056315b523a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056315b5088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056315b1b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056315b1b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cc6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cc6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cc6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056315b1b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2329 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ece370eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ece36de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ece37162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3996933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f399698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3996933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f399691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ece306bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ece306a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ece2eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ecdf9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ecdf9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f399691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f399691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f399691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ecdf9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (2330 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (2331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | de # | ... # `---data was truncated (10240/12091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056303a2d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056303a2cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056303a2d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0c881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0c88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0c881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0c8803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056303a267bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056303a267a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056303a24c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563039efbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563039efbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0c8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0c88050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0c88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563039efba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (2332 of 27910) ******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }> # | %struct.A.base = type <{ ptr, i32 }> # | # | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8 # | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000055c17b280eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c17b27de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c17b28162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0141f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0141f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0141f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0141eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c17b216bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c17b216a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c17b1fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c17aeaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c17aeaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0141eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0141eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0141eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c17aeaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (2333 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa74044eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa74041e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa7404562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a7ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a7ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a7ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a7ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa73fdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa73fdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa73fbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa73c6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa73c6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a7ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a7ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a7ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa73c6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (2334 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c7ff74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c7ff71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c7ff7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28cec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28cec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28cec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28cec03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c7ff0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c7ff0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c7feef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c7fb9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c7fb9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28cec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28cec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28cec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c7fb9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (2335 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a652b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a652b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a652b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f205ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f205eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f205ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f205ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a6524cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a6524ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a652318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a64ee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a64ee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f205ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f205ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f205ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a64ee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (2336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree n # | ... # `---data was truncated (10240/15237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055727b10beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055727b108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055727b10c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff898a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff898aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff898a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff898a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055727b0a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055727b0a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055727b0868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055727ad35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055727ad35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff898a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff898a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff898a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055727ad35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (2337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603a4f4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603a4f4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603a4f4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e12f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e12f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e12f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e12eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603a4ee3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603a4ee3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603a4ec88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603a4b77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603a4b77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e12eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e12eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e12eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603a4b77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (2338 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6) # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <4 x float> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load <4 x float>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 16 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %10, ptr %__ret.i, align 16 # | %11 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %c.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6) # | store <2 x double> %9, ptr %ref.tmp.i, align 16 # | %10 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %10, ptr %__ret.i, align 16 # | %11 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x float> # | %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> # | %fmla = bitcast <8 x i8> %4 to <2 x float> # | %fmla1 = bitcast <8 x i8> %3 to <2 x float> # | %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1) # | store <2 x float> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Functio # | ... # `---data was truncated (10240/80179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055dcb6240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcb623de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcb624162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc577449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc577449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc577431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcb61d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcb61d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcb61bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcb5e6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcb5e6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc577432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5774330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcb5e6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (2339 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm # | ... # `---data was truncated (10240/35597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581153aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581153a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581153ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0df2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0df275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0df2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0df26ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558115342bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558115342a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581153278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558114fd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558114fd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0df26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0df26ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0df26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558114fd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (2340 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d276846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d276843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d27684762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c58831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2767dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2767dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2767c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d276470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d276470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c588330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d276470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (2341 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643b33f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643b33f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643b33f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd88d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd88d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd88d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd88d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643b338bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643b338ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643b33708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643b301fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643b301fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd88d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd88d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd88d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643b301fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (2342 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d758801eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7587fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d75880262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb869d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb869d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb869d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb869d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d758797bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d758797a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d75877c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d75842be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d75842bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb869d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb869d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb869d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d75842ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (2343 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64im(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.aes64im(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ds(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64im(i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1566bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1566b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1566bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb81933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb8198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb81933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb8191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e156651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e156651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1566368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1562e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1562e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb8191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb8191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb8191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1562e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (2344 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrga # | ... # `---data was truncated (10240/28435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f23e73beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f23e738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f23e73c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4678a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4678aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4678a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4678a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f23e6d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f23e6d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f23e6b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f23e365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f23e365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4678a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4678a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4678a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f23e365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (2345 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a2c71eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a2c71be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a2c71f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb41b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb41b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb41b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb41b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a2c6b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a2c6b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a2c6998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a2c348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a2c348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb41b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb41b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb41b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a2c348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (2346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, # | ... # `---data was truncated (10240/28346) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fa6300eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fa62fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fa630162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa65f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa65f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa65f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa65f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fa6296bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fa6296a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fa627b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558fa5f2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558fa5f2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa65f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa65f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa65f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fa5f2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (2347 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be58864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be58861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be5886562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde18449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde184a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde18449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde18431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be587fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be587faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be587df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be5848ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be5848eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde18432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde184330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde184330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be5848ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (2348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c18206deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c18206ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c18206e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dc4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dc435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dc4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dc42ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c182003bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c182003a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c181fe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c181c97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c181c97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1dc42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dc42ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dc42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c181c97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (2349 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116957) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8163e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8163e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8163e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f8ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f8ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f8ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f8ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c81637cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c81637ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8163618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c816010e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c816010b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f8ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f8ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f8ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c816010a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (2350 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2351 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056450dbc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056450dbbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056450dbc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97e0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97e0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97e0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97e0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056450db56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056450db56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056450db3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056450d7eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056450d7eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97e0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97e0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97e0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056450d7eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (2352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605835f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605835ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605835f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c95f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c95f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c95f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c95eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560583586bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560583586a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056058356b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056058321ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056058321ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c95eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c95eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c95eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056058321aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (2353 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) # | ... # `---data was truncated (10240/27055) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607bce15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607bce12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607bce1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6433133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f643318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6433133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f643311b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607bcdabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607bcdaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607bcd908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607bca3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607bca3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f643311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f643311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f643311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607bca3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (2354 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (2355 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4c4758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4c4755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4c475962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f0b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f0b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f0b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f0b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4c46eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c4c46eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4c46d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4c4382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4c4382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f0b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f0b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f0b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4c4382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (2356 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a80e7adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a80e7aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a80e7ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bafe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bafea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bafe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bafe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a80e743bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a80e743a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a80e7288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a80e3d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a80e3d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bafe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bafe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bafe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a80e3d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (2357 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dff32eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556dff32be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556dff32f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f87f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f87f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f87f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f87eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dff2c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556dff2c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556dff2a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556dfef58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556dfef58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f87eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f87eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f87eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dfef58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (2358 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (2359 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637670caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637670c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637670cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe10249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe10249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe10231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563767060bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563767060a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637670458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563766cf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563766cf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe10232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe102330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563766cf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (2360 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a35d79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a35d76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a35d7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c0b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c0b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c0b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c0b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a35d0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a35d0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a35cf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a359a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a359a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c0b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c0b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c0b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a359a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (2361 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad2077aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad20777e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad2077b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1cd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad20710bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad20710a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad206f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad203a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad203a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad203a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (2362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (2363 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d0f111eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d0f10ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d0f11262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfd9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfd9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfd9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfd9c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d0f0a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d0f0a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d0f08c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d0ed3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d0ed3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfd9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfd9c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfd9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d0ed3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (2364 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/10610) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558beac8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558beac8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558beac8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e86431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558beac24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558beac24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558beac098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bea8b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bea8b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bea8b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2365 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f108a5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f108a59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f108a5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6c591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1089f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1089f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1089d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f108686e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f108686b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6c591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f108686a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (2366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2b55d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2b55cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2b55d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29fc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2b5567bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2b5567a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2b554c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2b51fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2b51fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29fc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2b51fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2367 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = all # | ... # `---data was truncated (10240/41587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c445e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c445e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c445e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f0ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f0ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f0ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f0ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c4457cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c4457ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c445618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c44210e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c44210b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f0ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f0ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f0ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c44210a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (2368 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a5438beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a54388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a5438c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3728e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3728e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3728e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3728e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a54321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a54321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a543068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a53fb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a53fb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3728e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3728e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3728e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a53fb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (2369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649b10b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649b10b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649b10b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38b9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38b978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38b9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38b971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649b1049bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649b1049a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649b102e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649b0cdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649b0cddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38b971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38b971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38b971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649b0cdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (2370 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (2371 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (2372 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601850d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601850cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601850d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0511f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0511f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0511f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0511f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560185066bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560185066a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056018504b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560184cfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560184cfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0511f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0511f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0511f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560184cfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (2373 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 # | ... # `---data was truncated (10240/18303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aeb281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559aeb27ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559aeb28262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fdc905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fdc95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fdc905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fdc8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aeb217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559aeb217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559aeb1fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559aeaeabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559aeaeabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fdc8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fdc8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fdc8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559aeaeaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (2374 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (2375 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055966a551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055966a54ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055966a55262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8431e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8431ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8431e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8431e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055966a4e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055966a4e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055966a4cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055966a17be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055966a17bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8431e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8431e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8431e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055966a17ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (2376 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612d62f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612d62f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612d62f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1587333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f158738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1587333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f158731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612d628bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612d628ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612d62708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612d5f1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612d5f1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f158731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f158731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f158731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612d5f1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (2377 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (2378 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a6c867eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a6c864e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a6c86862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4560e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4560ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4560e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4560e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a6c7fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a6c7fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a6c7e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a6c491e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a6c491b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4560e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4560e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4560e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a6c491a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (2379 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f373415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f373412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f37341662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc711b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc711b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc711b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc711b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3733abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3733aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3733908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f37303fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f37303fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc711b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc711b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc711b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f37303fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (2380 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b180177eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b180174e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b18017862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7154849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71548a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7154849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7154831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b18010dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b18010da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1800f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b17fda1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b17fda1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7154832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71548330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71548330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b17fda1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (2381 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, # | ... # `---data was truncated (10240/47764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582ea93beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582ea938e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582ea93c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8635533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f863558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8635533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f863551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582ea8d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582ea8d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582ea8b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582ea565e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582ea565b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f863551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f863551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f863551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582ea565a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (2382 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (2383 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cacd629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cacd626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cacd62a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ec1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ec1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ec1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ec1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cacd5bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cacd5bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cacd5a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cacd253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cacd253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ec1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ec1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ec1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cacd253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (2384 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/235596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f957414eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f957411e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f95741562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe263b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe263b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe263b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe263b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9573aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9573aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f95738f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f95703ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f95703eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe263b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe263b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe263b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f95703ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (2385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe7db13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe7db10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe7db1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6dc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6dc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6dc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6dc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe7daa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe7daa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe7da8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe7d73de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe7d73db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6dc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6dc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6dc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe7d73da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (2386 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0, align 8 # | %1 = load <4 x bfloat>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x bfloat> %1, i32 1 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0, align 16 # | %1 = load <8 x bfloat>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x bfloat> %1, i32 7 # | store bfloat %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_48 = alloca <4 x bfloat>, align 8 # | %__s0_48 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_48, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_48, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_48, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_48, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_46 = alloca <8 x bfloat>, align 16 # | %__s0_46 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_46, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_46, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_46, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_46, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_52 = alloca <4 x bfloat>, align 8 # | %__s0_52 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_52, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_52, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_52, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_52, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_50 = alloca <8 x bfloat>, align 16 # | %__s0_50 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_50, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_50, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_50, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_50, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %.compoundliteral.i = alloca <4 x bfloat>, align 8 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8 # | store <4 x bfloat> %5, ptr %__ret.i, align 8 # | %6 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %.compoundliteral.i = alloca <8 x bfloat>, align 16 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | %5 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4 # | %6 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5 # | %7 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6 # | %8 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7 # | store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16 # | %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/13833) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556e79251eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e7924ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e7925262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a3f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a3f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a3f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a3f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e791e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e791e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e791cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e78e7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e78e7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a3f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a3f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a3f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e78e7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (2387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056471ad23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056471ad20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056471ad2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ac1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ac158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ac1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ac151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056471acb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056471acb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056471ac9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056471a94de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056471a94db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ac151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ac151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ac151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056471a94da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (2388 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055668e4c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055668e4c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055668e4c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc36d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc36d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc36d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc36d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055668e45bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055668e45ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055668e4408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055668e0efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055668e0efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc36d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc36d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc36d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055668e0efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (2389 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564daea44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564daea41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564daea4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cc5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cc518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cc5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cc511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dae9dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dae9daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dae9bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564dae66ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564dae66eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cc511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cc511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cc511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dae66ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (2390 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618401f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618401f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618401f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c7b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c7b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c7b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c7b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561840189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561840189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056184016e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056183fe1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056183fe1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c7b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c7b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c7b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056183fe1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (2391 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bac8ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bac8dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bac8de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05ab31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bac873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bac873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bac8588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bac507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bac507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bac507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (2392 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (2393 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e222c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e222c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e222c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb55133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb5518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb55133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb5511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e222be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e222be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e222bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e222874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e222874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb5511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb5511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb5511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e222874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (2394 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/32701) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588f6994eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588f6991e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588f699562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ebb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ebb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ebb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ebb031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588f692abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588f692aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588f690f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588f65bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588f65beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ebb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ebb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ebb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588f65bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (2395 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | % # | ... # `---data was truncated (10240/33764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc4c116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc4c113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc4c11762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80b0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80b038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80b0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80b031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc4c0acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc4c0aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc4c0918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc4bd40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc4bd40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80b031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80b031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80b031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc4bd40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (2396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564342754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564342751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056434275562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2cca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2ccaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2cca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2cca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643426eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643426eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643426cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056434237ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056434237eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2cca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2cca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2cca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056434237ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (2397 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5e7c30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5e7c2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5e7c3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe755333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe75538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe755333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe75531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5e7bc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5e7bc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5e7bab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5e785ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5e785ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe75531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe75531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe75531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5e785aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (2398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c260aaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c260aabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c260aaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf7a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf7a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf7a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf7a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c260a44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c260a44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c260a298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2606d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2606d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf7a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf7a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf7a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2606d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2399 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m2_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv32i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m2_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m2_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv8i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m4_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv16i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv16i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m8_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv32i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv32i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale # | ... # `---data was truncated (10240/40902) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e80576deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e80576ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e80576e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84a1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84a1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84a1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84a1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e805703bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e805703a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8056e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e805397e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e805397b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84a1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84a1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84a1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e805397a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (2400 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558812ff5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558812ff2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558812ff662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc67ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc67aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc67ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc67ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558812f8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558812f8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558812f708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558812c1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558812c1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc67ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc67ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc67ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558812c1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2401 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p2.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %retval = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %c = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | %coerce4 = alloca <4 x half>, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b1 = load <4 x half>, ptr %b, align 8 # | store <2 x i32> %c.coerce, ptr %c, align 8 # | %c2 = load <4 x half>, ptr %c, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b1, ptr %b.addr, align 8 # | store <4 x half> %c2, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %1, ptr %coerce, align 8 # | %3 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %2, ptr %coerce3, align 8 # | %4 = load <2 x i32>, ptr %coerce3, align 8 # | store <2 x i32> %3, ptr %__p1.i, align 8 # | %__p11.i = load <4 x half>, ptr %__p1.i, align 8 # | store <2 x i32> %4, ptr %__p2.i, align 8 # | %__p22.i = load <4 x half>, ptr %__p2.i, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8 # | store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %7 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %9, ptr %retval.i, align 8 # | %10 = load <2 x i32>, ptr %retval.i, align 8 # | store <2 x i32> %10, ptr %coerce4, align 8 # | %11 = load <4 x half>, ptr %coerce4, align 8 # | store <4 x half> %11, ptr %retval, align 8 # | %12 = load <2 x i32>, ptr %retval, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p2.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %retval = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %c = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | %coerce4 = alloca <8 x half>, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b1 = load <8 x half>, ptr %b, align 16 # | store <4 x i32> %c.coerce, ptr %c, align 16 # | %c2 = load <8 x half>, ptr %c, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b1, ptr %b.addr, align 16 # | store <8 x half> %c2, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %1, ptr %coerce, align 16 # | %3 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %2, ptr %coerce3, align 16 # | %4 = load <4 x i32>, ptr %coerce3, align 16 # | store <4 x i32> %3, ptr %__p1.i, align 16 # | %__p11.i = load <8 x half>, ptr %__p1.i, align 16 # | store <4 x i32> %4, ptr %__p2.i, align 16 # | %__p22.i = load <8 x half>, ptr %__p2.i, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16 # | store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %7 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7) # | store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %9, ptr %retval.i, align 16 # | %10 = load <4 x i32>, ptr %retval.i, align 16 # | store <4 x i32> %10, ptr %coerce4, align 16 # | %11 = load <8 x half>, ptr %coerce4, align 16 # | store <8 x half> %11, ptr %retval, align 16 # | %12 = load <4 x i32>, ptr %retval, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %a = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | store <2 x i32> %a.coerce, ptr %a, align 8 # | %a1 = load <4 x half>, ptr %a, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b2 = load <4 x half>, ptr %b, align 8 # | store <4 x half> %a1, ptr %a.addr, align 8 # | store <4 x half> %b2, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %coerce, align 8 # | %2 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %1, ptr %coerce3, align 8 # | %3 = load <2 x i32>, ptr %coerce3, align 8 # | call void @llvm.experimental.noalias.scope.decl(metadata !3) # | store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3 # | %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3 # | store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3 # | %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3 # | store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3 # | store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3 # | %6 = bitcast <8 x i8> %4 to <4 x i16> # | %7 = bitcast <8 x i8> %5 to <4 x i16> # | %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3 # | %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %a = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | store <4 x i32> %a.coerce, ptr %a, align 16 # | %a1 = load <8 x half>, ptr %a, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b2 = load <8 x half>, ptr %b, align 16 # | store <8 x half> %a1, ptr %a.addr, align 16 # | store <8 x half> %b2, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %coerce, align 16 # | %2 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %1, ptr %coerce3, align 16 # | %3 = load <4 x i32>, ptr %coerce3, align 16 # | call void @llvm.experimental.noalias.scope.decl(metadata !6) # | store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6 # | %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6 # | store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6 # | %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6 # | store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6 # | store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6 # | %6 = bitcast <16 x i8> %4 to <8 x i16> # | %7 = bitcast <16 x i8> %5 to <8 x i16> # | %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6 # | %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef # | ... # `---data was truncated (10240/35874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055d7691f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7691f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7691f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bdbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bdbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bdbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bdbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d769189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d769189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d76916e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d768e1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d768e1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bdbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bdbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bdbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d768e1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (2402 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, al # | ... # `---data was truncated (10240/58468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d8d3eabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d8d3ea8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8d3eac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc870133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc87018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc870133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc87011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8d3e41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8d3e41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8d3e268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8d3ad5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8d3ad5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc87011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc87011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc87011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8d3ad5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2403 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1( # | ... # `---data was truncated (10240/32505) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec9d00eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec9d00be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec9d00f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe100533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe10058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe100533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe10051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec9cfa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec9cfa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec9cf898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec9cc38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec9cc38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe10051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe10051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe10051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec9cc38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (2404 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055794d008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055794d005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055794d00962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a39f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a39f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a39f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a39f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055794cf9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055794cf9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055794cf838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055794cc32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055794cc32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a39f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a39f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a39f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055794cc32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (2405 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056168989aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561689897e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056168989b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ecbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ecbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ecbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ecbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561689830bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561689830a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616898158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616894c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616894c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ecbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ecbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ecbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616894c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (2406 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target # | ... # `---data was truncated (10240/23439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561bd16bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561bd16b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561bd16bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56ae305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56ae35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56ae305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56ae2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bd1652bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561bd1652a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561bd16378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561bd12e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561bd12e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56ae2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56ae2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56ae2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bd12e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (2408 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bdbbedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bdbbeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bdbbee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efee3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efee36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efee3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efee3631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bdbb83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bdbb83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bdbb688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bdb817e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bdb817b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efee3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efee36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efee36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bdb817a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (2409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612fc58aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612fc587e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612fc58b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf1ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612fc520bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612fc520a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612fc5058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612fc1b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612fc1b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612fc1b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (2410 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056233d92eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056233d92be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056233d92f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd393705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd39375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd393705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3936ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056233d8c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056233d8c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056233d8a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056233d558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056233d558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3936eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3936ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3936ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056233d558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (2411 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ced4cb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ced4cafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ced4cb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f893db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f893db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f893db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f893daed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ced4c48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ced4c48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ced4c2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ced48dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ced48dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f893daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f893daef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f893daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ced48dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (2412 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c854526eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c854523e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c85452762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f060d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f060d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f060d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f060d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8544bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8544bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8544a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c854150e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c854150b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f060d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f060d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f060d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c854150a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (2413 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555955adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555955ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555955add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc68aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc68aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc68aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc68aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555955a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555955a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555955a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555955706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555955706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc68aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc68aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc68aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555955706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (2414 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac28e36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac28e33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac28e3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcdbab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcdbab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcdbab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcdbaaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac28dccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac28dcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac28db18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac28a60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac28a60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcdbaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcdbaaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcdbaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac28a60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (2415 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a201ee2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a201edfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a201ee362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7670133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f767018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7670133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f767011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a201e78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a201e78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a201e5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a201b0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a201b0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f767011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f767011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f767011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a201b0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (2416 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (2417 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563dbbbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563dbbbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563dbbbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f889f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f889f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f889f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f889f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563dbb53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563dbb53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563dbb388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563db7e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563db7e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f889f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f889f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f889f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563db7e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (2418 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/32709) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f5ab91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f5ab8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f5ab9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd28be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd28bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd28be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd28be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f5ab27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f5ab27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f5ab0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f5a7bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f5a7bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd28be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd28be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd28be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f5a7bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (2419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (2420 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4eae52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4eae4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4eae5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb1af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb1af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb1af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb1af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4eade8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4eade8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4eadcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4eaa7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4eaa7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb1af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb1af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb1af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4eaa7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (2421 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (2422 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.ris # | ... # `---data was truncated (10240/18562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579edb25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579edb22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579edb2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff805333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff80538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff805333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff80531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579edabbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579edabba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579edaa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579ed74fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579ed74fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff80531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff80531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff80531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579ed74fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (2423 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/54480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b29c4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b29c4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b29c4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae1ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b29be4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b29be4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b29bc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b29878e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b29878b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae1ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b29878a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055afa4c3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afa4c37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afa4c3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f289fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f289fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f289fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f289fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afa4bd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afa4bd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afa4bb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afa4864e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afa4864b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f289fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f289fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f289fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afa4864a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2425 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af78426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af78423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af7842762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fc8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fc818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fc8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fc811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af783bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af783bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af783a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af78050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af78050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fc811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fc811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fc811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af78050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (2426 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653d7ff0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653d7fede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653d7ff162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd475b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd475b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd475b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd475aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653d7f86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653d7f86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653d7f6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653d7c1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653d7c1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd475aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd475aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd475aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653d7c1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (2427 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a001511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a00150ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a00151262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67ebf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0014a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0014a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a00148c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a00113be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a00113bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a00113ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (2428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644c88f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644c88f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644c88f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c3c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c3c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c3c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c3c003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644c888ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644c888ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644c88738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644c8522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644c8522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c3c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c3c0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c3c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644c8522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (2429 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/47706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056459409aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564594097e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056459409b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c7e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c7e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c7e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c7e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564594030bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564594030a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645940158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564593cc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564593cc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c7e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c7e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c7e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564593cc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (2430 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d992dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d992dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d992e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c9ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c9ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c9ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c9ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d99275bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d99275a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d9925a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d98f09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d98f09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c9ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c9ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c9ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d98f09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (2431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv64i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u64m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/30303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055971c05ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055971c059e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055971c05d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc169305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc16935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc169305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1692ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055971bff2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055971bff2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055971bfd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055971bc86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055971bc86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1692eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1692ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1692ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055971bc86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (2432 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (2433 of 27910) ******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | declare noundef zeroext i1 @_Z1av() #1 # | # | declare noundef zeroext i1 @_Z1bv() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.expect.i64(i64, i64) #2 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true) # | br i1 %call.expval, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true) # | br i1 %call1.expval, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i1 @llvm.expect.i1(i1, i1) #2 # | # | declare noundef zeroext i1 @_Z1cv() #1 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1cv() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: ; preds = %lor.lhs.false # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %lor.end # | # | lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry # | %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %lor.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.end # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %if.then, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %if.then, label %lor.lhs.false2 # | # | lor.lhs.false2: ; preds = %lor.lhs.false # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.lhs.false2 # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %dec = add nsw i32 %2, -1 # | store i32 %dec, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: # | ... # `---data was truncated (10240/28468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # | #0 0x000055c8b9fc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8b9fc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8b9fc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc25d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc25d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc25d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc25d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8b9f5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8b9f5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8b9f438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8b9bf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8b9bf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc25d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc25d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc25d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8b9bf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (2434 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055803ccd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055803ccd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055803ccda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe66ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe66aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe66ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe66ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055803cc6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055803cc6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055803cc548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055803c903e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055803c903b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe66ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe66ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe66ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055803c903a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (2435 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055844a64eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055844a64be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055844a64f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8738a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8738aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8738a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8738a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055844a5e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055844a5e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055844a5c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055844a278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055844a278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8738a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8738a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8738a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055844a278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (2436 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c6bdebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c6bde8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c6bdec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f097ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f097ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f097ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f097ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c6bd81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c6bd81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c6bd668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c6ba15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c6ba15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f097ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f097ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f097ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c6ba15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (2437 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | st # | ... # `---data was truncated (10240/110292) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c4641eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c4641be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c4641f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dffa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c463b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c463b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c463998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c46048e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c46048b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0dffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dffa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c46048a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (2438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c7a48feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c7a48ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c7a49062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe506d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe506d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe506d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe506d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c7a425bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c7a425a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c7a40a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c7a0b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c7a0b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe506d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe506d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe506d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c7a0b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (2439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.a # | ... # `---data was truncated (10240/32394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfe011deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfe011ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfe011e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa65bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa65bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa65bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa65bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfe00b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfe00b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfe00988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfdfd47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfdfd47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa65bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa65bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa65bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfdfd47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (2440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643fc0e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643fc0e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643fc0e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb381133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb38118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb381133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb38111b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643fc07ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643fc07ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643fc0638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643fbd12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643fbd12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb38111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb38111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb38111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643fbd12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (2441 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564680b9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564680b9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564680ba062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96f6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96f678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96f6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96f671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564680b35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564680b35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564680b1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646807c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646807c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96f671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96f671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96f671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646807c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (2442 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f144c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f144c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f144c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92e8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f1445cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f1445ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f144418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f140f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f140f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f92e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92e8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f140f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (2444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d380f56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d380f53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d380f5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95f4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95f44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95f4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95f4431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d380eecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d380eeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d380ed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d380b80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d380b80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95f4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95f44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95f44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d380b80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (2445 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/205813) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567ba59feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005567ba59ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567ba5a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc573d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc573d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc573d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc573d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567ba535bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567ba535a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567ba51a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567ba1c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567ba1c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc573d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc573d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc573d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567ba1c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (2446 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055979a48ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055979a489e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055979a48d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa97e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa97e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa97e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa97e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055979a422bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055979a422a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055979a4078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055979a0b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055979a0b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa97e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa97e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa97e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055979a0b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (2447 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (2448 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637203b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637203afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637203b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2681449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26814a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2681449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2681431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563720348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563720348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056372032d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056371ffdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056371ffdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2681432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26814330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26814330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056371ffdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (2449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d0bab0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d0baade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d0bab162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c1c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c1c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c1c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c1c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d0ba46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d0ba46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d0ba2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d0b6dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d0b6dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c1c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c1c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c1c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d0b6daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (2450 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3be200eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3be1fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3be20162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63dab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63dab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63dab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63dab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3be196bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3be196a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3be17b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3bde2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3bde2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63dab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63dab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63dab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3bde2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (2451 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b75415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b75412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b7541662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9efc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9efc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9efc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9efc231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b753abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b753aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b753908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b7503fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b7503fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9efc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9efc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9efc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b7503fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (2452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | ... # `---data was truncated (10240/12457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd94749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd94746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd9474a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde97d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde97d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde97d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde97d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd946dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd946dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd946c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd94373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd94373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde97d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde97d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde97d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd94373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (2453 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2de7c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2de7c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2de7c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc240d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc240d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc240d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc240d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2de75bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2de75ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2de7408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2de3efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2de3efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc240d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc240d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc240d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2de3efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (2454 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff4cc57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff4cc54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff4cc5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7596d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7596d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7596d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7596d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff4cbedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff4cbeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff4cbd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff4c881e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff4c881b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7596d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7596d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7596d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff4c881a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (2455 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561bdeb3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561bdeb37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561bdeb3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0075d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0075d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0075d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0075d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bdead0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561bdead0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561bdeab58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561bde764e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561bde764b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0075d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0075d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0075d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bde764a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (2456 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (2457 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e6622deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e6622ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e6622e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde2b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde2b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde2b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde2b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e661c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e661c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e661a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e65e57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e65e57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde2b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde2b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde2b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e65e57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (2458 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f2b7c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f2b7c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f2b7c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f861221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86122725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f861221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8612203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f2b75cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f2b75ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f2b7418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f2b3f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f2b3f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8612204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86122050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86122050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f2b3f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2459 of 27910) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.funcref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5b214beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5b2148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5b214c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f007dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f007dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f007dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f007dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5b20e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5b20e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5b20c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5b1d75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5b1d75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f007dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f007dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f007dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5b1d75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (2460 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/47728) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e398af6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e398af3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e398af762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52c2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52c238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52c2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52c231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e398a8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e398a8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e398a718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e398720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e398720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52c231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52c231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52c231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e398720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (2461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e18823feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e18823ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e18824062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5169733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f516978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5169733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f516971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1881d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1881d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1881ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e187e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e187e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f516971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f516971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f516971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e187e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (2462 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9ef1d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9ef1cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9ef1d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81c4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81c478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81c4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81c471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9ef166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9ef166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9ef14b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9eedfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9eedfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81c471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81c471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81c471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9eedfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (2463 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f121c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f121bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f121c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd81133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd8118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd81133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd8111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f121b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f121b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f121b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f12182be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f12182bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd8111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd8111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd8111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f12182ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (2464 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560e23f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560e23f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560e23f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfdaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfdaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfdaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfdaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560e238dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560e238da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560e23728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560e2021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560e2021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfdaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfdaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfdaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560e2021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (2465 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c833b7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c833b7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c833b8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d50705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d5075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d50705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d506ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c833b15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c833b15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c833afa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8337a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8337a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d506eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d506ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d506ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8337a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2466 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (2467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv # | ... # `---data was truncated (10240/75133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557090bc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557090bc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557090bca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09eb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557090b5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557090b5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557090b448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570907f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570907f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570907f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2468 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562dd3d0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562dd3d07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562dd3d0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5655f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5655f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5655f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5655f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dd3ca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562dd3ca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562dd3c858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562dd3934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562dd3934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5655f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5655f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5655f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dd3934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (2469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4 # | ... # `---data was truncated (10240/25575) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bbfcabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bbfca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bbfcac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3156133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f315618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3156133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f315611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bbfc41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bbfc41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bbfc268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bbf8d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bbf8d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f315611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f315611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f315611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bbf8d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (2470 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr % # | ... # `---data was truncated (10240/66087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635b4c43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635b4c40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635b4c4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b18733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b1878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b18733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b1871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635b4bd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635b4bd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635b4bbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635b486de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635b486db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b1871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b1871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b1871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635b486da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (2471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ef3e52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ef3e4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ef3e5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08f8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08f8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08f8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08f8eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ef3de8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ef3de8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ef3dcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ef3a7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ef3a7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08f8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08f8eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08f8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ef3a7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (2473 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563162a54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563162a51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563162a5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f496b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f496b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f496b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f496b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631629eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631629eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631629cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056316267ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056316267eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f496b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f496b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f496b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056316267ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (2474 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580845d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580845d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580845d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f673a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f673a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f673a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f673a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055808456ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055808456ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580845538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558084202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558084202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f673a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f673a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f673a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558084202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2475 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (2476 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b3dc8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b3dc8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b3dc8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb387c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb387c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb387c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb387c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b3dc23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b3dc23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b3dc088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b3d8b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b3d8b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb387c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb387c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb387c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b3d8b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (2477 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7f6d6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7f6d68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7f6d6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75dad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f6d01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7f6d01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7f6ce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7f6995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7f6995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f6995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (2478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556212241eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055621223ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055621224262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6ca81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6ca8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6ca81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6ca803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562121d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562121d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562121bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556211e6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556211e6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6ca804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6ca8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6ca8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556211e6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2479 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7c770ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7c7709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7c770d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f073ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f073ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f073ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f073ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7c76a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7c76a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7c76878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7c7336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7c7336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f073ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f073ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f073ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7c7336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (2480 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (2481 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4a0966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4a0963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4a096762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0eae61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0eae6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0eae61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0eae603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4a08fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4a08fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4a08e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4a0590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4a0590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0eae604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0eae6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0eae6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4a0590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (2482 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c24773eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c24770e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c2477462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f621ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f621ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f621ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f621ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c24709bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c24709a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c246ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c2439de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c2439db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f621ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f621ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f621ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c2439da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (2483 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i # | ... # `---data was truncated (10240/14788) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616c55ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616c55cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616c55cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ca6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ca618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ca6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ca611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616c5564bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616c5564a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616c55498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616c51f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616c51f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ca611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ca611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ca611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616c51f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2484 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6777c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6777bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6777c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cc7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cc758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cc7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cc751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a677758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a677758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a67773d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6773ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6773ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3cc751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cc751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cc751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6773eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (2485 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613b3dcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613b3dc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613b3dcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfeed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfeed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfeed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfeed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613b3d61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613b3d61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613b3d468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613b39f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613b39f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfeed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfeed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfeed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613b39f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (2486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d9341beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d93418e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d9341c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd5881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd588725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd5881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd58803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d933b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d933b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d933968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d93045e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d93045b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd58804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd588050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd588050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d93045a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (2487 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (2488 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (2489 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596eada9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596eada6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596eadaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9c1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9c175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9c1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9c16ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596ead3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596ead3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596ead248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596ea9d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596ea9d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9c16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9c16ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9c16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596ea9d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (2490 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0a72d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0a72cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0a72d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f096a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f096a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f096a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f096a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0a7266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0a7266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0a724b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0a6efae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0a6efab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f096a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f096a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f096a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0a6efaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (2491 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625b8971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625b896ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625b897262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36f3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36f3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36f3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36f3e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625b8907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625b8907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625b88ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625b859be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625b859bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f36f3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36f3e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36f3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625b859ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (2492 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba0a658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba0a655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba0a65962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f218e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f218e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f218e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f218e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba0a5eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba0a5eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba0a5d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba0a282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba0a282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f218e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f218e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f218e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba0a282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (2493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ba4c0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ba4c09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ba4c0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50abb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50abb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50abb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50abb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ba4ba2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ba4ba2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ba4b878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ba4836e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ba4836b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50abb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50abb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50abb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ba4836a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (2494 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (2495 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 # | ... # `---data was truncated (10240/73182) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f72314deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f72314ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f72314e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6d9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6d9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6d9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6d9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7230e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7230e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7230c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f722d77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f722d77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6d9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6d9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6d9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f722d77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (2496 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0044a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c00449de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0044a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2067133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f206718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2067133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f206711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c004436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c004436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c00441b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0040cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0040cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f206711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f206711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f206711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0040caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (2497 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6b1258eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6b1255e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6b125962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd877f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd877f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd877f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd877f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6b11eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6b11eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6b11d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6b0e82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6b0e82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd877f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd877f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd877f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6b0e82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (2498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586401a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586401a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586401aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbed9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbed955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbed9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbed94ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055864013fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055864013fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586401248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055863fdd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055863fdd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbed94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbed94ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbed94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055863fdd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (2499 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efb90b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055efb90b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055efb90b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f434e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f434e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f434e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f434e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efb904bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055efb904ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055efb90308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055efb8cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055efb8cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f434e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f434e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f434e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efb8cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (2500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f71fb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f71fafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f71fb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f455c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f455c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f455c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f455c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f71f48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f71f48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f71f2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f71bdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f71bdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f455c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f455c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f455c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f71bdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (2501 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (2502 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627d441ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627d4419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627d441d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d6f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d6f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d6f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d6f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627d43b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627d43b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627d43978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627d4046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627d4046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d6f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d6f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d6f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627d4046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (2503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac8e15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bac8e12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bac8e1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffae7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffae7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffae7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffae7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac8dabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bac8daba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bac8d908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bac8a3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bac8a3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffae7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffae7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffae7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac8a3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (2504 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3ecf44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a3ecf41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a3ecf4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ff4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ff42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ff4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ff4231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ecedabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3ecedaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3ecebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3ecb6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3ecb6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ff4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ff42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ff42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ecb6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (2505 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563265ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563265ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563265ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7ab31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563265a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563265a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563265a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563265703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563265703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc7ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563265703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (2506 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (2507 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c10572eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c1056fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c1057362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a0ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a0ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a0ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a0ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c10508bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c10508a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c104ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c1019ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c1019cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a0ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a0ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a0ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c1019ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (2508 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmac # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e77d96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e77d93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e77d9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c7641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c764725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c7641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c76403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e77d2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e77d2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e77d118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e779c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e779c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c76404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c764050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c764050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e779c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (2509 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565000e53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565000e50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565000e5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5238649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5238649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5238631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565000de9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565000de9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565000dce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565000a7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565000a7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5238632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52386330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565000a7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (2510 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563d17b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563d17b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563d17b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fdd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fdd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fdd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fdd2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563d174dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563d174da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563d17328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563d13e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563d13e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fdd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fdd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fdd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563d13e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (2511 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1511afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1511ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1511b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5b2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5b218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5b2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5b211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c151145bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c151145a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c15112a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c150dd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c150dd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5b211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5b211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5b211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c150dd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (2512 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i) # | store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i) # | store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i) # | store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i) # | store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i) # | store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i) # | store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i) # | store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i) # | store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i) # | store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i) # | store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i) # | store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i) # | st # | ... # `---data was truncated (10240/16770) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d4e6b1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4e6b1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4e6b1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0346449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0346449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0346431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4e6ab4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4e6ab4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4e6a998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4e6748e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4e6748b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0346432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03464330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4e6748a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (2513 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align # | ... # `---data was truncated (10240/97506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f03be9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f03be6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f03bea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f960d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f960d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f960d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f960d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f03b7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f03b7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f03b648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f03813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f03813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f960d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f960d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f960d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f03813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (2514 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (2515 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056504e947eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056504e944e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056504e94862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bdf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bdf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bdf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bdf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056504e8ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056504e8dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056504e8c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056504e571e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056504e571b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bdf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bdf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bdf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056504e571a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (2516 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e092511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e09250ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e09251262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ca1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ca1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ca1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ca1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0924a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0924a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e09248c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e09213be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e09213bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ca1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ca1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ca1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e09213ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (2517 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 # | ... # `---data was truncated (10240/27063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdf2fcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bdf2fcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bdf2fce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb95d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb95d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb95d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb95d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdf2f63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bdf2f63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bdf2f488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bdf2bf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bdf2bf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb95d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb95d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb95d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdf2bf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (2518 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dc528beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556dc5288e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556dc528c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb524533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb52458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb524533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb52451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dc5221bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556dc5221a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556dc52068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556dc4eb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556dc4eb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb52451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb52451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb52451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dc4eb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (2519 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056311f628eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056311f625e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056311f62962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0da8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0da86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0da8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0da8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056311f5bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056311f5bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056311f5a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056311f252e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056311f252b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0da8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0da86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0da86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056311f252a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (2520 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f61e749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f61e746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f61e74a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcaef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcaef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcaef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcaef31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f61e6dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f61e6dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f61e6c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f61e373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f61e373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcaef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcaef31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcaef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f61e373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (2521 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ # | ... # `---data was truncated (10240/18570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd6a734eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd6a731e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd6a73562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fe0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fe058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fe0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fe051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd6a6cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd6a6caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd6a6af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd6a35ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd6a35eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fe051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fe051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fe051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd6a35ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (2522 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b83c650eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b83c64de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b83c65162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3799a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3799aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3799a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3799a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b83c5e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b83c5e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b83c5cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b83c27ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b83c27ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3799a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3799a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3799a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b83c27aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (2523 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7ba6aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7ba6a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7ba6ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d2a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d2a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d2a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d2a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7ba642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7ba642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7ba6278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7ba2d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7ba2d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d2a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d2a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d2a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7ba2d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (2524 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e55feaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e55fea7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e55feab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f327b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f327b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f327b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f327b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e55fe40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e55fe40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e55fe258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e55fad4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e55fad4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f327b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f327b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f327b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e55fad4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (2525 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fc4071eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fc406ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fc407262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0bc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0bc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0bc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0bc203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fc4007bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fc4007a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fc3fec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fc3c9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fc3c9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0bc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0bc2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0bc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fc3c9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (2526 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639b9bc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639b9bc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639b9bc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb272e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb272ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb272e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb272e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639b9b5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639b9b5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639b9b3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639b97eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639b97eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb272e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb272e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb272e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639b97eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (2527 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (2528 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d9a62eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d9a62be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d9a62f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa931533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa93158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa931533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa93151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d9a5c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d9a5c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d9a5a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d9a258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d9a258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa93151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa93151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa93151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d9a258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (2529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627ec49feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627ec49ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627ec4a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f09533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f0958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f09533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f0951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627ec435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627ec435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627ec41a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627ec0c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627ec0c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f0951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f0951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f0951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627ec0c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (2530 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d27da0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d27d9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d27da162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2db5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2db5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2db5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2db5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d27d36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d27d36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d27d1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d279cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d279cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2db5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2db5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2db5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d279caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2531 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d60a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d60a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d60a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f252e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f252e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f252e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f252e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d60a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d60a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d609f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d606a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d606a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f252e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f252e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f252e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d606a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (2532 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585d410ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585d4109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585d410d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89a6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89a6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89a6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89a6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585d40a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585d40a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585d40878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585d3d36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585d3d36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f89a6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89a6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89a6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585d3d36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (2533 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (2534 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (2535 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d2765ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d27659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d2765d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc6ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc6caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc6ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc6ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d275f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d275f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d275d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d27286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d27286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc6ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc6ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc6ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d27286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (2536 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (2537 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (2538 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (2539 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f5d074eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f5d071e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f5d07562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7375133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f737518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7375133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f737511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f5d00abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f5d00aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f5cfef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f5cc9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f5cc9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f737511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f737511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f737511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f5cc9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (2540 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (2541 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a38b99ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a38b999e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a38b99d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4003049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40030a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4003049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4003031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a38b932bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a38b932a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a38b9178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a38b5c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a38b5c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4003032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40030330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40030330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38b5c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (2542 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603c0898eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603c0895e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603c089962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f136de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f136dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f136de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f136de31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603c082ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603c082ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603c08138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603c04c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603c04c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f136de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f136de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f136de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603c04c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (2543 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | # | ... # `---data was truncated (10240/17536) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557995d37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557995d34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557995d3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8467d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8467d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8467d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8467d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557995ccdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557995ccda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557995cb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557995961e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557995961b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8467d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8467d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8467d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557995961a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2544 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (2545 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee313efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee313ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee313f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd573e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd573ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd573e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd573e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee31385bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee31385a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee3136a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee31019e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee31019b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd573e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd573e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd573e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee31019a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2546 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b58fdbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b58fdbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b58fdbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd90849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd908a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd90849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd90831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b58fd53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b58fd53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b58fd388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b58f9e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b58f9e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd90832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd908330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd908330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b58f9e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (2547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d96026eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d96023e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d9602762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97ce849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97ce8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97ce849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97ce831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d95fbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d95fbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d95fa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d95c50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d95c50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97ce832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97ce8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97ce8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d95c50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (2548 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (2549 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d1a857eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d1a854e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d1a85862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f919eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f919eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f919eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f919eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d1a7edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d1a7eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d1a7d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d1a481e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d1a481b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f919eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f919eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f919eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d1a481a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (2550 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = loa # | ... # `---data was truncated (10240/33443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597d3e67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597d3e64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597d3e6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f28f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f28f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f28f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f28f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597d3dfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597d3dfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597d3de28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597d3a91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597d3a91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f28f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f28f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f28f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597d3a91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (2551 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # | #0 0x000055ae27f7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae27f7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae27f7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ddcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ddcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ddcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ddcb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae27f14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae27f14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae27ef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae27ba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae27ba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ddcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ddcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ddcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae27ba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (2552 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562579e94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562579e91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562579e9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09ed31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562579e2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562579e2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562579e0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562579abee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562579abeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562579abea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (2553 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (2554 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %v # | ... # `---data was truncated (10240/43948) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556afc6e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556afc6e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556afc6e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8df933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8df98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8df933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8df91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556afc679bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556afc679a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556afc65e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556afc30de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556afc30db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8df91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8df91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8df91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556afc30da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (2555 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9c44edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9c44eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9c44ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6313849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63138a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6313849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6313831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9c4483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9c4483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9c44688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9c4117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9c4117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6313832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63138330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63138330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9c4117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (2556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, ali # | ... # `---data was truncated (10240/58334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055765e158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055765e155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055765e15962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcea9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcea9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcea9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcea9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055765e0eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055765e0eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055765e0d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055765dd82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055765dd82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcea9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcea9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcea9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055765dd82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (2557 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv16i8 # | ... # `---data was truncated (10240/215036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a4a24aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a4a247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a4a24b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc94249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc942a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc94249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc94231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a4a1e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a4a1e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a4a1c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a49e74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a49e74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc94232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc942330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc942330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a49e74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2558 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558596996eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558596993e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055859699762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ef3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ef375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ef3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ef36ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055859692cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055859692ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585969118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585965c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585965c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ef36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ef36ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ef36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585965c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (2559 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (2560 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a216fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a216f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a216fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1240933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1240933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a21691bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a21691a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a216768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a21325e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a21325b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f124091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a21325a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2561 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # | #0 0x0000564e70de5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e70de2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e70de662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f488f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f488f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f488f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f488f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e70d7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e70d7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e70d608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e70a0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e70a0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f488f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f488f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f488f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e70a0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (2562 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd83f0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd83f08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd83f0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fd8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fd858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fd8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fd851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd83ea1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd83ea1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd83e868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd83b35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd83b35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fd851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fd851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fd851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd83b35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (2563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626fb2b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626fb2b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626fb2b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a2f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a2f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a2f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a2f431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626fb24cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626fb24ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626fb2318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626faee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626faee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a2f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a2f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a2f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626faee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (2564 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2565 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3801f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3801eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3801f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1486049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1486049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1486031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f380187bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f380187a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f38016c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f37fe1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f37fe1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1486032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14860330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f37fe1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (2566 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055932ae83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055932ae80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055932ae8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff214649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff214649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff214631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055932ae19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055932ae19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055932adfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055932aaade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055932aaadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff214632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2146330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055932aaada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (2567 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055749c27aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055749c277e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055749c27b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055749c210bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055749c210a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055749c1f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055749bea4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055749bea4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ce571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055749bea4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a34dfc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a34dfc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a34dfc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a51449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a514a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a51449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a51431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a34df5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a34df5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a34df418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a34dbf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a34dbf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a51432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a514330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a514330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a34dbf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (2569 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0fff7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0fff7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0fff8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed09a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed09aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed09a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed09a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0fff15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0fff15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0ffefa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0ffba9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0ffba9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed09a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed09a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed09a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0ffba9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (2570 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec7b8b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec7b8b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec7b8b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc2e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc2e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc2e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc2e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec7b84ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec7b84ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec7b8338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec7b4e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec7b4e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc2e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc2e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc2e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec7b4e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (2571 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0b26b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0b26aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0b26b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f830ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f830ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f830ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f830aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0b2647bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0b2647a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0b262c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0b22dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0b22dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f830aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f830aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f830aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0b22dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (2572 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056462f3c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056462f3c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056462f3c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c38d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c38d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c38d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c38d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056462f35cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056462f35ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056462f3418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056462eff0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056462eff0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c38d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c38d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c38d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056462eff0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (2573 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (2574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be97146eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be97143e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be9714762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea52a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea52aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea52a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea52a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be970dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be970dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be970c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be96d70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be96d70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea52a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea52a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea52a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be96d70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2575 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/13255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f489abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f489a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f489ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5434c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5434ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5434c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5434c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f48941bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f48941a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f489268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f485d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f485d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5434c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5434c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5434c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f485d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (2576 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddcafcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ddcafc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ddcafcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2ede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2edea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2ede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2ede31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddcaf60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ddcaf60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ddcaf458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ddcabf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ddcabf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2ede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2ede330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2ede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddcabf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (2577 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vect # | ... # `---data was truncated (10240/24229) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a9e1cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a9e1cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a9e1d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe23cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe23cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe23cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe23cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a9e165bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a9e165a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a9e14a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a9ddf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a9ddf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe23cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe23cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe23cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a9ddf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (2578 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056455e0b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056455e0b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056455e0b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa007533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa00758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa007533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa00751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056455e049bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056455e049a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056455e02e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056455dcdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056455dcddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa00751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa00751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa00751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056455dcdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (2579 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d120037eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d120034e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d12003862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90f3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90f3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90f3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90f3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d11ffcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d11ffcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d11ffb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d11fc61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d11fc61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90f3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90f3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90f3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d11fc61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (2580 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd42c99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd42c96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd42c9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb39933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb3998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb39933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb3991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd42c2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd42c2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd42c148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd428c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd428c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb3991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb3991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb3991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd428c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (2581 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2582 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de3cecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de3cecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de3cece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6fae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de3ce63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de3ce63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de3ce488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de3caf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de3caf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6fae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de3caf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (2583 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1d1f7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1d1f78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1d1f7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8761d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8761d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8761d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8761d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1d1f11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1d1f11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1d1ef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1d1ba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1d1ba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8761d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8761d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8761d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1d1ba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (2584 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (2585 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557caa582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557caa57fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557caa58362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc12a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc12a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc12a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc12a231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557caa518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557caa518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557caa4fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557caa1ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557caa1acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc12a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc12a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc12a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557caa1aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (2586 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_and_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32( %0) # | ret i32 %rdx.and # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.and.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_or_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32( %0) # | ret i32 %rdx.or # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.or.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_xor_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32( %0) # | ret i32 %rdx.xor # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.xor.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smax_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smin_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umax_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umin_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmax_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmax.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmin_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmin.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmaximum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32( %0) # | ret float %rdx.maximum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmaximum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fminimum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32( %0) # | ret float %rdx.minimum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fminimum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32_m8( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv16i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @reduce_add_i64( %a) #0 { # | entry: # | %a.addr = alloca , align 8 # | store %a, ptr %a.addr, align 8 # | %0 = load , ptr %a.addr, align 8 # | %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64( %0) # | ret i64 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vector.reduce.add.nxv1i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_mul_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32( %0) # | ret i32 %rdx.mul # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.mul.nxv2i32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055c0beca7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0beca4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0beca862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c19249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c192a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c19249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c19231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0bec3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0bec3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0bec228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0be8d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0be8d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c19232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c192330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c192330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0be8d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0acac3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0acac0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0acac462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3260733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f326078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3260733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f326071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0aca59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0aca59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0aca3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0ac6ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0ac6edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f326071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f326071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f326071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0ac6eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (2588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e9cbffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e9cbfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e9cc0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f355b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f355b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f355b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f355b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e9cb95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e9cb95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e9cb7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e9c829e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e9c829b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f355b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f355b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f355b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e9c829a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (2589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/64349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e5780feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e5780ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e5781062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b7d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b7d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b7d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b7d4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e577a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e577a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e5778a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e57439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e57439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b7d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b7d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b7d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e57439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (2590 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bdaa10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bdaa0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bdaa1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bcff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bcff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bcff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bcff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bda9a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bda9a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bda98b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bda63ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bda63ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bcff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bcff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bcff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bda63aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (2591 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f55011feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f55011ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f55012062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe39fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe39fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe39fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe39fe03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5500b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5500b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f55009a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f54fd49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f54fd49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe39fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe39fe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe39fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f54fd49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (2592 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bf7ceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558bf7cebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558bf7cef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7823133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f782318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7823133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f782311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bf7c84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558bf7c84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558bf7c698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bf7918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bf7918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f782311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f782311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f782311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bf7918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (2593 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4c02b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4c02b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4c02b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6f0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6f055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6f0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6f04ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4c024cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4c024ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4c02318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4bfee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4bfee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe6f04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6f04ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6f04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4bfee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (2594 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055971c200eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055971c1fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055971c20162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7d6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7d698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7d6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7d691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055971c196bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055971c196a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055971c17b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055971be2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055971be2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7d691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7d691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7d691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055971be2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (2595 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e822df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e822df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e822dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb997d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb997d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb997d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb997d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e822d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e822d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e822d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e822a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e822a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb997d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb997d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb997d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e822a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (2596 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (2597 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625d5b06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625d5b03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625d5b0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7075849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7075849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7075831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625d5a9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625d5a9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625d5a818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625d5730e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625d5730b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7075832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70758330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625d5730a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (2598 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562712f56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562712f53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562712f5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd4521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd452725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd4521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd45203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562712eecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562712eeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562712ed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562712b80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562712b80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd45204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd452050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd452050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562712b80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dee47d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dee47cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dee47d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f914ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f914ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f914ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f914ec03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dee4767bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dee4767a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dee474c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dee43fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dee43fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f914ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f914ec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f914ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dee43fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (2600 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560578d24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560578d21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560578d2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1948a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1948a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1948a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1948a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560578cbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560578cbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560578c9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056057894ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056057894eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1948a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1948a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1948a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056057894ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (2601 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b87b53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b87b50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b87b5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6c1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6c12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6c1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6c1231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b87ae9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b87ae9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b87ace8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b8777de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b8777db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6c1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6c12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6c12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b8777da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (2602 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9832a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9832a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9832a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97dc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97dc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97dc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97dc231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b98323bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b98323ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9832208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b982ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b982ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97dc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97dc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97dc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b982ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055893e40ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055893e409e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055893e40d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3214933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f321498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3214933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f321491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055893e3a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055893e3a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055893e3878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055893e036e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055893e036b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f321491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f321491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f321491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055893e036a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (2604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056020ab86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056020ab83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056020ab8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38f481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38f48725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38f481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38f4803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056020ab1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056020ab1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056020ab018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056020a7b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056020a7b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38f4804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38f48050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38f48050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056020a7b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (2605 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e942445eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e942442e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e94244662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ff8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ff8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ff8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ff8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9423dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9423dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9423c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e94206fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e94206fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ff8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ff8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ff8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e94206fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (2606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637b0dfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637b0df9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637b0dfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8152a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8152aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8152a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8152a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637b0d92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637b0d92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637b0d778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637b0a26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637b0a26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8152a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8152a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8152a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637b0a26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (2607 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cbf152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cbf14fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cbf15362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cbf0e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cbf0e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cbf0cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cbed7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cbed7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efca391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cbed7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (2608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4cbdceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4cbdcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4cbdcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f0d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f0d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f0d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f0d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4cbd64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4cbd64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4cbd498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4cb9f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4cb9f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f0d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f0d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f0d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4cb9f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (2609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652cd52beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652cd528e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652cd52c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdecec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdececa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdecec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdecec31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652cd4c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652cd4c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652cd4a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652cd155e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652cd155b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdecec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdecec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdecec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652cd155a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (2610 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b981725eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b981722e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b98172662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb29b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb29b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb29b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb29b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9816bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9816bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9816a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b98134fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b98134fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb29b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb29b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb29b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b98134fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (2611 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055635eb17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055635eb14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055635eb1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7752133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f775218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7752133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f775211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055635eaadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055635eaada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055635ea928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055635e741e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055635e741b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f775211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f775211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f775211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055635e741a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (2612 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (2613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_ # | ... # `---data was truncated (10240/10440) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a62bb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a62bb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a62bb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f943e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f943e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f943e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f943e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a62b4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a62b4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a62b2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a627dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a627deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f943e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f943e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f943e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a627dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (2614 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627fd172eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627fd16fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627fd17362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50fcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627fd108bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627fd108a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627fd0ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627fcd9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627fcd9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627fcd9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (2615 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/24982) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce85d19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce85d16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce85d1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0217533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f021758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0217533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f021751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce85cafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce85cafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce85c948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce85943e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce85943b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f021751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f021751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f021751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce85943a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (2616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e7ffeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e7ffe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e7ffeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecf3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecf36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecf3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecf3631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e7ff80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e7ff80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e7ff658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e7fc14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e7fc14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecf3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecf36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecf36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e7fc14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (2617 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = l # | ... # `---data was truncated (10240/23247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8cffbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8cffbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8cffbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbfde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbfdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbfde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbfde31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8cff53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8cff53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8cff388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8cfbe7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8cfbe7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbfde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbfde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbfde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8cfbe7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (2618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (2619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055726c192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055726c18fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055726c19362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84a6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84a618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84a6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84a611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055726c128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055726c128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055726c10d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055726bdbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055726bdbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84a611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84a611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84a611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055726bdbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (2620 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be3b9b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be3b9b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be3b9b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f755321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75532725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f755321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7553203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be3b94dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be3b94da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be3b9328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be3b5e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be3b5e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7553204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75532050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75532050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be3b5e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (2621 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (2622 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (2623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a42ddfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a42ddce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a42de062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a68a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a68aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a68a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a68a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a42d75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a42d75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a42d5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a42a09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a42a09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a68a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a68a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a68a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a42a09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (2624 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtin-align.c (2625 of 27910) ******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | @aligned_true = global i8 1, align 1 # | @aligned_false = global i8 0, align 1 # | @down_1 = global i32 992, align 4 # | @down_2 = global i32 256, align 4 # | @up_1 = global i32 1024, align 4 # | @up_2 = global i32 256, align 4 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @get_type() #0 { # | entry: # | ret ptr null # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %src_addr = ptrtoint ptr %0 to i64 # | %set_bits = and i64 %src_addr, %mask # | %is_aligned = icmp eq i64 %set_bits, 0 # | ret i1 %is_aligned # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005630db6e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630db6e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630db6e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe645333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe64538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe645333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe64531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630db67abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630db67aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630db65f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630db30ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630db30eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe64531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe64531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe64531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630db30ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (2626 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 # | ... # `---data was truncated (10240/14429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649196bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649196b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649196bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f602e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f602e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f602e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f602e8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564919652bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564919652a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649196378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649192e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649192e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f602e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f602e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f602e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649192e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (2627 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1 # | ... # `---data was truncated (10240/26772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5c6736eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5c6733e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5c673762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fd3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fd3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fd3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fd3a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5c66ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5c66cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5c66b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5c6360e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5c6360b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fd3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fd3a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fd3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5c6360a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (2628 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (2629 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ef6ec4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ef6ec1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ef6ec562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aaf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aaf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aaf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aaf231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ef6e5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ef6e5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ef6e3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ef6aeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ef6aeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6aaf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aaf2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aaf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ef6aeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (2630 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9768e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9768e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9768e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a6b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a6b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a6b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a6b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f97687ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f97687ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9768638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f976512e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f976512b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a6b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a6b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a6b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f976512a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (2631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ce4094eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ce4091e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ce409562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f616b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f616b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f616b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f616b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ce402abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ce402aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ce400f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ce3cbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ce3cbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f616b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f616b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f616b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ce3cbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (2632 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643396ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643396cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643396cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc3df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc3df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc3df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc3df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564339664bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564339664a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643396498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643392f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643392f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc3df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc3df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc3df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643392f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (2633 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055756b004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055756b001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055756b00562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcaa1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcaa14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcaa1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcaa1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055756af9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055756af9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055756af7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055756ac2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055756ac2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcaa1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcaa14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcaa14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055756ac2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (2634 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0d45e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0d45e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0d45e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8573449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8573449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8573431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0d457dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0d457da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0d45628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0d4211e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0d4211b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8573432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85734330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0d4211a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (2635 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (2636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d57e591eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d57e58ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d57e59262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cb9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cb9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cb9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cb9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d57e527bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d57e527a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d57e50c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d57e1bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d57e1bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cb9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cb9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cb9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d57e1bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (2637 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601af57beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601af578e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601af57c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80cf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601af511bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601af511a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601af4f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601af1a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601af1a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601af1a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (2638 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557512efceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557512ef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557512efd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd6b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd6b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd6b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd6b831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557512e92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557512e92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557512e778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557512b26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557512b26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd6b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd6b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd6b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557512b26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2639 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b2990deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b2990ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b2990e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cbe41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cbe4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cbe41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cbe403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b298a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b298a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b298888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b29537e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b29537b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cbe404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cbe4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cbe4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b29537a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (2640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056374dbcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056374dbc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056374dbcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43ed649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43ed6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43ed649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43ed631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056374db62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056374db62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056374db478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056374d7f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056374d7f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43ed632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43ed6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43ed6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056374d7f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (2641 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c220049eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c220046e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c22004a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbae4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbae46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbae4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbae4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c21ffdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c21ffdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c21ffc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c21fc73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c21fc73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbae4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbae46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbae46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c21fc73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (2642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-unknown-linux-gnu" # | # | @__riscv_cpu_model = external dso_local global { i32, i64, i64 } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1808 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372035378380799 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 1152921505839391232 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775800 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 102892581 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775543 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 337970694 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f859d68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f859d65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f859d6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ab4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ab4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ab4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ab4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f859cfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f859cfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f859ce38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f859992e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f859992b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ab4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ab4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ab4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f859992a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (2643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d439433eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d439430e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d43943462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f035d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f035d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f035d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f035d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4393c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4393c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4393ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d43905de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d43905db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f035d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f035d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f035d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d43905da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (2644 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9d28caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9d28c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9d28cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3baa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9d2860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9d2860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9d28458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9d24f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9d24f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff3baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3baa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9d24f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (2645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i # | ... # `---data was truncated (10240/51295) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561dc0984eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561dc0981e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561dc098562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4132305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f413235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4132305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41322ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dc091abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561dc091aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561dc08ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561dc05aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561dc05aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41322eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41322ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41322ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dc05aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562762653eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562762650e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056276265462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa512f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa512f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa512f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa512eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627625e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627625e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627625ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056276227de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056276227db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa512eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa512eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa512eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056276227da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (2647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602c6aa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602c6aa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602c6aa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe68ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe68ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe68ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe68ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602c6a3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602c6a3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602c6a218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602c66d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602c66d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe68ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe68ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe68ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602c66d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-riscv.c (2648 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 10, ptr %res, align 4 # | store volatile i32 11, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c31d1c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c31d1c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c31d1ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1ad249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1ad2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1ad249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1ad231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c31d15fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c31d15fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c31d1448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c31cdf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c31cdf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1ad232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1ad2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1ad2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c31cdf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (2649 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6ddcc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6ddcc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6ddcc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20b3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20b375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20b3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20b36ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6ddc5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6ddc5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6ddc418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6dd8f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6dd8f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f20b36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20b36ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20b36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6dd8f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (2650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6f2129eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6f2126e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6f212a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6123133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f612318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6123133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f612311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6f20bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6f20bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6f20a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6f1d53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6f1d53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f612311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f612311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f612311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6f1d53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-arm64.c (2652 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load ptr, ptr %b.addr, align 8 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @tp() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbitl(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.bitreverse.i64(i64) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbit64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @hints() #0 { # | entry: # | call void @llvm.aarch64.hint(i32 0) # | call void @llvm.aarch64.hint(i32 1) # | call void @llvm.aarch64.hint(i32 2) # | call void @llvm.aarch64.hint(i32 3) # | call void @llvm.aarch64.hint(i32 4) # | call void @llvm.aarch64.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.aarch64.hint(i32) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @barriers() #0 { # | entry: # | call void @llvm.aarch64.dmb(i32 1) # | call void @llvm.aarch64.dsb(i32 2) # | call void @llvm.aarch64.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dmb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dsb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.isb(i32) #5 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch_x() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @read_intent_prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch.ir(ptr null) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @jcvt(double noundef %v) #7 { # | entry: # | %v.addr = alloca double, align 8 # | store double %v, ptr %v.addr, align 8 # | %0 = load double, ptr %v.addr, align 8 # | %1 = call i32 @llvm.aarch64.fjcvtzs(double %0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.fjcvtzs(double) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rsr() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = trunc i64 %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nounwind # | declare i64 @llvm.read_volatile_register.i64(metadata) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rsr64() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @rsrp() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = inttoptr i64 %0 to ptr # | ret ptr %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %1 = zext i32 %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: nocallback nounwind # | declare void @llvm.write_register.i64(metadata, i64) #8 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr64(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | call void @llvm.write_register.i64(metadata !7, i64 %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsrp(ptr noundef %v) #0 { # | entry: # | %v.addr = alloca ptr, align 8 # | store ptr %v, ptr %v.addr, align 8 # | %0 = load ptr, ptr %v.addr, align 8 # | %1 = ptrtoint ptr %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cls(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %cls = call i32 @llvm.aarch64.cls(i32 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsl(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls64(i64) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsll(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndr(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndr() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndr() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndrrs() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndrrs() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @trap() #0 { # | entry: # | call void @llvm.aarch64.break(i32 42) # | ret void # | } # | # | ; Function Attrs: cold noreturn nounwind # | declare void @llvm.aarch64.break(i32 immarg) #10 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca i64, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8 # | %2 = load ptr, ptr %a.addr, align 8 # | %3 = load i64, ptr %b.addr, a # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 243 | __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint # | | ^ ~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type] # | 305 | __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type] # | 306 | __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type] # | 307 | __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH); # | | ^ ~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 308 | return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5); # | | ^ ~ # | 5 warnings generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bcf478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bcf475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bcf47962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18dc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18dc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18dc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18dc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bcf40ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bcf40ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bcf3f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bcf0a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bcf0a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18dc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18dc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18dc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bcf0a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (2653 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv # | ... # `---data was truncated (10240/53548) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640f038feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640f038ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640f039062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a78333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a7838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a78333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a7831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640f0325bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640f0325a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640f030a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640effb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640effb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a7831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a7831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a7831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640effb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (2654 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf670daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf670d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf670db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79d1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79d1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79d1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79d1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf67070bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf67070a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf670558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf66d04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf66d04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f79d1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79d1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79d1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf66d04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (2655 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f71d5b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f71d5ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f71d5b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cadea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cade31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f71d546bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f71d546a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f71d52b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f71d1dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f71d1dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cade330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f71d1daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (2656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056247f7d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056247f7d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056247f7d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efff0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efff0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efff0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efff0eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056247f76abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056247f76aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056247f74f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056247f3fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056247f3feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efff0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efff0eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efff0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056247f3fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (2657 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,10 # | ... # `---data was truncated (10240/48393) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056050c63feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056050c63ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056050c64062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b5af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056050c5d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056050c5d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056050c5ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056050c269e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056050c269b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056050c269a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2658 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fc6edfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fc6edce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fc6ee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f695f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f695f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f695f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f695f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fc6e75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fc6e75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fc6e5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fc6b09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fc6b09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f695f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f695f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f695f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fc6b09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (2659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d37f3f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d37f3f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d37f3f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f621cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f621cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f621cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f621cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d37f38ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d37f38ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d37f3738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d37f022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d37f022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f621cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f621cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f621cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d37f022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (2660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571908deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571908dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571908df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b22c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b22ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b22c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b22c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557190874bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557190874a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571908598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557190508e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557190508b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b22c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b22c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b22c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557190508a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, al # | ... # `---data was truncated (10240/26756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564525f81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564525f7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564525f8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0593f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0593f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0593f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0593f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564525f17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564525f17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564525efc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564525babe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564525babb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0593f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0593f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0593f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564525baba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (2662 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558426a76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558426a73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558426a7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff423249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4232a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff423249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff423231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558426a0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558426a0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584269f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584266a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584266a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff423232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4232330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4232330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584266a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (2663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb0b084eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb0b081e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb0b08562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7753733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f775378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7753733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f775371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb0b01abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb0b01aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb0afff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb0acaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb0acaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f775371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f775371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f775371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb0acaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (2664 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = or <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = or <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = or <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = or <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32 # | ... # `---data was truncated (10240/10897) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0549fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0549f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0549fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb51b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb51b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb51b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb51b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d054991bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d054991a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0549768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d054625e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d054625b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb51b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb51b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb51b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d054625a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (2665 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.ad # | ... # `---data was truncated (10240/16274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfd7db6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfd7db3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfd7db762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddb5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddb558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddb5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddb551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfd7d4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfd7d4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfd7d318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfd79e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfd79e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddb551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddb551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddb551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfd79e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (2666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599bdd22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599bdd1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599bdd2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7e8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599bdcb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599bdcb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599bdc9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599bd94ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599bd94cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7e8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599bd94ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (2667 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056214b000eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056214affde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056214b00162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44d111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056214af96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056214af96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056214af7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056214ac2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056214ac2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44d111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056214ac2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (2668 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/18595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8f579eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8f579be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8f579f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc47ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc47ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc47ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc47aced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8f5734bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8f5734a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8f57198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8f53c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8f53c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc47aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc47acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc47acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8f53c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (2669 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65738deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f65738ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f65738e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67e6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67e66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67e6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67e6631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f657323bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f657323a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6573088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f656fb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f656fb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67e6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67e66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67e66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f656fb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (2670 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.ris # | ... # `---data was truncated (10240/12914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1fa788eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1fa785e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1fa78962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c77533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c7758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c77533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c7751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1fa71ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1fa71ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1fa7038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1fa3b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1fa3b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c7751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c7751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c7751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1fa3b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (2671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619fbd81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619fbd7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619fbd8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6388c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6388ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6388c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6388c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619fbd17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619fbd17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619fbcfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619fb9abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619fb9abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6388c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6388c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6388c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619fb9aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (2672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2673 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055978beddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055978bedae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055978bede62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7551e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7551ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7551e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7551e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055978be73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055978be73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055978be588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055978bb07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055978bb07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7551e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7551e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7551e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055978bb07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (2674 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636c73c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636c73c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636c73c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27f2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27f28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27f2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27f2831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636c735dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636c735da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636c73428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636c6ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636c6ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27f2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27f28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27f28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636c6ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (2675 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572d6c68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572d6c65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572d6c6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb17ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb17ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb17ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb17ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572d6bfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572d6bfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572d6be38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572d6892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572d6892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb17ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb17ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb17ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572d6892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (2676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/29319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e8db5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e8db5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e8db6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6a7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6a7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6a7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6a7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e8daf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e8daf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e8dada8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e8d789e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e8d789b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6a7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6a7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6a7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e8d789a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (2677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555628122eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055562811fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055562812362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc892333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc89238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc892333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc89231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556280b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556280b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055562809d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555627d4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555627d4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc89231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc89231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc89231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555627d4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (2678 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c33d99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c33d96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c33d9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fe2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fe215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fe2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fe20ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c33d2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c33d2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c33d148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c339c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c339c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fe20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fe20ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fe20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c339c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (2679 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4fc841eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4fc83ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4fc84262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effae31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4fc7d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4fc7d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4fc7bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4fc46be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4fc46bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effae31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4fc46ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (2680 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056374a29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056374a297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056374a29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8abdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8abdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8abdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8abdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056374a230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056374a230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056374a2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563749ec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563749ec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8abdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8abdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8abdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563749ec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (2681 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a646faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a646f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a646fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc89933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc8998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc89933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc8991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a64690bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a64690a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a646758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a64324e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a64324b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc8991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc8991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc8991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a64324a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (2682 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562aab431eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562aab42ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562aab43262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8830d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8830d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8830d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8830d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aab3c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562aab3c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562aab3ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562aab05be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562aab05bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8830d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8830d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8830d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aab05ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (2683 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64 # | ... # `---data was truncated (10240/29259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f092895eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f092892e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f09289662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bd4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bd438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bd4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bd431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f09282bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f09282ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0928108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0924bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0924bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bd431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bd431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bd431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0924bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (2684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560509dd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560509dd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560509dd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd266933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd26698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd266933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd26691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560509d6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560509d6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560509d4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605099fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605099feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd26691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd26691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd26691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605099fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (2685 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622374dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622374dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622374e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b16333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b1638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b16333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b1631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562237475bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562237475a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056223745a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562237109e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562237109b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b1631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b1631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b1631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562237109a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (2686 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055563a9beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055563a9bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055563a9bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd06c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd06c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd06c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd06c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055563a954bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055563a954a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055563a9398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055563a5e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055563a5e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd06c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd06c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd06c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055563a5e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (2687 of 27910) ******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c" # | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128" # | target triple = "i386-apple-darwin10" # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke_copy_to_stack() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 { # | entry: # | %that.addr = alloca ptr, align 4 # | %methodIndex.addr = alloca i32, align 4 # | %paramCount.addr = alloca i32, align 4 # | %params.addr = alloca ptr, align 4 # | store ptr %that, ptr %that.addr, align 4 # | store i32 %methodIndex, ptr %methodIndex.addr, align 4 # | store i32 %paramCount, ptr %paramCount.addr, align 4 # | store ptr %params, ptr %params.addr, align 4 # | call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2 # | ret void # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" } # | attributes #1 = { nounwind } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"NumRegisterParameters", i32 0} # | !1 = !{!"clang version 24.0.0"} # | !2 = !{i64 1623} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # | #0 0x000055a233e86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a233e83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a233e8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff04f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff04f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff04f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff04f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a233e1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a233e1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a233e018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a233ab0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a233ab0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff04f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff04f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff04f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a233ab0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (2688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e49f910eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e49f90de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e49f91162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e94f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e94f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e94f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e94f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e49f8a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e49f8a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e49f88b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e49f53ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e49f53ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e94f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e94f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e94f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e49f53aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (2689 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.r # | ... # `---data was truncated (10240/53678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc13a5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc13a5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc13a5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24c7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc139f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc139f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc139d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc13687e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc13687b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f24c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24c72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc13687a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (2690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.n # | ... # `---data was truncated (10240/33624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2652bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2652b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2652bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f485c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f485c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f485c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f485c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a265251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a265251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2652368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a264ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a264ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f485c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f485c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f485c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a264ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (2691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d2046beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d20468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d2046c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f026141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02614725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f026141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0261403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d20401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d20401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d203e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d20095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d20095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0261404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02614050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02614050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d20095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (2692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561628f2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561628f28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561628f2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ba2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ba2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ba2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ba2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561628ec1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561628ec1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561628ea68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561628b55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561628b55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ba2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ba2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ba2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561628b55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (2693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f40aeeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f40aeebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f40aeef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8629933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f862998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8629933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f862991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f40ae84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f40ae84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f40ae698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f40ab18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f40ab18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f862991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f862991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f862991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f40ab18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (2694 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2d661feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2d661ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2d662062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f923f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f923f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f923f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f923f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2d65b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2d65b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2d659a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2d6249e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2d6249b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f923f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f923f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f923f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2d6249a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (2695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0ce677eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0ce674e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0ce67862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4c0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4c038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4c0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4c031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0ce60dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0ce60da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0ce5f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0ce2a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0ce2a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4c031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4c031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4c031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0ce2a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (2696 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560576264eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560576261e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056057626562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0811c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0811ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0811c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0811c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605761fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605761faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605761df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560575e8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560575e8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0811c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0811c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0811c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560575e8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (2697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d2e143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d2e140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d2e14462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1eda333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1eda38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1eda333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1eda31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d2e0d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d2e0d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d2e0be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d2dd6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d2dd6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1eda31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1eda31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1eda31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d2dd6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (2698 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6857e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6857e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6857ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f064f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f064f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f064f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f064f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d68577fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d68577fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6857648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d685413e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d685413b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f064f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f064f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f064f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d685413a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (2699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ecb9cc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ecb9cbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ecb9cc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e7b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e7b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e7b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e7b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ecb9c58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ecb9c58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ecb9c3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ecb98ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ecb98ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e7b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e7b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e7b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ecb98eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (2700 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align # | ... # `---data was truncated (10240/39627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dd1306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564dd1303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564dd130762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dd129cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dd129ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dd12818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564dd0f30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564dd0f30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dd0f30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (2701 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642d4db5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642d4db2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642d4db662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab72133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab7218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab72133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab7211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642d4d4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642d4d4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642d4d308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642d49dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642d49dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab7211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab7211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab7211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642d49dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (2702 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (2703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align # | ... # `---data was truncated (10240/10944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055561014feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055561014ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055561015062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2608b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2608b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2608b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2608b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556100e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556100e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556100ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055560fd79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055560fd79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2608b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2608b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2608b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055560fd79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (2704 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557668d1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557668d17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557668d1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3af8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3af898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3af8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3af891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557668cb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557668cb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557668c958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557668944e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557668944b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3af891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3af891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3af891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557668944a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (2705 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556946003eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556946000e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055694600462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf7cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf7cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf7cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf7cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556945f99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556945f99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556945f7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556945c2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556945c2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf7cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf7cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf7cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556945c2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (2706 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645559b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645559ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645559b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feff1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feff1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feff1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feff1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564555946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564555946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056455592b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645555dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645555dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feff1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feff1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feff1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645555daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (2707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565475e86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565475e83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565475e8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb80f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb80f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb80f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb80f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565475e1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565475e1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565475e018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565475ab0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565475ab0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb80f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb80f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb80f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565475ab0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (2708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/12688) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e42182deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e42182ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e42182e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1561705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f156175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1561705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15616ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4217c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4217c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4217a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e421457e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e421457b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15616eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15616ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15616ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e421457a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (2709 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056336c9d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056336c9cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056336c9d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28e101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28e10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28e101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28e1003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056336c967bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056336c967a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056336c94c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056336c5fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056336c5fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28e1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28e10050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28e10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056336c5fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (2710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdccdbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bdccdbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bdccdbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8e5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8e5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8e5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8e5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdccd54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bdccd54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bdccd398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bdcc9e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bdcc9e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8e5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8e5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8e5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdcc9e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (2711 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align # | ... # `---data was truncated (10240/39416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1b4f33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1b4f30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1b4f3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2111d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2111d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2111d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2111d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1b4ec9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1b4ec9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1b4eae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1b4b5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1b4b5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2111d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2111d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2111d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1b4b5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (2712 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056051e306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056051e303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056051e30762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66a1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66a1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66a1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66a1aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056051e29cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056051e29ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056051e2818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056051df30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056051df30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f66a1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66a1aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66a1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056051df30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (2713 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555598cbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555598cb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555598cbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07aab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07aab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07aab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07aab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555598c52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555598c52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555598c378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555988e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555988e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f07aab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07aab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07aab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555988e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2714 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/18873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560be021ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560be0219e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560be021d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f008e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f008e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f008e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f008e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560be01b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560be01b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560be01978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560bdfe46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560bdfe46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f008e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f008e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f008e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bdfe46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (2715 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri # | ... # `---data was truncated (10240/20523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0bbf27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0bbf24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0bbf2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c3a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c3a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c3a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c3a803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0bbebdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0bbebda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0bbea28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0bbb51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0bbb51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c3a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c3a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c3a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0bbb51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (2716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f63c99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f63c96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f63c9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f55705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f5575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f55705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f556ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f63c2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f63c2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f63c148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f638c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f638c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f556eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f556ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f556ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f638c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (2717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/12652) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056509bf92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056509bf8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056509bf9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8705133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f870518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8705133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f870511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056509bf28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056509bf28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056509bf0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056509bbbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056509bbbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f870511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f870511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f870511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056509bbbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (2718 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563faf547eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563faf544e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563faf54862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1f691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563faf4ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563faf4dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563faf4c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563faf171e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563faf171b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1f691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563faf171a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2719 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560689d14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560689d11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560689d1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f868f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f868f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f868f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f868f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560689caabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560689caaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560689c8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056068993ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056068993eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f868f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f868f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f868f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056068993ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (2720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579e0345eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579e0342e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579e034662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcac049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcac0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcac049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcac031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579e02dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579e02dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579e02c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579dff6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579dff6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdcac032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcac0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcac0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579dff6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (2721 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7d74ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7d74fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7d750062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8860e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8860ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8860e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8860e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7d7495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7d7495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7d747a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7d7129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7d7129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8860e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8860e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8860e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7d7129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (2722 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s0, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x i32> # | %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 # | ... # `---data was truncated (10240/18482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e302e59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e302e56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e302e5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9f6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9f615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9f6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9f60ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e302defbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e302defa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e302dd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e302a83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e302a83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9f60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9f60ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9f60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e302a83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (2723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3f376ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b3f3769e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3f376d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70b1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70b18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70b1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70b1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3f3702bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b3f3702a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3f36e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3f3396e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3f3396b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70b1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70b18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70b18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3f3396a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (2724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564176d84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564176d81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564176d8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8235c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8235ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8235c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8235c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564176d1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564176d1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564176cff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641769aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641769aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8235c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8235c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8235c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641769aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (2725 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (2726 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load p # | ... # `---data was truncated (10240/28353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e45de79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e45de76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e45de7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd3c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd3c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd3c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd3c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e45de0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e45de0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e45ddf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e45daa3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e45daa3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd3c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd3c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd3c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e45daa3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (2727 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | s # | ... # `---data was truncated (10240/280209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624209f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624209f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624209f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f236b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f236b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f236b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f236b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056242098abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056242098aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056242096f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056242061ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056242061eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f236b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f236b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f236b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056242061ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (2728 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/135337) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586bc0feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586bc0fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586bc0ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7028d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7028d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7028d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7028d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586bc094bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586bc094a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586bc0798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586bbd28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586bbd28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7028d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7028d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7028d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586bbd28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (2729 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfa8d30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfa8d2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfa8d3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb605049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb605049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb605031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfa8cc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfa8cc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfa8cab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfa895ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfa895ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb605032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6050330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfa895aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (2730 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a40defeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a40dece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a40df062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a29505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a2955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a29505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a294ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a40d85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a40d85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a40d6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a40a19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a40a19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a294eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a294ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a294ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a40a19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (2731 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/81507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055934f83beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055934f838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055934f83c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaee705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaee75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaee705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaee6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055934f7d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055934f7d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055934f7b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055934f465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055934f465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaee6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaee6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaee6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055934f465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2732 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b09c54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b09c51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b09c5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0280b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0280b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0280b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0280b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b09beabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b09beaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b09bcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b0987ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b0987eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0280b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0280b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0280b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b0987ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (2733 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, # | ... # `---data was truncated (10240/157475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056490f9d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056490f9cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056490f9d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c3ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c3ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c3ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c3ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056490f967bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056490f967a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056490f94c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056490f5fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056490f5fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c3ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c3ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c3ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056490f5fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (2734 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (2735 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055749b053eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055749b050e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055749b05462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54ea41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54ea4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54ea41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54ea403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055749afe9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055749afe9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055749afce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055749ac7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055749ac7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54ea404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54ea4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54ea4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055749ac7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (2736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056363c604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056363c601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056363c60562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bf3d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bf3d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bf3d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bf3ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000056363c59abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056363c59aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056363c57f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056363c22ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056363c22eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bf3ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bf3cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bf3cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363c22ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (2737 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-dot-product.c (2738 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 8 # | %__s0_827 = alloca <4 x i32>, align 8 # | %__s1_827 = alloca <16 x i8>, align 8 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x i32>, align 8 # | %tmp2 = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0_827, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %1, ptr %__s1_827, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 8 # | %4 = load <16 x i8>, ptr %__s1_827, align 8 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (2739 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056450ceb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056450ceb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056450ceb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd629d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd629d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd629d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd629d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056450ce4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056450ce4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056450ce328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056450cae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056450cae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd629d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd629d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd629d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056450cae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2740 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noin # | ... # `---data was truncated (10240/25042) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b76b45beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b76b458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b76b45c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f31e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f31ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f31e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f31e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b76b3f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b76b3f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b76b3d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b76b085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b76b085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f31e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f31e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f31e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b76b085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (2741 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584ffd50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584ffd4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584ffd5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a4c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a4c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a4c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a4c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584ffce6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584ffce6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584ffccb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584ff97ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584ff97ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a4c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a4c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a4c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584ff97aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto_backend.ll (2742 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # | #0 0x00005641c93a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641c93a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641c93a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c53249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c53249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c53231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641c9339bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641c9339a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641c931e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641c8fcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641c8fcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c53232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c532330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641c8fcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (2743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560570aa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560570a9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560570aa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7814f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7814f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7814f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7814f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560570a38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560570a38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560570a1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605706cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605706ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7814f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7814f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7814f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605706cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (2744 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565510b5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565510b57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565510b5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51a6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51a658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51a6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51a651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565510af0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565510af0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565510ad58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565510784e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565510784b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51a651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51a651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51a651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565510784a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (2745 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (2746 of 27910) ******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc | not grep _foo2 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @bar() #0 { # | entry: # | call void @foo2() # | ret void # | } # | # | declare void @foo2() #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # | #0 0x000055929bcebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055929bce8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055929bcec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2623e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2623ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2623e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2623e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055929bc81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055929bc81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055929bc668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055929b915e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055929b915b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2623e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2623e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2623e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055929b915a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: llc # executed command: not grep _foo2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a538006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a538003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a53800762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91ad21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91ad2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91ad21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91ad203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a537f9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a537f9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a537f818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a537c30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a537c30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91ad204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91ad2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91ad2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a537c30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (2748 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aad22e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aad22dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aad22e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f454d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f454d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f454d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f454d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aad2278bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aad2278a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aad225d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aad1f0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aad1f0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f454d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f454d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f454d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aad1f0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (2749 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652fdcf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652fdcf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652fdcf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb530c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb530c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb530c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb530c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652fdc8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652fdc8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652fdc718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652fd920e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652fd920b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb530c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb530c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb530c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652fd920a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (2750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @test_vlenb() #0 { # | entry: # | %0 = call i32 @llvm.read_register.i32(metadata !4) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.read_register.i32(metadata) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"vlenb"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x00005591fcf7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591fcf7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591fcf7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd76849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd76849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd76831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591fcf13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591fcf13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591fcef88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591fcba7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591fcba7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd76832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd768330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591fcba7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (2751 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608e84b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608e84b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608e84b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f990dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f990dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f990dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f990dc03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608e844ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608e844ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608e84338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608e80e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608e80e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f990dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f990dc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f990dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608e80e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (2752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7bb648eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7bb645e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7bb64962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7bb5debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7bb5dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7bb5c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7bb272e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7bb272b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7bb272a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (2753 of 27910) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1 # | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615e168eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615e168be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615e168f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f772c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f772c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f772c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f772c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615e1624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615e1624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615e16098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615e12b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615e12b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f772c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f772c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f772c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615e12b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (2754 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca270eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca270e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca270ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29fc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca27082bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca27082a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca270678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca26d16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca26d16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29fc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca26d16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (2755 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055743b60deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055743b60ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055743b60e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a0db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a0db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a0db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a0daed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055743b5a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055743b5a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055743b5888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055743b237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055743b237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a0daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a0daef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a0daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055743b237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (2756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b79f999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b79f996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b79f99a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f282b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f282b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f282b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f282b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b79f92fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b79f92fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b79f9148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b79f5c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b79f5c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f282b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f282b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f282b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b79f5c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (2757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce42f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce42f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce42f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefdfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefdfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefdfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefdfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce42f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce42f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce42f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce42bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce42bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fefdfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefdfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefdfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce42bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (2758 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056547f106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056547f103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056547f10762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d6b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d6b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d6b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d6b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056547f09cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056547f09ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056547f0818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056547ed30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056547ed30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d6b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d6b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d6b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056547ed30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (2759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d71e873eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d71e870e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d71e87462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc417333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc41738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc417333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc41731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d71e809bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d71e809a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d71e7ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d71e49de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d71e49db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc41731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc41731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc41731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d71e49da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (2760 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (2761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (2762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (2763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056545c6bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056545c6b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056545c6bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b54133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b5418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b54133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b5411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056545c651bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056545c651a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056545c6368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056545c2e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056545c2e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b5411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b5411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b5411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056545c2e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (2764 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (2765 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = # | ... # `---data was truncated (10240/19190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c13e375eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c13e372e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c13e37662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9715049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9715049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9715031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c13e30bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c13e30ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c13e2f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c13df9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c13df9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9715032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97150330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c13df9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (2766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be19ab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be19ab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be19ab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca75733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca7578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca75733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca7571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be19a4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be19a4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be19a318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be196e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be196e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca7571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca7571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca7571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be196e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (2767 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dd77d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559dd77d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559dd77d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb907f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb907f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb907f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb907f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dd776cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559dd776ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559dd77518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559dd7400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559dd7400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb907f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb907f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb907f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dd7400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (2768 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | # | ... # `---data was truncated (10240/135119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc74dbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc74dbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc74dbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd673c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd673c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd673c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd673c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc74d53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc74d53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc74d388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc749e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc749e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd673c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd673c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd673c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc749e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (2769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564686ea8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564686ea5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564686ea962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f177f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f177f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f177f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f177f631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564686e3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564686e3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564686e238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564686ad2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564686ad2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f177f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f177f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f177f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564686ad2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/12433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572ccfe1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572ccfdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572ccfe262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7da5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7da5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7da5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7da5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572ccf77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572ccf77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572ccf5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572ccc0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572ccc0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7da5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7da5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7da5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572ccc0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (2771 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcdec08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcdec05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcdec0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5001d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5001d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5001d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5001ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcdeb9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcdeb9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcdeb838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcde832e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcde832b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5001ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5001cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5001cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcde832a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2772 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbee101eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbee0fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbee10262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea2aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea2aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea2aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea2aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbee097bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbee097a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbee07c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbedd2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbedd2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea2aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea2aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea2aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbedd2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2773 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, alig # | ... # `---data was truncated (10240/32578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563186426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563186423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056318642762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05cac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631863bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631863bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631863a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563186050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563186050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05cac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563186050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (2774 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9a83daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9a83d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9a83db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3824e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3824ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3824e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3824e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9a8370bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9a8370a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9a83558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9a8004e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9a8004b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3824e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3824e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3824e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9a8004a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (2775 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005651eb275eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005651eb272e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005651eb27662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8697533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f869758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8697533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f869751b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651eb20bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651eb20ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651eb1f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651eae9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651eae9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f869751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f869751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f869751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651eae9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (2776 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fafb76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fafb73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fafb7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7e1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7e14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7e1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7e1431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fafb0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fafb0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fafaf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558faf7a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558faf7a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7e1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7e14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7e14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558faf7a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (2777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4c0ab7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4c0ab4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4c0ab862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd58ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd58ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd58ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd58ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4c0a4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4c0a4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4c0a328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4c06e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4c06e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd58ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd58ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd58ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4c06e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (2778 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642192a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056421929fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642192a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae9af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564219238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564219238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056421921d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564218ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564218eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564218ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (2779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559983565eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559983562e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055998356662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55d7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55d718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55d7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55d711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599834fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599834fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599834e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055998318fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055998318fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55d711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55d711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55d711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055998318fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Fun # | ... # `---data was truncated (10240/40883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcbd2b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcbd2b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcbd2b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0030133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f003018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0030133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f003011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcbd24abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcbd24aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcbd22f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcbcedee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcbcedeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f003011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f003011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f003011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcbcedea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (2781 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056109e46beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056109e468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056109e46c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff870b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff870b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff870b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff870b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056109e401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056109e401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056109e3e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056109e095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056109e095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff870b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff870b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff870b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056109e095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (2782 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd9b380eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd9b37de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd9b38162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59eaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59eaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59eaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59eaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd9b316bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd9b316a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd9b2fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd9afaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd9afaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59eaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59eaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59eaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd9afaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (2783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( po # | ... # `---data was truncated (10240/50898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd9ec53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd9ec50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd9ec5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1837133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1837133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd9ebe9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd9ebe9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd9ebce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd9e87de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd9e87db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f183711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd9e87da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (2784 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b31afd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b31afcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b31afd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b31af68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b31af68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b31af4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b31abfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b31abfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1c191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b31abfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (2785 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653fa7a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653fa7a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653fa7a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7065e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7065ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7065e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7065e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653fa73dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653fa73da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653fa7228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653fa3d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653fa3d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7065e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7065e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7065e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653fa3d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (2786 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607682fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607682fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607682fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c0b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c0b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c0b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c0b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560768293bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560768293a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607682788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560767f27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560767f27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c0b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c0b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c0b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560767f27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (2787 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = mul <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = mul <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = mul <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fmul <4 x float> %0, %1 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.m # | ... # `---data was truncated (10240/21288) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055dcbeacfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcbeacce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcbead062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cceb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cceb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cceb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cceb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcbea65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcbea65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcbea4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcbe6f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcbe6f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cceb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cceb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cceb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcbe6f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (2788 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.srshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nos # | ... # `---data was truncated (10240/11578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a892074eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a892071e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a89207562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc923a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc923aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc923a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc923a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a89200abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a89200aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a891fef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a891c9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a891c9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc923a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc923a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc923a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a891c9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (2789 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cb349deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cb349ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cb349e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe61ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe61baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe61ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe61ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cb3433bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cb3433a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cb34188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cb30c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cb30c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe61ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe61ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe61ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cb30c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2790 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1388edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1388eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1388ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaddf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaddf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaddf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaddf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e138883bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e138883a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1388688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e138517e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e138517b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaddf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaddf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaddf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e138517a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (2791 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (2792 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9cfeeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9cfeebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9cfeef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05e2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05e26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05e2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05e2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9cfe84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9cfe84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9cfe698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9cfb18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9cfb18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05e2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05e26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05e26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9cfb18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (2793 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594b765ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594b7659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594b765d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed9ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed9ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed9ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed9eced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594b75f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594b75f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594b75d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594b7286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594b7286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed9eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed9ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed9ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594b7286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (2794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bi # | ... # `---data was truncated (10240/136481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a2609beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a26098e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a2609c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f4f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f4f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f4f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f4f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a26031bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a26031a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a260168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a25cc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a25cc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f4f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f4f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f4f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a25cc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (2795 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618cb822eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618cb81fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618cb82362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4224249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4224249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4224231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618cb7b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618cb7b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618cb79d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618cb44ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618cb44cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4224232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42242330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618cb44ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (2796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd07013eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd07010e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd0701462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b82b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b82b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b82b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b82b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd06fa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd06fa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd06f8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd06c3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd06c3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b82b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b82b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b82b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd06c3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (2797 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, ali # | ... # `---data was truncated (10240/33772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616deee6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616deee3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616deee762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3e9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3e90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3e9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3e9031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616dee7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616dee7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616dee618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616deb10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616deb10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3e9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3e90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3e90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616deb10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (2798 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/54488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ba49b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ba49b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ba49ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91a3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91a34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91a3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91a3431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ba494fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ba494fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ba49348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ba45e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ba45e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91a3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91a34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91a34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ba45e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (2799 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598de158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598de155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598de15962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49b8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49b84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49b8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49b8431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598de0eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598de0eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598de0d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598ddd82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598ddd82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49b8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49b84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49b84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598ddd82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (2800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e1d772eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e1d76fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e1d77362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f065ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f065cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f065ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f065ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e1d708bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e1d708a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e1d6ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e1d39ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e1d39cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f065ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f065ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f065ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e1d39ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (2801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d8bb7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d8bb7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d8bb7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5f7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d8bb14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d8bb14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d8baf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d8b7a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d8b7a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff5f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d8b7a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (2802 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa756a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa756a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa756a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e14049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e14049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e14031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa7563ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa7563ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa756238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa752d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa752d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e14032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e140330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa752d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (2803 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055753c826eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055753c823e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055753c82762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc863d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc863d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc863d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc863d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055753c7bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055753c7bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055753c7a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055753c450e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055753c450b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc863d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc863d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc863d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055753c450a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (2804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (2805 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @or_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %or = or <32 x i8> %0, %1 # | store <32 x i8> %or, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (2806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611266cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611266cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611266d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb914849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9148a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb914849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb914831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561126665bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561126665a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056112664a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611262f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611262f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb914832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9148330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9148330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611262f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (2807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558eaa6d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558eaa6d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558eaa6d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf3e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf3e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf3e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf3e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558eaa66cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558eaa66ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558eaa6518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558eaa300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558eaa300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf3e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf3e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf3e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558eaa300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (2808 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/72143) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056445db6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056445db68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056445db6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9ceb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9ceb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9ceb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9ceb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056445db01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056445db01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056445dae68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056445d795e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056445d795b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9ceb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9ceb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9ceb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056445d795a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (2809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3d9e0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3d9e07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3d9e0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1960249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19602a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1960249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1960231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d9da0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3d9da0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3d9d858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3d9a34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3d9a34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1960232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19602330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19602330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d9a34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (2810 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e2b4a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e2b49fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e2b4a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2918133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f291818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2918133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f291811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e2b438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e2b438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e2b41d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e2b0cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e2b0ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f291811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f291811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f291811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e2b0cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (2811 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t. # | ... # `---data was truncated (10240/15486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f0fa64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f0fa61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f0fa6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fb3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fb338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fb3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fb331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f0f9fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f0f9faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f0f9df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f0f68ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f0f68eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fb331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fb331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fb331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f0f68ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (2812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (2813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3746cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3746c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3746cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8cde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8cdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8cde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8cde31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e374662bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e374662a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3746478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3742f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3742f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8cde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8cde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8cde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3742f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (2814 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align # | ... # `---data was truncated (10240/39586) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b87f18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b87f15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b87f1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dd5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dd52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dd5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dd5231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b87eaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b87eaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b87e938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b87b42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b87b42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dd5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dd52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dd52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b87b42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (2815 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (2816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c941a32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c941a2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c941a3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ccd01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ccd0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ccd01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ccd003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9419c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9419c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9419ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c94165ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c94165cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ccd004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ccd0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ccd0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c94165ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (2817 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622390eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622390e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622390eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26ebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26ebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26ebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26ebb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562239080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562239080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622390658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562238d14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562238d14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f26ebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26ebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26ebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562238d14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (2818 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/183423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555a5adaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555a5ad7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555a5adb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88eae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88eaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88eae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88eae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555a5a70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555a5a70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555a5a558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555a5704e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555a5704b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88eae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88eae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88eae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555a5704a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (2819 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056439bdabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056439bda8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056439bdac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ef9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ef9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ef9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ef9eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056439bd41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056439bd41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056439bd268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056439b9d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056439b9d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ef9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ef9eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ef9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056439b9d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (2820 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f77e8eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f77e8ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f77e8ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f77e884bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f77e884a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f77e8698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f77e518e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f77e518b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0c831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f77e518a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (2821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/15211) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056220b839eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056220b836e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056220b83a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe653649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6536a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe653649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe653631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056220b7cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056220b7cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056220b7b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056220b463e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056220b463b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe653632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6536330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6536330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056220b463a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (2822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c41544eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c41541e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c4154562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b8f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b8f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b8f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b8f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c414dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c414daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c414bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c4116ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c4116eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b8f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b8f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b8f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c4116ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (2823 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_v # | ... # `---data was truncated (10240/29273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dd8b68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dd8b65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dd8b6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa756649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7566a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa756649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa756631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dd8afebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dd8afea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dd8ae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dd8792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dd8792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa756632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7566330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7566330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dd8792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (2824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da8465ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da84659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da8465d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb78661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7866725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb78661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb786603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da845f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da845f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da845d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da84286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da84286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb786604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7866050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7866050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da84286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (2825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bc5f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bc5f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bc5f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03b241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03b24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03b241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03b2403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bc5f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bc5f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bc5f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bc5bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bc5bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03b2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03b24050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03b24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bc5bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (2826 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558823604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558823601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055882360562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f033e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f033e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f033e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f033e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055882359abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055882359aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055882357f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055882322ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055882322eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f033e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f033e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f033e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055882322ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (2827 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b628bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b628bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b628be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f5f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f5f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f5f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f5f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b62853bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b62853a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b628388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b624e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b624e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f5f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f5f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f5f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b624e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (2828 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/14461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055975bb37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055975bb34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055975bb3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e88649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e88649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e88631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055975bacdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055975bacda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055975bab28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055975b761e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055975b761b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e88632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e886330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055975b761a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (2829 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 noundef # | ... # `---data was truncated (10240/29167) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617291b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617291b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617291b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8f4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8f4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8f4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8f4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056172914dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056172914da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617291328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561728de1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561728de1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8f4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8f4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8f4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561728de1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (2830 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557357cabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557357ca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557357cac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b52249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b522a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b52249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b52231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557357c41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557357c41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557357c268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005573578d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005573578d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b52232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b522330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b522330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573578d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (2831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643f2243eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643f2240e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643f224462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c7a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643f21d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643f21d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643f21be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643f1e6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643f1e6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643f1e6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2832 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bae10bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bae10b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bae10bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc15b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc15b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc15b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc15b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bae1052bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bae1052a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bae10378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bae0ce6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bae0ce6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc15b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc15b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc15b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bae0ce6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (2833 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557097bc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557097bc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557097bc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01dc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01dc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01dc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01dc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557097b5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557097b5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557097b408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570977efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570977efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01dc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01dc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01dc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570977efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (2834 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c0b153eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c0b150e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c0b15462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa86c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa86c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa86c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa86c631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c0b0e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c0b0e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c0b0ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c0ad7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c0ad7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa86c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa86c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa86c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c0ad7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2835 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26710) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620f8abceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620f8ab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620f8abd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21acd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21acd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21acd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21acd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620f8a52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620f8a52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620f8a378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620f86e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620f86e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21acd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21acd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21acd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620f86e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (2836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559264478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559264475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055926447962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd58831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055926440ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055926440ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592643f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592640a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592640a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd588330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592640a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (2837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (2838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563797595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563797592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056379759662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd93721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9372725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd93721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd937203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056379752bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056379752ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637975108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637971bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637971bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd937204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9372050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9372050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637971bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (2839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a8b9d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a8b9d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a8b9d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f797a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f797a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f797a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f797a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a8b969bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a8b969a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a8b94e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a8b5fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a8b5fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f797a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f797a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f797a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a8b5fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2840 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (2841 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ba8507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ba8504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ba850862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44db449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44db4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44db449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44db431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ba849dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ba849da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ba84828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ba8131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ba8131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44db432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44db4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44db4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ba8131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (2842 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621ca4deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621ca4dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621ca4df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8086e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8086ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8086e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8086e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621ca474bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621ca474a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621ca4598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621ca108e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621ca108b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8086e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8086e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8086e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621ca108a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-loongarch.c (2843 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "loongarch32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 4, ptr %res, align 4 # | store volatile i32 5, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563dea46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563dea43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563dea4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc524449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc524449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc524431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563de9dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563de9dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563de9c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563de670e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563de670b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc524432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563de670a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (2844 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/43507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef0b04beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef0b048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef0b04c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca79133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca7918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca79133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca7911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef0afe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef0afe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef0afc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef0ac75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef0ac75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca7911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca7911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca7911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef0ac75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (2845 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, # | ... # `---data was truncated (10240/23056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608ea408eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608ea405e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608ea40962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d79d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d79d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d79d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d79d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608ea39ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608ea39ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608ea3838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608ea032e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608ea032b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d79d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d79d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d79d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608ea032a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/11958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fdcefeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fdcefbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fdceff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01bd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fdce94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fdce94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fdce798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558fdcb28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558fdcb28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fdcb28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2847 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a923ed8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a923ed5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a923ed962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f724c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f724c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f724c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f724c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a923e6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a923e6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a923e538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a923b02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a923b02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f724c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f724c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f724c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a923b02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2848 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa02717eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa02714e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa0271862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda4a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda4a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda4a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda4a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa026adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa026ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa026928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa02341e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa02341b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda4a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda4a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda4a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa02341a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (2849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055634fd7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055634fd7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055634fd7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f394ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f394ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f394ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f394ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055634fd14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055634fd14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055634fcf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055634f9a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055634f9a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f394ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f394ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f394ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055634f9a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-vcadd.c (2850 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.3a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i) # | %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i) # | %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i) # | %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %result = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float> # | %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float> # | %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i) # | %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i) # | %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i) # | %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i) # | %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 # | ... # `---data was truncated (10240/13572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # | #0 0x000056330475ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563304759e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056330475d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f358fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f358fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f358fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f358fced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633046f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633046f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633046d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563304386e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563304386b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f358fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f358fcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f358fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563304386a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (2851 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056275dbe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056275dbe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056275dbea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff56d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff56d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056275db7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056275db7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056275db648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056275d813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056275d813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff56d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056275d813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (2852 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/67482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561dd0fc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561dd0fbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561dd0fc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febaa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febaa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febaa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febaa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dd0f57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561dd0f57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561dd0f3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561dd0bebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561dd0bebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febaa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febaa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febaa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dd0beba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (2853 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056130c7aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056130c7a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056130c7ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fa2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fa2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fa2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fa2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056130c742bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056130c742a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056130c7278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056130c3d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056130c3d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fa2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fa2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fa2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056130c3d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (2854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d684c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d684c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d684c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6be4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6be44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6be4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6be4431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d6845ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d6845ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d684438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d680f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d680f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6be4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6be44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6be44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d680f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (2855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b07085eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b07082e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b0708662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6809333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f680938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6809333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f680931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b0701bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b0701ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b070008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b06cafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b06cafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f680931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f680931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f680931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b06cafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (2856 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (2857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fbad67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fbad64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fbad6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4da9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4da9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4da9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4da9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fbacfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fbacfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fbace28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fba991e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fba991b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4da9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4da9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4da9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fba991a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (2858 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586da7d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586da7d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586da7da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff486e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff486ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff486e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff486e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586da76fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586da76fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586da7548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586da403e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586da403b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff486e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff486e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff486e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586da403a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (2859 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8e71cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8e71c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8e71cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22fae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8e7162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8e7162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8e71478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8e6df6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8e6df6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22fae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8e6df6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (2860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557391ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557391dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557391de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7fc831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555739173bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555739173a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557391588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555738e07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555738e07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7fc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555738e07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (2861 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/28559) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629544a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056295449de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629544a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08ed831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562954436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562954436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056295441b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629540cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629540cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08ed8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629540caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (2862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/31868) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f76639eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f76636e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f7663a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57f0631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f765cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f765cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f765b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f76263e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f76263b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f57f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57f06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f76263a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (2863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc9db9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc9db9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc9db9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d4f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc9db34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc9db34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc9db198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc9d7c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc9d7c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc9d7c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (2864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638a5966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005638a5963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005638a596762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31f9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638a58fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638a58fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638a58e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005638a5590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005638a5590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638a5590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (2865 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055793a435eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055793a432e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055793a43662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47f8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47f84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47f8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47f8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055793a3cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055793a3cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055793a3b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055793a05fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055793a05fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47f8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47f84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47f84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055793a05fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (2866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a18836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a18833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a1883762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93be231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a187ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a187cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a187b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a18460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a18460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93be2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a18460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (2867 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqr # | ... # `---data was truncated (10240/28170) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abe952beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abe9528e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abe952c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f33b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f33b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f33b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f33b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abe94c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abe94c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abe94a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abe9155e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abe9155b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f33b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f33b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f33b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abe9155a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (2868 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (2869 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3760c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3760c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3760c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d0d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d0d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d0d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d0d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c37605ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c37605ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3760438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c375cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c375cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d0d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d0d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d0d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c375cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (2870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa41478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa41475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa4147962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe93f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe93f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe93f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe93f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa4140ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa4140ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa413f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa410a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa410a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe93f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe93f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe93f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa410a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (2871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7f6b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7f6b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7f6b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a68c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a68ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a68c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a68c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f6ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7f6ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7f6ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7f6766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7f6766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a68c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a68c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a68c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f6766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (2872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f05836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f05833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f0583762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf62e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf62ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf62e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf62e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f057ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f057cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f057b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f05460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f05460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf62e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf62e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf62e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f05460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (2873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa76d64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa76d61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa76d6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a5e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a5e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a5e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a5e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa76cfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa76cfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa76cdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa7698ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa7698eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a5e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a5e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a5e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa7698ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (2874 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c66c513eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c66c510e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c66c51462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff250105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff25015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff250105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2500ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c66c4a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c66c4a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c66c48e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c66c13de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c66c13db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2500eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2500ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2500ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c66c13da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (2875 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e1ad8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e1ad8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e1ad8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe88221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8822725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe88221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe882203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e1ad23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e1ad23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e1ad088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e1a9b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e1a9b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe882204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8822050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8822050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e1a9b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (2876 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c1b428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c1b425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c1b42962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb03c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb03ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb03c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb03c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c1b3bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c1b3bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c1b3a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c1b052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c1b052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb03c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb03c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb03c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c1b052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2877 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (2878 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (2879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a2e2f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a2e2f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a2e2f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc76f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc76f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc76f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc76f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a2e28dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a2e28da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a2e2728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a2df21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a2df21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc76f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc76f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc76f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a2df21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (2880 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 nou # | ... # `---data was truncated (10240/27442) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ef0e4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ef0e4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ef0e5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f680fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f680fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f680fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f680fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ef0de5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ef0de5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ef0dca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ef0a79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ef0a79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f680fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f680fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f680fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ef0a79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (2881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cef03eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560cef03be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560cef03f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3060049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30600a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3060049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3060031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ceefd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ceefd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ceefb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ceec68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ceec68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3060032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30600330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30600330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ceec68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (2882 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555687222eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055568721fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055568722362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe376b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe376b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe376b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe376b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556871b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556871b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055568719d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555686e4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555686e4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe376b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe376b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe376b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555686e4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (2883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca # | ... # `---data was truncated (10240/43625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d35897beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d358978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d35897c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f824741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82474725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f824741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8247403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d358911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d358911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3588f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3585a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3585a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8247404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82474050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82474050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3585a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (2884 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632c6f55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632c6f52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632c6f5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a15533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a1558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a15533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a1551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632c6eebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632c6eeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632c6ed08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632c6b7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632c6b7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a1551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a1551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a1551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632c6b7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (2885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e39f729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e39f726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e39f72a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd28ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd28baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd28ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd28ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e39f6bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e39f6bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e39f6a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e39f353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e39f353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd28ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd28ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd28ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e39f353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (2886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (2887 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff22150eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff2214de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff2215162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cc3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cc34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cc3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cc3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff220e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff220e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff220cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff21d7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff21d7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cc3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cc34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cc34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff21d7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (2888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (2889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb134c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb134c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb134c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaeb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaeb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaeb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaeb831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb1345bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb1345ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb134408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb130efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb130efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaeb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaeb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaeb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb130efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (2890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557416b1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557416b1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557416b1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a8ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a8caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a8ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a8ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557416ab3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557416ab3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557416a988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557416747e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557416747b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a8ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a8ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a8ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557416747a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (2891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ce8ccceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ce8cc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ce8ccd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9648049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96480a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9648049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9648031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ce8c62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ce8c62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ce8c478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ce88f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ce88f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9648032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96480330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96480330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ce88f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (2892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (2893 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556227d54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556227d51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556227d5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc03b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc03b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc03b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc03b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556227ceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556227ceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556227ccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055622797ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055622797eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc03b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc03b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc03b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055622797ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (2894 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba88f87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba88f84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba88f8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb179e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb179ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb179e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb179e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba88f1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba88f1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba88f028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba88bb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba88bb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb179e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb179e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb179e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba88bb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (2895 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/22367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584f99d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584f99d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584f99d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32c1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32c1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32c1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32c1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584f996abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584f996aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584f994f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584f95fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584f95feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32c1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32c1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32c1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584f95fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (2896 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = sub <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fsub <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = sub <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fsub <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055fc3bf95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc3bf92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc3bf9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb13333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb1338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb13333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb1331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc3bf2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc3bf2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc3bf108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc3bbbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc3bbbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb1331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb1331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb1331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc3bbbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (2897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsli # | ... # `---data was truncated (10240/14908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597299afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597299ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597299b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ea9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ea9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ea9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ea9eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559729945bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559729945a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055972992a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597295d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597295d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ea9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ea9eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ea9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597295d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (2898 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (2899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | # | ... # `---data was truncated (10240/40891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a91d9b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a91d9b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a91d9b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc269133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc26918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc269133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc26911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a91d94ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a91d94ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a91d9338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a91d5e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a91d5e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc26911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc26911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc26911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a91d5e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2900 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2901 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 % # | ... # `---data was truncated (10240/20326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d59f5d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d59f5d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d59f5d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedb6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedb638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedb6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedb631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d59f56abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d59f56aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d59f54f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d59f1fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d59f1feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fedb631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedb631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedb631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d59f1fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (2902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558548d41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558548d3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558548d4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f640c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f640c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f640c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f640c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558548cd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558548cd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558548cbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055854896be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055854896bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f640c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f640c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f640c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055854896ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (2903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555edf67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555edf64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555edf6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4da3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4da3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4da3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4da3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555edefdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555edefda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555edee28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555edb91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555edb91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4da3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4da3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4da3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555edb91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (2904 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i6 # | ... # `---data was truncated (10240/182165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5cb17feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5cb17ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5cb18062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9f7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9f74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9f7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9f7431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5cb115bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5cb115a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5cb0fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5cada9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5cada9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9f7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9f74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9f74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5cada9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (2905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa7b2d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa7b2d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa7b2d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd51533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd5158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd51533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd5151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa7b26dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa7b26da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa7b2528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa7af01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa7af01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd5151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd5151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd5151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa7af01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (2906 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611e6a6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611e6a69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611e6a6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e4f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e4f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e4f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e4f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611e6a02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611e6a02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611e69e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611e6696e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611e6696b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e4f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e4f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e4f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611e6696a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (2907 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7bd12aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7bd127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7bd12b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a09e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a09ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a09e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a09e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7bd0c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7bd0c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7bd0a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7bcd54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7bcd54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a09e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a09e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a09e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7bcd54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (2908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (2909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b9b134eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b9b131e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b9b13562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f029b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f029b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f029b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f029b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b9b0cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b9b0caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b9b0af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b9ad5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b9ad5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f029b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f029b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f029b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b9ad5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (2910 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fa6b47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fa6b44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fa6b4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9e7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9e7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9e7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9e7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fa6addbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fa6adda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fa6ac28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fa6771e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fa6771b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9e7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9e7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9e7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fa6771a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (2911 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b7a6b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b7a6b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b7a6b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69d0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69d018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69d0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69d011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b7a649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b7a649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b7a62e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b7a2dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b7a2ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69d011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69d011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69d011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b7a2dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (2912 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056127d5edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056127d5eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056127d5ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2eaec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2eaeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2eaec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2eaec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056127d583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056127d583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056127d5688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056127d217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056127d217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2eaec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2eaec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2eaec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056127d217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (2913 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559598180eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055959817de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055959818162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21ff505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21ff55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21ff505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21ff4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559598116bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559598116a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595980fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559597daae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559597daab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21ff4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21ff4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21ff4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559597daaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (2914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4d26feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4d26fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4d26ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd760049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7600a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd760049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd760031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4d2694bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4d2694a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4d26798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4d2328e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4d2328b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd760032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7600330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7600330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4d2328a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (2915 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6827b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6827b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6827b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d34449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d34449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d34431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a682749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a682749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a68272e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6823dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6823ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d34432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d344330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6823dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (2916 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/63510) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615cd26beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615cd268e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615cd26c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39b6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39b6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39b6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39b6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615cd201bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615cd201a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615cd1e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615cce95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615cce95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39b6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39b6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39b6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615cce95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (2917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa95505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa95502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa9550662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfdc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfdc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfdc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfdc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa9549bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa9549ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa954808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa9512fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa9512fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfdc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfdc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfdc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa9512fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (2918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fef990eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fef98de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fef99162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3644733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f364478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3644733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f364471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fef926bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fef926a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fef90b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fef5bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fef5bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f364471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f364471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f364471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fef5baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (2919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9834e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9834e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9834e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fada0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fada00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fada0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fada0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c983479bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c983479a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c98345e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c98310de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c98310db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fada0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fada00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fada00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c98310da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (2920 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a3b46eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a3b46be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a3b46f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65d731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a3b404bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a3b404a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a3b3e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a3b098e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a3b098b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65d731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a3b098a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-cde-vec.c (2921 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 { # | entry: # | %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %acc, ptr %acc.addr, align 8 # | %0 = load <4 x i32>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113) # | %3 = bitcast <16 x i8> %2 to <4 x i32> # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 { # | entry: # | %n.addr = alloca <8 x half>, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | %0 = load <8 x half>, ptr %n.addr, align 8 # | %1 = bitcast <8 x half> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 { # | entry: # | %n.addr = alloca <4 x float>, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %n.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112) # | %3 = bitcast <16 x i8> %2 to <4 x float> # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <2 x i64>, align 8 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = load <2 x i64>, ptr %n.addr, align 8 # | %3 = bitcast <2 x i64> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113) # | %5 = bitcast <16 x i8> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 { # | entry: # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x i32> %m, ptr %m.addr, align 8 # | %0 = load <8 x i16>, ptr %n.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <16 x i8> # | %2 = load <4 x i32>, ptr %m.addr, align 8 # | %3 = bitcast <4 x i32> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %n.addr = alloca <2 x i64>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <2 x i64>, ptr %n.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %2 = load <4 x float>, ptr %m.addr, align 8 # | %3 = bitcast <4 x float> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12) # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load <8 x i16>, ptr %n.addr, align 8 # | %2 = bitcast <8 x i16> %1 to <16 x i8> # | %3 = load <4 x float>, ptr %m.addr, align 8 # | %4 = bitcast <4 x float> %3 to <16 x i8> # | %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %n.addr, align 8 # | %2 = bitcast <4 x float> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = load <8 x half>, ptr %n.addr, align 8 # | %2 = bitcast <8 x half> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %m.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | ... # `---data was truncated (10240/13030) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558890601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588905fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055889060262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d16933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d1698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d16933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d1691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558890597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558890597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055889057c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055889022be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055889022bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d1691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d1691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d1691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055889022ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (2922 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vsqrth_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %vsqrt, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %c.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %__s2 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load half, ptr %__s0, align 2 # | %4 = load half, ptr %__s1, align 2 # | %5 = load half, ptr %__s2, align 2 # | %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %6, ptr %ref.tmp, align 2 # | %7 = load half, ptr %ref.tmp, align 2 # | store half %7, ptr %__ret, align 2 # | %8 = load half, ptr %__ret, align 2 # | store half %8, ptr %tmp, align 2 # | %9 = load half, ptr %tmp, align 2 # | ret half %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # | #0 0x000055ef447c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef447c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef447c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b98533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b9858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b98533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b9851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef44759bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef44759a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef4473e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef443ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef443edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b9851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b9851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b9851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef443eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (2923 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (2924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddb773deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ddb773ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ddb773e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7401d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7401d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7401d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7401d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddb76d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ddb76d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ddb76b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ddb7367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ddb7367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7401d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7401d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7401d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddb7367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (2925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c17a35aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c17a357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c17a35b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8073249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8073249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8073231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c17a2f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c17a2f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c17a2d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c179f84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c179f84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8073232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80732330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c179f84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (2926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (2927 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb3735deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb3735ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb3735e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7add133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7add18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7add133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7add11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb372f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb372f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb372d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb36f87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb36f87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7add11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7add11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7add11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb36f87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560206419eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560206416e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056020641a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfeb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfeb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfeb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfeb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602063afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602063afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602063948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560206043e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560206043b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfeb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfeb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfeb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560206043a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2929 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a36790beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a367908e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a36790c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8107b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8107b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8107b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8107b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3678a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3678a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3678868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a367535e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a367535b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8107b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8107b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8107b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a367535a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (2930 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055833d45eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055833d45be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055833d45f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf26a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf26aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf26a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf26a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055833d3f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055833d3f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055833d3d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055833d088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055833d088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf26a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf26a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf26a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055833d088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (2931 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056198500feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056198500ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056198501062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07bea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07beaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07bea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07bea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561984fa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561984fa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561984f8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561984c39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561984c39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f07bea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07bea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07bea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561984c39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (2932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align # | ... # `---data was truncated (10240/14145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e78c7d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e78c7d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e78c7d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd00c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd00c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd00c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd00c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e78c76ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e78c76ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e78c7538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e78c402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e78c402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd00c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd00c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd00c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e78c402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (2933 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2b101beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2b1018e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2b101c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2b0fb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2b0fb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2b0f968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2b0c45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2b0c45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2b0c45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (2934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/13617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601b4152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601b414fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601b415362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4219d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4219d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4219d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4219ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601b40e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601b40e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601b40cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601b3d7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601b3d7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4219ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4219cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4219cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601b3d7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (2935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8fa437eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8fa434e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8fa43862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5042933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f504298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5042933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f504291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8fa3cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8fa3cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8fa3b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8fa061e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8fa061b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f504291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f504291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f504291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8fa061a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (2936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562df2e92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562df2e8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562df2e9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1cde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1cde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1cde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1cde03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562df2e28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562df2e28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562df2e0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562df2abce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562df2abcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1cde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1cde050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1cde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562df2abca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (2937 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a3fcaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a3fca7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a3fcab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0227c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0227c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0227c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0227c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a3fc40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a3fc40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a3fc258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a3f8d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a3f8d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0227c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0227c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0227c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a3f8d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (2938 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff3832aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff38327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff3832b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e19449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e19449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e19431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff382c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff382c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff382a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff37f54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff37f54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e19432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e194330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff37f54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (2939 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # | #0 0x000055ebc4aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebc4aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebc4af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3315a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3315aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3315a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3315a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebc4a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebc4a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebc4a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebc4719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebc4719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3315a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3315a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3315a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebc4719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (2940 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609c687ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609c6879e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609c687d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5c0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5c0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5c0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5c0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609c6812bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609c6812a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609c67f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609c64a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609c64a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5c0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5c0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5c0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609c64a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (2941 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c5956beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c59568e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c5956c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2db9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2db98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2db9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2db9831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c59501bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c59501a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c594e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c59195e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c59195b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2db9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2db98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2db98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c59195a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/thinlto-multi-module.ll (2942 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # | #0 0x000055e056c91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e056c8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e056c9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86b611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e056c27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e056c27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e056c0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0568bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0568bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86b611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0568bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (2943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | sto # | ... # `---data was truncated (10240/102864) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561db3609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561db3606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561db360a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05df01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05df0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05df01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05df003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561db359fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561db359fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561db35848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561db3233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561db3233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05df004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05df0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05df0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561db3233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (2944 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6bc8c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6bc8c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6bc8c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc0c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc0c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc0c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc0c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6bc85cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6bc85ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6bc8418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6bc4f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6bc4f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc0c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc0c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc0c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6bc4f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (2945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f7aa5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f7aa57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f7aa5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63c4705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63c475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63c4705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63c46ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f7a9f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f7a9f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f7a9d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f7a684e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f7a684b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63c46eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63c46ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63c46ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f7a684a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (2946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c635a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c635a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c635a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06c0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06c098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06c0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06c091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c6353dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c6353da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c635228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c631d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c631d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06c091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06c091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06c091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c631d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (2947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d5f3a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d5f3a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d5f3a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd25b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd25b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd25b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd25b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d5f33ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d5f33ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d5f3238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d5efd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d5efd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd25b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd25b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd25b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d5efd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (2948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4 # | ... # `---data was truncated (10240/96257) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e0d806eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e0d803e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e0d80762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a11333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a1138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a11333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a1131b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e0d79cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e0d79ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e0d7818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e0d430e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e0d430b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a1131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a1131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a1131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e0d430a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (2949 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/12050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b84631eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b8462ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b8463262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3776249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3776249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3776231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b845c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b845c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b845ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b8425be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b8425bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3776232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37762330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b8425ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (2950 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, , # | ... # `---data was truncated (10240/16521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb60221eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb6021ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb6022262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb57f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb57f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb57f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb57f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb601b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb601b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb6019c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb5fe4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb5fe4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb57f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb57f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb57f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb5fe4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (2951 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load < # | ... # `---data was truncated (10240/14421) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618a5691eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618a568ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618a569262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88c7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618a5627bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618a5627a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618a560c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618a52bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618a52bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88c72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618a52bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (2952 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fdcb03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fdcb00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fdcb0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c27733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c2778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c27733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c2771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fdca99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fdca99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fdca7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fdc72de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fdc72db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c2771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c2771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c2771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fdc72da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (2953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (2954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aa3988eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558aa3985e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558aa398962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd78e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd78e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aa391ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558aa391ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558aa39038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558aa35b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558aa35b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd78e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aa35b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (2955 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (2956 of 27910) ******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.MyTask = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { ptr } # | %"struct.std::suspend_always" = type { i8 } # | %struct.Awaiter = type { ptr } # | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" } # | # | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any # | # | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type15await_transformERKi = comdat any # | # | $_ZN7Awaiter11await_readyEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any # | # | $_ZN7Awaiter12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type13final_suspendEv = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | @g_array = global [32 x i32] zeroinitializer, align 16 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local ptr @_Z6FooBarv() #0 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1 # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6 # | store ptr @_Z6FooBarv.resume, ptr %call, align 8 # | %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup # | %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8 # | store ptr %0, ptr %destroy.addr, align 8 # | %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18 # | %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24 # | %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32 # | %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40 # | %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48 # | %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56 # | %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19 # | %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16 # | %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call1, ptr %coerce.dive2, align 8 # | call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | br i1 %call3, label %init.ready, label %CoroSave # | # | CoroSave: ; preds = %entry # | %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 0, ptr %index.addr39, align 1 # | call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | init.ready: ; preds = %entry # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | store ptr @g_array, ptr %__range1.reload.addr, align 8 # | store ptr @g_array, ptr %__begin1.reload.addr, align 8 # | store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %init.ready # | %1 = load ptr, ptr %__begin1.reload.addr, align 8 # | %2 = load ptr, ptr %__end1.reload.addr, align 8 # | %cmp = icmp ne ptr %1, %2 # | br i1 %cmp, label %for.body, label %coro.final # | # | for.body: ; preds = %for.cond # | %3 = load ptr, ptr %__begin1.reload.addr, align 8 # | store ptr %3, ptr %x.reload.addr, align 8 # | %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2 # | %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4) # | %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0 # | store ptr %call5, ptr %coerce.dive6, align 8 # | %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | br i1 %call7, label %await.ready, label %CoroSave27 # | # | CoroSave27: ; preds = %for.body # | %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 1, ptr %index.addr40, align 1 # | %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call) # | %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0 # | %7 = load ptr, ptr %6, align 8 # | call void %7(ptr %5) # | br label %AfterCoroEnd # | # | await.ready: ; preds = %for.body # | call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | %cond = icmp eq i32 0, 0 # | %cond26 = icmp eq i32 0, 0 # | br i1 %cond26, label %for.inc, label %coro.final # | # | for.inc: ; preds = %await.ready # | %8 = load ptr, ptr %__begin1.reload.addr, align 8 # | %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1 # | store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8 # | br label %for.cond # | # | coro.final: ; preds = %await.ready, %for.cond # | call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7 # | %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | br i1 %call20, label %final.ready, label %CoroSave31 # | # | CoroSave31: ; preds = %coro.final # | store ptr null, ptr %call, align 8 # | call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | final.ready: ; preds = %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | %9 = icmp ne ptr %call, null # | br i1 %9, label %coro.free, label %AfterCoroEnd # | # | coro.free: ; preds = %final.ready # | call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7 # | br label %AfterCoroEnd # | # | AfterCoroEnd: ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave # | %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0 # | %10 = load ptr, ptr %coerce.dive25, align 8 # | ret ptr %10 # | } # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %this.addr = alloca ptr, align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call, ptr %coerce.dive2, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false) # | %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0 # | %0 = load ptr, ptr %coerce.dive4, align 8 # | ret ptr %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret i1 false # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 { # | entry: # | %.addr = alloca ptr, align 8 # | %.addr1 = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %0, ptr %.addr, align 8 # | store ptr %1, ptr %.addr1, align 8 # | %2 = load ptr, ptr %.addr, align 8 # | %3 = load ptr, ptr %.addr1, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7 # | # | ... # `---data was truncated (10240/37953) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # | #0 0x0000562ada375eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ada372e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ada37662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbbd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbbd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbbd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbbd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ada30bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ada30ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ada2f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ad9f9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ad9f9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbbd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbbd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbbd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ad9f9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (2957 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e777125eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e777122e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e77712662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f4af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f4af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f4af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f4af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7770bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7770bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7770a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e776d4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e776d4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f4af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f4af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f4af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e776d4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (2958 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = loa # | ... # `---data was truncated (10240/23447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a73728eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a73725e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a7372962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8262533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f826258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8262533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f826251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a736bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a736bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a736a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a73352e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a73352b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f826251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f826251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f826251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a73352a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (2959 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628cbec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628cbec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628cbec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed4eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed4eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed4eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed4eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628cbe5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628cbe5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628cbe418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628cbaf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628cbaf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed4eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed4eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed4eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628cbaf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (2960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9b8a5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9b8a57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9b8a5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20d931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9b89f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9b89f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9b89d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9b8684e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9b8684b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f20d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20d931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9b8684a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (2961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (2962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nof # | ... # `---data was truncated (10240/11966) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb8a59deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb8a59ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb8a59e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9832849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9832849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9832831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb8a533bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb8a533a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb8a5188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb8a1c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb8a1c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9832832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98328330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb8a1c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (2963 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down. # | ... # `---data was truncated (10240/14900) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b852593eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b852590e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b85259462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f149e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f149e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f149e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f149e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b852529bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b852529a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b85250e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8521bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8521bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f149e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f149e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f149e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8521bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (2964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056463e405eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056463e402e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056463e40662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9817649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98176a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9817649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9817631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056463e39bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056463e39ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056463e3808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056463e02fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056463e02fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9817632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98176330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98176330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056463e02fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (2965 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f3b190eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f3b18de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f3b19162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3106333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f310638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3106333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f310631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f3b126bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f3b126a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f3b10b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f3adbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f3adbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f310631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f310631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f310631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f3adbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (2967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = # | ... # `---data was truncated (10240/33471) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7e2d69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7e2d66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7e2d6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e0e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e0e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e0e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e0e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7e2cffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7e2cffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7e2ce48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7e2993e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7e2993b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e0e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e0e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e0e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7e2993a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (2968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c75838ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c758389e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c75838d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3fce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3fcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3fce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3fce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c758322bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c758322a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7583078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c757fb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c757fb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3fce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3fce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3fce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c757fb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (2969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c70eaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c70eabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c70eaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f607bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f607bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f607bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f607bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c70e44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c70e44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c70e298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c70ad8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c70ad8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f607bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f607bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f607bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c70ad8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (2971 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.add # | ... # `---data was truncated (10240/86739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f397624eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f397621e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f39762562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6c901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6c90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6c901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6c9003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3975babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3975baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f39759f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f39724ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f39724eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6c9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6c90050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6c90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f39724ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (2972 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entr # | ... # `---data was truncated (10240/18361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565279ba9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565279ba6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565279baa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f63b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f63b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f63b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f63b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565279b3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565279b3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565279b248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652797d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652797d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f63b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f63b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f63b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652797d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (2973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ac15eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ac15ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ac15ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe564133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe56418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe564133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe56411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ac1584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ac1584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ac15698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ac1218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ac1218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe56411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe56411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe56411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ac1218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (2974 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb773cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb773c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb773cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ada533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ada58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ada533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ada51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb77361bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb77361a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb773468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb76ff5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb76ff5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ada51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ada51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ada51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb76ff5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (2975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557867d4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557867d4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557867d4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f697941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69794725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f697941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6979403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557867ce4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557867ce4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557867cc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557867978e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557867978b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6979404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69794050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69794050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557867978a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (2976 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.v # | ... # `---data was truncated (10240/58683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd6c5a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd6c59fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd6c5a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26c4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd6c538bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd6c538a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd6c51d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd6c1cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd6c1ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f26c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd6c1cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (2977 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3b7a57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a3b7a54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a3b7a5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d2da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d2daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d2da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d2da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3b79edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3b79eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3b79d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3b7681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3b7681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d2da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d2da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d2da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3b7681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (2978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558407b65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558407b62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558407b6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f260a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f260a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f260a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f260a831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558407afbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558407afba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558407ae08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055840778fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055840778fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f260a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f260a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f260a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055840778fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (2979 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0e1eadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0e1eaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0e1eae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14e5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14e50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14e5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14e5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0e1e43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0e1e43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0e1e288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0e1ad7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0e1ad7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14e5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14e50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14e50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0e1ad7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (2980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( p # | ... # `---data was truncated (10240/24606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055789f78aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055789f787e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055789f78b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d6e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d6e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d6e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d6e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055789f720bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055789f720a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055789f7058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055789f3b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055789f3b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d6e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d6e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d6e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055789f3b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (2981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea5d07eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea5d07be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea5d07f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bf5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bf578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bf5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bf571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea5d014bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea5d014a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea5cff98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea5cca8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea5cca8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bf571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bf571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bf571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea5cca8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (2982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a64946eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a64943e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a6494762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f08049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f08049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f08031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a648dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a648dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a648c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a64570e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a64570b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f08032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f080330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a64570a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (2983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8df731eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8df72ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8df73262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f35e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f35e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f35e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f35e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8df6c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8df6c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8df6ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8df35be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8df35bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f35e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f35e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f35e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8df35ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (2984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7f690aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7f6907e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7f690b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a97a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a97a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a97a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a97a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7f68a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7f68a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7f68858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7f6534e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7f6534b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a97a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a97a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a97a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7f6534a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (2985 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabi" # | # | %struct.Simple = type { i8, i8 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldrex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldaex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_strex(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %res = alloca i32, align 4 # | %var = alloca %struct.Simple, align 1 # | %tmp = alloca i64, align 8 # | %tmp8 = alloca double, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store i32 0, ptr %res, align 4 # | call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false) # | %0 = load ptr, ptr %addr.addr, align 4 # | %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0) # | %1 = load i32, ptr %res, align 4 # | %or = or i32 %1, %strex # | store i32 %or, ptr %res, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2) # | %3 = load i32, ptr %res, align 4 # | %or2 = or i32 %3, %strex1 # | store i32 %or2, ptr %res, align 4 # | %4 = load ptr, ptr %addr.addr, align 4 # | %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4) # | %5 = load i32, ptr %res, align 4 # | %or4 = or i32 %5, %strex3 # | store i32 %or4, ptr %res, align 4 # | store i64 42, ptr %tmp, align 8 # | %6 = load { i32, i32 }, ptr %tmp, align 8 # | %7 = extractvalue { i32, i32 } %6, 0 # | %8 = extractvalue { i32, i32 } %6, 1 # | %9 = load ptr, ptr %addr.addr, align 4 # | %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9) # | %10 = load i32, ptr %res, align 4 # | %or5 = or i32 %10, %strexd # | store i32 %or5, ptr %res, align 4 # | %11 = load ptr, ptr %addr.addr, align 4 # | %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11) # | %12 = load i32, ptr %res, align 4 # | %or7 = or i32 %12, %strex6 # | store i32 %or7, ptr %res, align 4 # | store double 3.141590e+00, ptr %tmp8, align 8 # | %13 = load { i32, i32 }, ptr %tmp8, align 8 # | %14 = extractvalue { i32, i32 } %13, 0 # | %15 = extractvalue { i32, i32 } %13, 1 # | %16 = load ptr, ptr %addr.addr, align 4 # | %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16) # | %17 = load i32, ptr %res, align 4 # | %or10 = or i32 %17, %strexd9 # | store i32 %or10, ptr %res, align 4 # | %18 = load ptr, ptr %addr.addr, ali # | ... # `---data was truncated (10240/16971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d28000beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d280008e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d28000c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51f7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51f758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51f7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51f751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d27ffa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d27ffa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d27ff868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d27fc35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d27fc35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51f751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51f751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51f751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d27fc35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (2986 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (2987 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557b5081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557b507ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557b508262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff003449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0034a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff003449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff003431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557b5017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557b5017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557b4ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557b4cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557b4cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff003432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0034330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0034330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557b4caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2988 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abf9135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abf9132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abf913662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c93533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c9358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c93533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c9351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abf90cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abf90cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abf90b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abf8d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abf8d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c9351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c9351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c9351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abf8d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (2989 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (2990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056110c725eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056110c722e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056110c72662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f522f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f522f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f522f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f522f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056110c6bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056110c6bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056110c6a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056110c34fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056110c34fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f522f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f522f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f522f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056110c34fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (2991 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056150dc1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056150dc17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056150dc1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c6d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c6d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c6d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c6d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056150dbb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056150dbb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056150db958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056150d844e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056150d844b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c6d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c6d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c6d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056150d844a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (2992 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bc9a85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564bc9a82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564bc9a8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e05e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e05ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e05e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e05e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bc9a1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564bc9a1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564bc9a008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564bc96afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564bc96afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e05e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e05e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e05e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bc96afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (2993 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622bf89deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622bf89ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622bf89e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f923ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f923ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f923ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f923ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622bf833bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622bf833a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622bf8188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622bf4c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622bf4c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f923ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f923ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f923ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622bf4c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (2994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f629caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f629c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f629cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8bd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f62960bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f62960a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f629458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f625f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f625f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f625f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (2995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e1646feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e1646ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e1647062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80b9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80b9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80b9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80b9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e16405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e16405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e163ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e16099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e16099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80b9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80b9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80b9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e16099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (2996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1dc741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1dc73ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1dc74262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effa5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effa54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effa5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effa5431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1dc6d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1dc6d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1dc6bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1dc36be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1dc36bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effa5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effa54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effa54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1dc36ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (2997 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <4 x half>, align 8 # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <8 x i8> %4 to <4 x half> # | %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6) # | store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <16 x i8> %4 to <8 x half> # | %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %9 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %9, ptr %__ret, align 8 # | %10 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %10, ptr %tmp, align 8 # | %11 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <16 x i8>, align 16 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | store <16 x i8> %2, ptr %__s2, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <16 x i8>, ptr %__s2, align 16 # | %7 = load i64, ptr %__s4, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %8 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %8, ptr %__ret, align 8 # | %9 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %9, ptr %tmp, align 8 # | %10 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <16 x i8>, ptr %__s0, align 16 # | %5 = load <16 x i8>, ptr %__s1, align 16 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <16 x i8> %4 to <8 x half> # | %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3) # | store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16 # | %9 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, < # | ... # `---data was truncated (10240/24508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055a235d1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a235d1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a235d1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50cd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50cd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50cd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50cd431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a235cb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a235cb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a235c988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a235947e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a235947b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50cd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50cd4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50cd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a235947a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (2998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2e86c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2e86c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2e86c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff185449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff185449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff185431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2e865bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2e865ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2e86408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2e82efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2e82efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff185432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1854330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2e82efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (2999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (3000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b75eb2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b75eb2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b75eb2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f413f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f413f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f413f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f413f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b75eac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b75eac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b75eaa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b75e757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b75e757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f413f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f413f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f413f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b75e757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (3001 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (3002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f8b4ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f8b4cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f8b4cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe5481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe548725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe5481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe54803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f8b464bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f8b464a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f8b4498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f8b0f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f8b0f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe54804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe548050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe548050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f8b0f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (3003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633b5b3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633b5b3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633b5b4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8622049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86220a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8622049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8622031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633b5ad5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633b5ad5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633b5aba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633b5769e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633b5769b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8622032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86220330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86220330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633b5769a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (3004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i8 @subscript_int8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i8 @subscript_uint8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64( %a.coerce, i64 0) # | store <4 x double> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x double>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000056424e225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056424e222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056424e22662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe919b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe919b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe919b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe919b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056424e1bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056424e1bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056424e1a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056424de4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056424de4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe919b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe919b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe919b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056424de4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (3005 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store targ # | ... # `---data was truncated (10240/14667) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd39045eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd39042e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd3904662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64ee705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64ee75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64ee705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64ee6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd38fdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd38fdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd38fc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd38c6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd38c6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f64ee6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64ee6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64ee6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd38c6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (3006 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c0b2c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c0b2bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c0b2c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa61f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa61f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa61f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa61f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c0b257bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c0b257a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c0b23c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c0aeebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c0aeebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa61f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa61f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa61f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c0aeeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (3007 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7c455deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7c455ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7c455e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f054ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f054ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f054ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f054ae03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7c44f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7c44f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7c44d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7c4187e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7c4187b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f054ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f054ae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f054ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7c4187a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (3008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb28544eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb28541e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb2854562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6821a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6821aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6821a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6821a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb284dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb284daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb284bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb2816ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb2816eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6821a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6821a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6821a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb2816ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (3009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 8) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t( %dest, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 8) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563eea2b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563eea2ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563eea2b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dd2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dd258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dd2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dd251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563eea246bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563eea246a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563eea22b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ee9edae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ee9edab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dd251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dd251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dd251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ee9edaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (3010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/30759) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bbc6e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bbc6e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bbc6e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f384f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f384f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f384f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f384f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bbc679bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bbc679a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bbc65e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bbc30de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bbc30db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f384f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f384f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f384f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bbc30da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (3011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc55ed3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc55ed0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc55ed462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a18849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a18849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a18831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc55e69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc55e69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc55e4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc55afde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc55afdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a18832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a188330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc55afda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (3012 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b54c9cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b54c9cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b54c9ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e0e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e0e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e0e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e0e003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b54c963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b54c963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b54c9488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b54c5f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b54c5f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e0e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e0e0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e0e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b54c5f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (3013 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056019ae52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056019ae4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056019ae5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f707c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f707c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f707c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f707c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056019ade8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056019ade8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056019adcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056019aa7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056019aa7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f707c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f707c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f707c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056019aa7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (3014 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a17dd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a17dcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a17dd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3455c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3455ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3455c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3455c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a17d66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a17d66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a17d4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a179fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a179fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3455c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3455c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3455c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a179faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (3015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccdb4e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ccdb4e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ccdb4e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd097a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd097aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd097a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd097a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccdb47ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ccdb47ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ccdb4638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ccdb112e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ccdb112b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd097a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd097a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd097a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccdb112a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (3016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557792283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557792280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055779228462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f372a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f372a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f372a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f372a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557792219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557792219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577921fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557791eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557791eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f372a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f372a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f372a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557791eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (3017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bad3505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bad3502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bad350662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb67eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb67eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb67eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb67eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bad349bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bad349ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bad34808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bad312fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bad312fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb67eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb67eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb67eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bad312fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (3018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (3019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (3020 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575bbd9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575bbd99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575bbd9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23f3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23f338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23f3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23f331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575bbd32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575bbd32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575bbd178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575bb9c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575bb9c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23f331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23f331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23f331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575bb9c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (3021 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vr # | ... # `---data was truncated (10240/96265) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056275e679eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056275e676e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056275e67a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea92e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea92ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea92e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea92e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056275e60fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056275e60fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056275e5f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056275e2a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056275e2a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea92e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea92e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea92e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056275e2a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (3022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac7b6daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac7b6d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac7b6db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26c3231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac7b670bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac7b670a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac7b6558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac7b304e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac7b304b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f26c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26c32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac7b304a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (3023 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594eaec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594eaec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594eaec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c8c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c8c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c8c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c8c631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594eae5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594eae5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594eae418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594eaaf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594eaaf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c8c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c8c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c8c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594eaaf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (3024 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) # # | ... # `---data was truncated (10240/26584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a80cb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a80cb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a80cb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7564133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f756418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7564133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f756411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a80c4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a80c4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a80c2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a808dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a808deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f756411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f756411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f756411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a808dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (3025 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, p # | ... # `---data was truncated (10240/33435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602830c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602830bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602830c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9407733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f940778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9407733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f940771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560283058bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560283058a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056028303d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560282cece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560282cecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f940771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f940771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f940771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560282ceca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (3026 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056363b1f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056363b1f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056363b1fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa06ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa06aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa06ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa06ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056363b18fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056363b18fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056363b1748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056363ae23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056363ae23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa06ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa06ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa06ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363ae23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (3027 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fad296eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fad293e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fad29762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd631c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd631ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd631c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd631c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fad22cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fad22ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fad2118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561facec0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561facec0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd631c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd631c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd631c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561facec0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (3028 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (3029 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dae918eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dae915e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dae91962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c17f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c17f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c17f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c17f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dae8aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dae8aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dae8938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dae542e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dae542b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c17f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c17f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c17f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dae542a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (3030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/47720) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdc9389eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdc9386e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdc938a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c59733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c5978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c59733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c5971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdc931fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdc931fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdc93048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdc8fb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdc8fb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c5971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c5971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c5971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdc8fb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-cde-gpr.c (3031 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 { # | entry: # | %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 { # | entry: # | %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567) # | %1 = extractvalue { i32, i32 } %0, 1 # | %2 = zext i32 %1 to i64 # | %3 = shl i64 %2, 32 # | %4 = extractvalue { i32, i32 } %0, 0 # | %5 = zext i32 %4 to i64 # | %6 = or i64 %3, %5 # | ret i64 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33) # | %2 = extractvalue { i32, i32 } %1, 1 # | %3 = zext i32 %2 to i64 # | %4 = shl i64 %3, 32 # | %5 = extractvalue { i32, i32 } %1, 0 # | %6 = zext i32 %5 to i64 # | %7 = or i64 %4, %6 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = load i32, ptr %m.addr, align 4 # | %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3) # | %3 = extractvalue { i32, i32 } %2, 1 # | %4 = zext i32 %3 to i64 # | %5 = shl i64 %4, 32 # | %6 = extractvalue { i32, i32 } %2, 0 # | %7 = zext i32 %6 to i64 # | %8 = or i64 %5, %7 # | ret i64 %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = load i32, ptr %m.addr, align 4 # | %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8388c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8388c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8388c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dc7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dc70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dc7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dc7031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c83885dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c83885da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8388428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8384f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8384f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8dc7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dc70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dc70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8384f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (3032 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd4f744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd4f741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd4f74562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f828d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f828d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f828d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f828d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd4f6dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd4f6daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd4f6bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd4f36ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd4f36eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f828d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f828d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f828d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd4f36ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (3033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1341baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1341b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1341bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3979333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f397938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3979333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f397931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d134150bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d134150a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1341358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d133de4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d133de4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f397931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f397931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f397931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d133de4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (3034 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = ashr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = lshr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = ashr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = lshr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %shl = shl <8 x i32> %0, %1 # | store <8 x i32> %shl, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %r # | ... # `---data was truncated (10240/50943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b6f362aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6f3627e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6f362b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff101d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff101d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff101d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff101d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6f35c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6f35c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6f35a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6f3254e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6f3254b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff101d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff101d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff101d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6f3254a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (3035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055772a0dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055772a0d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055772a0dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f708b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f708b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f708b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f708b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055772a071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055772a071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055772a0568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557729d05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557729d05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f708b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f708b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f708b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557729d05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (3036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (3037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055726c9bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055726c9b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055726c9bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a0561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a056725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a0561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a05603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055726c951bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055726c951a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055726c9368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055726c5e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055726c5e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a05604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a056050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a056050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055726c5e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (3038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ac573beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ac5738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ac573c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f417d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f417d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f417d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f417d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ac56d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ac56d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ac56b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ac5365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ac5365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f417d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f417d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f417d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ac5365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (3039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v # | ... # `---data was truncated (10240/18520) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f7483eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f7483be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f7483f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ed0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ed08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ed0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ed0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f747d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f747d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f747b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f74468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f74468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ed0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ed08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ed08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f74468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (3040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/62752) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618a4b74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618a4b71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618a4b7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ff9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ff9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ff9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ff9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618a4b0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618a4b0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618a4aef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618a479ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618a479eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ff9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ff9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ff9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618a479ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (3041 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df986cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df986c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df986cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa00a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa00a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa00a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa00a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df98662bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df98662a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df986478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df982f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df982f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa00a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa00a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa00a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df982f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (3042 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cee5b8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cee5b8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cee5b8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2496333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f249638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2496333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f249631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cee5b24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cee5b24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cee5b098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cee57b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cee57b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f249631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f249631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f249631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cee57b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (3043 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aa83d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558aa83d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558aa83da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaf6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaf658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaf6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaf651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aa836fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558aa836fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558aa83548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558aa8003e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558aa8003b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaf651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaf651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaf651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aa8003a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (3044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret # | ... # `---data was truncated (10240/25287) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e3a46beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e3a468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e3a46c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e01733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e0178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e01733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e0171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e3a401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e3a401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e3a3e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e3a095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e3a095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e0171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e0171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e0171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e3a095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (3045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee0dc00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee0dbfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee0dc0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe842a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe842aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe842a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe842a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee0db96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee0db96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee0db7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee0d82ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee0d82ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe842a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe842a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe842a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee0d82aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (3046 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5dc8afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5dc8ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5dc8b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9600f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9600f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9600f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9600f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5dc845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5dc845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5dc82a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5dc4d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5dc4d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9600f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9600f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9600f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5dc4d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (3047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (3048 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (3049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c59231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c5922ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c5923262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f8321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f832725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f8321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f83203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c591c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c591c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c591ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c58e5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c58e5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f83204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f832050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f832050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c58e5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/linker-diagnostic.ll (3050 of 27910) ******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # | #0 0x000055918c1c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055918c1c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055918c1ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafd7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafd7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafd7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafd7c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055918c15fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055918c15fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055918c1448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055918bdf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055918bdf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fafd7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafd7c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafd7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055918bdf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (3051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (3052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (3053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562698363eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562698360e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056269836462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fa0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fa075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fa0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fa06ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626982f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626982f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626982de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562697f8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562697f8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1fa06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fa06ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fa06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562697f8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (3054 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613d6faceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613d6fa9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613d6fad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc12af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc12af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc12af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc12af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613d6f42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613d6f42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613d6f278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613d6bd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613d6bd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc12af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc12af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc12af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613d6bd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (3055 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579aab75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579aab72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579aab7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63efb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579aab0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579aab0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579aaaf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579aa79fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579aa79fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579aa79fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (3056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", , 2) %src) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 8 # | %1 = call @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", , 2) %dest, %val) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %val.addr = alloca , align 8 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 8 # | store %val, ptr %val.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 8 # | %1 = load , ptr %val.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2) %0, %1, i32 1) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562919728eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562919725e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056291972962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a36d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a36d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a36d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a36d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629196bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629196bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629196a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562919352e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562919352b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a36d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a36d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a36d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562919352a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (3057 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd51827eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd51824e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd5182862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bca631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd517bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd517bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd517a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd51451e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd51451b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bca6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd51451a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (3058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.ad # | ... # `---data was truncated (10240/26762) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6037a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a60379fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6037a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a603738bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a603738a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a60371d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6033cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6033ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ce791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6033cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (3059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bb6baceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bb6ba9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bb6bad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1dff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1dff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1dff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1dfeed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bb6b42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bb6b42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bb6b278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bb67d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bb67d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1dfeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1dfeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1dfeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bb67d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (3060 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c81ebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c81eb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c81ebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6435733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f643578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6435733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f643571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c81e52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c81e52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c81e378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c81ae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c81ae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f643571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f643571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f643571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c81ae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (3061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaf8f83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eaf8f80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eaf8f8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32da51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaf8f19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eaf8f19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eaf8efe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eaf8bade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eaf8badb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32da51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaf8bada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (3062 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c559d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c559d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c559d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc537649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc537649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc537631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c5596bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c5596ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c559508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c555ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c555ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc537632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5376330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c555ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (3063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559656d10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559656d0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559656d1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d7e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d7e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d7e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d7e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559656ca6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559656ca6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559656c8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055965693ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055965693ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d7e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d7e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d7e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055965693aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (3064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad2e6f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad2e6eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad2e6f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6710e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6710ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6710e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6710e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad2e687bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad2e687a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad2e66c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad2e31be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad2e31bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6710e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6710e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6710e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad2e31ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (3065 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f23f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f23f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f23f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7afa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7afa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7afa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7afa11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f23f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f23f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f23f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f23bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f23bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7afa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7afa11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7afa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f23bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (3066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ba4cd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ba4ccee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ba4cd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc33505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc3355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc33505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc334ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ba4c67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ba4c67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ba4c4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ba48fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ba48fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc334eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc334ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc334ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ba48fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (3067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e53fa34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e53fa31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e53fa3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab1ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab1baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab1ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab1ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e53f9cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e53f9caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e53f9af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e53f65ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e53f65eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab1ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab1ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab1ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e53f65ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (3068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589835c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589835c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589835c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1126d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1126d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1126d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1126ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055898355dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055898355da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589835428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589831f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589831f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1126ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1126cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1126cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589831f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (3069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (3070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dcfb12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555dcfb0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555dcfb1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f182a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f182a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f182a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f182a631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dcfaa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555dcfaa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555dcfa8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dcf73ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dcf73cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f182a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f182a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f182a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dcf73ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (3071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b160edeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b160edbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b160edf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88c4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88c498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88c4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88c491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b160e74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b160e74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b160e598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b160b08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b160b08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88c491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88c491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88c491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b160b08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (3072 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbcb477eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbcb474e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbcb47862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f072dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f072dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f072dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f072dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbcb40dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbcb40da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbcb3f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbcb0a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbcb0a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f072dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f072dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f072dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbcb0a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (3073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556ddbb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556ddbb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556ddbb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9238c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9238ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9238c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9238c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556ddb4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556ddb4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556ddb328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556dd7e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556dd7e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9238c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9238c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9238c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556dd7e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (3074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff516e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff516e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff516e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcebb305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcebb35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcebb305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcebb2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff5167cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff5167ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff516618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff51310e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff51310b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcebb2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcebb2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcebb2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff51310a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (3075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ee93d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ee93d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ee93d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59f9231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ee936dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ee936da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ee93528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ee9001e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ee9001b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59f92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ee9001a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (3076 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056188f224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056188f221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056188f22562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd885249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8852a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd885249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd885231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056188f1babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056188f1baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056188f19f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056188ee4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056188ee4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd885232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8852330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8852330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056188ee4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (3077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563da0eb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563da0eb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563da0eb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc658733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc65878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc658733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc65871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563da0e49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563da0e49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563da0e2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563da0adde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563da0addb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc65871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc65871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc65871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563da0adda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (3078 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055990d9afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055990d9ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055990d9b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07a5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07a538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07a5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07a531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055990d945bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055990d945a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055990d92a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055990d5d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055990d5d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f07a531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07a531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07a531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055990d5d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (3079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfm # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac17e9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac17e9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac17e9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd129a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd129aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd129a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd129a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac17e33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac17e33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac17e188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac17ac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac17ac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd129a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd129a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd129a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac17ac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (3080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (3081 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a11c7b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a11c7afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a11c7b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f475d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f475d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f475d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f475d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a11c748bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a11c748a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a11c72d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a11c3dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a11c3dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f475d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f475d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f475d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a11c3dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (3082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d125c97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d125c94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d125c9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ff5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ff5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ff5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ff5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d125c2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d125c2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d125c128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1258c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1258c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ff5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ff5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ff5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1258c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (3083 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b70059eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b70056e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b7005a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f855b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f855b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f855b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f855b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b6ffefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b6ffefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b6ffd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b6fc83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b6fc83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f855b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f855b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f855b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b6fc83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (3084 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (3085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fe9f85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fe9f82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fe9f8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95fb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95fb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95fb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95fb631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fe9f1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fe9f1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fe9f008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fe9bafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fe9bafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95fb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95fb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95fb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fe9bafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (3086 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/32702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dd9a7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dd9a7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dd9a7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f657eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f657eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f657eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f657eaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dd9a13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dd9a13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dd99f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dd96a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dd96a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f657eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f657eaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f657eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dd96a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (3087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (3088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562635f45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562635f42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562635f4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5a7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5a718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5a7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5a711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562635edbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562635edba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562635ec08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562635b6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562635b6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5a711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5a711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5a711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562635b6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (3089 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dd36e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559dd36e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559dd36ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc49933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc4998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc49933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc4991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dd367fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559dd367fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559dd36648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559dd3313e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559dd3313b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc4991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc4991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc4991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dd3313a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (3090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b061b9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b061b9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b061b9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ff5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ff50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ff5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ff5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b061b33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b061b33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b061b188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0617c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0617c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ff5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ff50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ff50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0617c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (3091 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056002d845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056002d842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056002d84662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d0771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056002d7dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056002d7dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056002d7c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056002d46fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056002d46fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d0771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056002d46fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (3092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a14709eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a14706e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a1470a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cd9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cd9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cd9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cd9e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a1469fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a1469fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a146848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a14333e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a14333b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3cd9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cd9e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cd9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a14333a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (3093 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055573f830eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055573f82de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055573f83162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ba5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ba558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ba5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ba551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055573f7c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055573f7c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055573f7ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055573f45ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055573f45ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ba551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ba551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ba551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055573f45aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (3094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fdeed1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fdeecee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fdeed262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54b301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54b30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54b301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54b3003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fdee67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fdee67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fdee4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fdeafbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fdeafbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54b3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54b30050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54b30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fdeafba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (3095 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f525437eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f525434e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f52543862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc53c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc53c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc53c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc53c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5253cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5253cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5253b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f525061e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f525061b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc53c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc53c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc53c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f525061a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (3096 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp sge <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp uge <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp sge <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c724174eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c724171e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c72417562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa70b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa70b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa70b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa70b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c72410abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c72410aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7240ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c723d9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c723d9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa70b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa70b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa70b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c723d9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (3097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba83f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba83f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba83f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbac9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbac9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbac9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbac9aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba83ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba83ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba83ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba83b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba83b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbac9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbac9aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbac9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba83b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (3098 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e179f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e179f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e179f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc78df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc78df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc78df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc78df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e1798ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e1798ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e179738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e17622e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e17622b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc78df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc78df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc78df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e17622a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (3099 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643dafb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643dafb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643dafb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd59041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5904725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd59041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd590403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643daf4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643daf4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643daf308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643dabdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643dabdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd590404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5904050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5904050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643dabdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (3100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/31876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056096ff2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056096ff2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056096ff2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3816249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3816249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3816231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056096fec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056096fec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056096fea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056096fb57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056096fb57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3816232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38162330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056096fb57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (3101 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # | #0 0x0000555efe271eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555efe26ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555efe27262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd7f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd7f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd7f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd7f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555efe207bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555efe207a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555efe1ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555efde9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555efde9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd7f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd7f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd7f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555efde9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (3102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef %rs1, i # | ... # `---data was truncated (10240/14325) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd4c6bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd4c6bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd4c6c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb09a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb09a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb09a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb09a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd4c655bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd4c655a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd4c63a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd4c2e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd4c2e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb09a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb09a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb09a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd4c2e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (3103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056407bc6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056407bc68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056407bc6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c49d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c49d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c49d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c49d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056407bc01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056407bc01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056407bbe68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056407b895e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056407b895b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c49d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c49d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c49d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056407b895a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (3104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz # | ... # `---data was truncated (10240/58675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a2cb49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a2cb46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a2cb4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e0ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e0ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e0ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e0ba03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a2cadfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a2cadfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a2cac48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a2c773e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a2c773b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e0ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e0ba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e0ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a2c773a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (3105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, # | ... # `---data was truncated (10240/30635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645c0057eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645c0054e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645c005862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efff6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efff678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efff6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efff671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645bffedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005645bffeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645bffd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645bfc81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645bfc81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efff671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efff671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efff671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645bfc81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (3106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577f2333eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577f2330e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577f233462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febb5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febb5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febb5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febb5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577f22c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577f22c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577f22ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577f1f5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577f1f5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febb5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febb5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febb5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577f1f5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (3107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.ad # | ... # `---data was truncated (10240/13903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a37555eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a37552e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a3755662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f351f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f351f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f351f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f351f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a374ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a374eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a374d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a3717fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a3717fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f351f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f351f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f351f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a3717fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (3108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599c16f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599c16f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599c16fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9068e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9068ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9068e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9068e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599c168fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599c168fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599c16748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599c1323e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599c1323b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9068e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9068e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9068e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599c1323a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (3109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f04607eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f04604e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f0460862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39e5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39e50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39e5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39e5031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f0459dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f0459da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f045828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f04231e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f04231b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39e5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39e50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39e50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f04231a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (3110 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dce5996eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dce5993e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dce599762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2acf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2acf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2acf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2acf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dce592cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dce592ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dce59118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dce55c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dce55c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2acf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2acf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2acf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dce55c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (3111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (3112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557618334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557618331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055761833562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e98c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e98ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e98c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e98c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576182cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576182caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576182af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557617f5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557617f5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e98c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e98c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e98c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557617f5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (3113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a23e428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a23e425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a23e42962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f786ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f786ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f786ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f786ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a23e3bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a23e3bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a23e3a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a23e052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a23e052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f786ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f786ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f786ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a23e052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (3114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056447f9efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056447f9ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056447f9f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7718f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7718f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7718f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7718f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056447f985bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056447f985a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056447f96a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056447f619e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056447f619b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7718f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7718f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7718f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056447f619a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (3115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055829c4eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055829c4e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055829c4ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f121bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f121bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f121bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f121bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055829c482bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055829c482a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055829c4678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055829c116e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055829c116b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f121bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f121bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f121bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055829c116a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (3116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056066aaefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056066aaece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056066aaf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43d8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43d818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43d8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43d811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056066aa85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056066aa85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056066aa6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056066a719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056066a719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43d811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43d811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43d811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056066a719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (3117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055577cb01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055577cafee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055577cb0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f207e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f207e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f207e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f207e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055577ca97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055577ca97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055577ca7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055577c72be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055577c72bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f207e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f207e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f207e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055577c72ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (3118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f64.i64( poison, double %0, i64 %1) # | # | ... # `---data was truncated (10240/30849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0f4524eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0f4521e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0f452562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37aad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37aad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37aad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37aad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0f44babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0f44baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0f449f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0f414ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0f414eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37aad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37aad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37aad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0f414ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (3119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %m # | ... # `---data was truncated (10240/41661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619f90b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619f90b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619f90b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f963a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f963a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f963a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f963a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619f904dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619f904da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619f90328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619f8ce1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619f8ce1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f963a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f963a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f963a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619f8ce1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (3120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055853d10aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055853d107e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055853d10b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea24333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea2438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea24333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea2431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055853d0a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055853d0a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055853d0858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055853cd34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055853cd34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea2431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea2431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea2431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055853cd34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (3121 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = extractelement <8 x half> %0, i32 2 # | ret half %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = extractelement <4 x float> %0, i32 3 # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 4 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 0 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 10 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 3 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 3 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 1 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 1 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca <8 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load half, ptr %a.addr, align 2 # | %2 = insertelement <8 x half> %0, half %1, i32 4 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 8 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load float, ptr %a.addr, align 4 # | %2 = insertelement <4 x float> %0, float %1, i32 2 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 12 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 6 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 2 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 0 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 2 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 7 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 1 # | ret <2 x i64> %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055ee0e052eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee0e04fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee0e05362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37c9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37c9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37c9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37c9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee0dfe8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee0dfe8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee0dfcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee0dc7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee0dc7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37c9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37c9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37c9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee0dc7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (3122 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1) # | ret float %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1) # | ret double %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1) # | ret float %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1) # | ret double %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1) # | ret float %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1) # | ret double %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1) # | ret float %frint64x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1) # | ret double %frint64x.i # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32x.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64x.f64(double) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8d7a25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8d7a22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8d7a2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50de649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50de6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50de649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50de631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8d79bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8d79bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8d79a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8d764fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8d764fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50de632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50de6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50de6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8d764fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (3123 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611f54deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611f54dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611f54df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e2cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e2cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e2cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e2cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611f5474bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611f5474a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611f54598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611f5108e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611f5108b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e2cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e2cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e2cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611f5108a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (3124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (3125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (3126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (3127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a6790deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a6790ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a6790e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3092b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3092b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3092b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3092b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a678a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a678a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a678888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a67537e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a67537b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3092b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3092b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3092b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a67537a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (3128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3d0627eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3d0624e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3d062862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d7a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d7a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d7a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d05bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3d05bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3d05a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3d0251e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3d0251b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d7a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d7a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d7a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d0251a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (3129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed22428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed22425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed2242962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fd4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fd498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fd4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fd491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed223bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed223bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed223a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed22052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed22052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1fd491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fd491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fd491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed22052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (3130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (3131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedo # | ... # `---data was truncated (10240/30751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056204e7f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056204e7f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056204e7f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e34c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e34c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e34c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e34c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056204e78cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056204e78ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056204e7718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056204e420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056204e420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e34c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e34c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e34c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056204e420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (3132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609a9357eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609a9354e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609a935862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fbef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fbef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fbef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fbef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609a92edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609a92eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609a92d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609a8f81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609a8f81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fbef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fbef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fbef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609a8f81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (3133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) % # | ... # `---data was truncated (10240/27994) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4abd81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4abd7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4abd8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4653133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f465318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4653133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f465311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4abd17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4abd17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4abcfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4ab9abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4ab9abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f465311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f465311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f465311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4ab9aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (3134 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = and <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = and <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = and <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = and <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr # | ... # `---data was truncated (10240/11060) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a63fa8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a63fa8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a63fa8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff111d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff111d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff111d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff111d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a63fa24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a63fa24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a63fa098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a63f6b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a63f6b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff111d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff111d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff111d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a63f6b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (3135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e3321feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e3321ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e3322062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47a671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e331b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e331b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e3319a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e32e49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e32e49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47a671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e32e49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (3136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ... # `---data was truncated (10240/14904) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca65948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca65945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca6594962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f7d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f7d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f7d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f7d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca658debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca658dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca658c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca65572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca65572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f7d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f7d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f7d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca65572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (3137 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> % # | ... # `---data was truncated (10240/15051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056218668ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562186689e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056218668d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5767449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5767449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5767431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562186622bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562186622a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621866078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621862b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621862b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5767432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57674330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621862b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (3138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c986184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c986181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c98618562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa126705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa12675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa126705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1266ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c98611abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c98611aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9860ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c985daee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c985daeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1266eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1266ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1266ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c985daea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (3139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (3140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c1498deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c1498ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c1498e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe906d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe906d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe906d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe906ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c14923bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c14923a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c149088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c145b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c145b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe906ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe906cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe906cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c145b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (3141 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642f993aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642f9937e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642f993b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe227f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe227f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe227f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe227f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642f98d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642f98d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642f98b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642f9564e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642f9564b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe227f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe227f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe227f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642f9564a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (3142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vs # | ... # `---data was truncated (10240/10886) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d15f6edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d15f6eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d15f6ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61ddf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61ddf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61ddf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61ddf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d15f683bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d15f683a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d15f6688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d15f317e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d15f317b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61ddf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61ddf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61ddf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d15f317a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (3143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055558b202eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055558b1ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055558b20362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6139333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f613938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6139333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f613931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055558b198bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055558b198a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055558b17d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055558ae2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055558ae2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f613931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f613931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f613931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055558ae2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (3144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584a9f2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584a9f28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584a9f2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca32133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca3218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca32133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca3211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584a9ec1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584a9ec1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584a9ea68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584a9b55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584a9b55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca3211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca3211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca3211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584a9b55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (3145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f6f410eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f6f40de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f6f41162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f417a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f417a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f417a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f417a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f6f3a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f6f3a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f6f38b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f6f03ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f6f03ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f417a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f417a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f417a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f6f03aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (3146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dc1478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dc1475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dc147962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe962249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9622a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe962249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe962231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dc140ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dc140ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dc13f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dc10a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dc10a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe962232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9622330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9622330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dc10a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (3147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0032d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0032d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0032d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40dc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40dc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40dc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40dc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e00326cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e00326ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0032518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e002f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e002f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40dc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40dc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40dc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e002f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (3148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055922e010eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055922e00de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055922e01162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f142781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14278725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f142781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1427803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055922dfa6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055922dfa6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055922df8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055922dc3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055922dc3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1427804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14278050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14278050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055922dc3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (3149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555df3eeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555df3ee9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555df3eed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aff31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555df3e82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555df3e82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555df3e678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555df3b16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555df3b16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0aff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aff31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555df3b16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (3150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056430ef19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056430ef16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056430ef1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc86f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc86f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc86f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc86f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056430eeafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056430eeafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056430ee948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056430eb43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056430eb43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc86f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc86f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc86f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056430eb43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (3151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e8554deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e8554ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e8554e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59f3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59f3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59f3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59f3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e854e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e854e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e854c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e85177e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e85177b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59f3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59f3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59f3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e85177a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (3152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608feae0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608feadde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608feae162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc668933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc66898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc668933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc66891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608fea76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608fea76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608fea5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608fe70ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608fe70ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc66891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc66891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc66891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608fe70aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (3153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556261fcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556261fc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556261fcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa56d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa56d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa56d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa56d831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556261f61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556261f61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556261f468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556261bf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556261bf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa56d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa56d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa56d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556261bf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (3154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm # | ... # `---data was truncated (10240/53200) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e852b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e852b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e852b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d9d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d9d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d9d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d9d631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e8524dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e8524da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e852328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e84ee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e84ee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d9d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d9d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d9d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e84ee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (3155 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613c977beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613c9778e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613c977c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb136f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb136f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb136f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb136f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613c9711bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613c9711a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613c96f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613c93a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613c93a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb136f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb136f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb136f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613c93a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c994abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c994a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c994ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa87c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa87c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa87c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa87c003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c99441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c99441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c994268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c990d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c990d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa87c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa87c0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa87c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c990d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (3157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db52d31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db52d2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db52d3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaab831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db52cc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db52cc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db52cac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db5295be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db5295bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaab8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db5295ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (3158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593bc89deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593bc89ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593bc89e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb605049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb605049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb605031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593bc833bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593bc833a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593bc8188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593bc4c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593bc4c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb605032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6050330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593bc4c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (3159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, # | ... # `---data was truncated (10240/26468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d83324eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d83321e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d8332562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb37cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb37cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb37cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb37cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d832babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d832baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d8329f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d82f4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d82f4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb37cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb37cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb37cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d82f4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (3160 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577aa8f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577aa8f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577aa8f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4df2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4df28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4df2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4df2831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577aa88ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577aa88ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577aa8738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577aa522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577aa522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4df2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4df28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4df28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577aa522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (3161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, %vs1, # | ... # `---data was truncated (10240/62087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055931d428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055931d425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055931d42962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f899df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f899df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f899df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f899deed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055931d3bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055931d3bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055931d3a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055931d052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055931d052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f899deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f899deef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f899deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055931d052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (3162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055997beb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055997beade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055997beb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cc7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cc7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cc7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cc7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055997be46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055997be46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055997be2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055997badae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055997badab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cc7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cc7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cc7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055997badaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (3163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561816b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561816b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561816b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84d3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84d3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84d3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84d3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561816ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561816ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561816ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561816766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561816766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84d3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84d3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84d3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561816766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (3164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ecfa729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ecfa726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ecfa72a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0acfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0acfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0acfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0acfc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ecfa6bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ecfa6bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ecfa6a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ecfa353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ecfa353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0acfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0acfc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0acfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ecfa353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (3165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581b6970eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581b696de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581b697162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3515a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3515aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3515a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3515a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581b6906bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581b6906a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581b68eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581b659ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581b659ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3515a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3515a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3515a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581b659aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (3166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3bb6f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3bb6ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3bb6f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13c9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13c915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13c9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13c90ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3bb686bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3bb686a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3bb66b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3bb31ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3bb31ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13c90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13c90ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13c90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3bb31aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (3167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (3168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560665482eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056066547fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056066548362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f956c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f956c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f956c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f956c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560665418bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560665418a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606653fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606650ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606650acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f956c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f956c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f956c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606650aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (3169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2f7998eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2f7995e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2f799962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b65733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b6578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b65733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b6571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2f792ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2f792ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2f79138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2f75c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2f75c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b6571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b6571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b6571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2f75c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (3170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.v # | ... # `---data was truncated (10240/53192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570d667ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570d6679e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570d667d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95ec431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570d6612bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570d6612a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570d65f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570d62a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570d62a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95ec4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570d62a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (3171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc47e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc47e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc47e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb138305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb13835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb138305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1382ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc47daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc47daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc47d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc47a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc47a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1382eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1382ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1382ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc47a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (3172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582b6ab2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582b6aafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582b6ab362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38d7431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582b6a48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582b6a48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582b6a2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582b66dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582b66dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38d74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582b66dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (3173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad49b4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad49b4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad49b5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec28f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec28f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec28f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec28f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad49ae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad49ae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad49aca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad49779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad49779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec28f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec28f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec28f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad49779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (3174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7f08c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7f08c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7f08c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f633a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f633a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f633a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f633a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7f085abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7f085aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7f083f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7f04eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7f04eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f633a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f633a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f633a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7f04eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (3175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10878) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acf1d9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acf1d9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acf1d9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadf3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadf398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadf3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadf391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acf1d33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acf1d33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acf1d188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acf19c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acf19c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadf391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadf391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadf391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acf19c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (3176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd2a68beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd2a688e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd2a68c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8e2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8e24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8e2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8e2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd2a621bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd2a621a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd2a6068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd2a2b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd2a2b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8e2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8e24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8e24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd2a2b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (3177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9fb38ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9fb389e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9fb38d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa584b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa584b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa584b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa584b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9fb322bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9fb322a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9fb3078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9fafb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9fafb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa584b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa584b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa584b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9fafb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (3178 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vaddh = fadd half %2, %3 # | store half %vaddh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vsubh = fsub half %2, %3 # | store half %vsubh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmulh = fmul half %2, %3 # | store half %vmulh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vdivh = fdiv half %2, %3 # | store half %vdivh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3) # | store half %vmax, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3) # | store half %vmaxnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3) # | store half %vmin, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3) # | store half %vminnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabsh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vabs = call half @llvm.fabs.f16(half %1) # | store half %vabs, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.fabs.f16(half) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = all # | ... # `---data was truncated (10240/27802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647a0d46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647a0d43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647a0d4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaec249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaec2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaec249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaec231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647a0cdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647a0cdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647a0cc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647a0970e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647a0970b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaec232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaec2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaec2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647a0970a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (3179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055baf20d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055baf20d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055baf20da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8c0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8c02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8c0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8c0231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055baf206fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055baf206fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055baf20548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055baf1d03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055baf1d03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8c0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8c02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8c02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055baf1d03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (3180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e9fb9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e9fb97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e9fb9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc75d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc75d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc75d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc75d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e9fb30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e9fb30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e9fb158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e9f7c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e9f7c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc75d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc75d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc75d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e9f7c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (3181 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , pt # | ... # `---data was truncated (10240/32402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583177eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583177e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583177eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0159333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f015938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0159333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f015931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558317780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558317780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583177658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558317414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558317414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f015931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f015931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f015931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558317414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (3182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (3183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056532e2c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056532e2c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056532e2c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4a6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4a6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4a6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4a6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056532e25abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056532e25aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056532e23f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056532deeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056532deeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4a6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4a6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4a6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056532deeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (3184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/20082) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cd0615eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cd0612e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cd061662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d9b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d9b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d9b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d9b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cd05abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cd05aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cd05908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cd023fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cd023fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d9b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d9b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d9b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cd023fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (3185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loca # | ... # `---data was truncated (10240/18587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629b35bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629b35b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629b35bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe17ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe17ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe17ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe17ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629b3552bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629b3552a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629b35378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629b31e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629b31e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe17ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe17ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe17ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629b31e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (3186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598cf782eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598cf77fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598cf78362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59b2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59b275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59b2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59b26ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598cf718bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598cf718a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598cf6fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598cf3ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598cf3acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59b26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59b26ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59b26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598cf3aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (3187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfcc2ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfcc2fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfcc30062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e3bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e3bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e3bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e3bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfcc295bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfcc295a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfcc27a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfcbf29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfcbf29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e3bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e3bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e3bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfcbf29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (3188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd18b84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd18b81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd18b8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1eaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1eaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1eaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1eaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd18b1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd18b1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd18aff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd187aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd187aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1eaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1eaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1eaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd187aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (3189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define d # | ... # `---data was truncated (10240/25350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614b8370eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614b836de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614b837162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc99081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9908725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc99081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc990803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614b8306bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614b8306a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614b82eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614b7f9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614b7f9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc990804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9908050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9908050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614b7f9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (3190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c9a19beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c9a198e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c9a19c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd70d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd70d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd70d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd70d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c9a131bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c9a131a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c9a1168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c99dc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c99dc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd70d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd70d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd70d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c99dc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (3191 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (3192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bea16aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564bea167e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564bea16b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7648849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7648849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7648831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bea100bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564bea100a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564bea0e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564be9d94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564be9d94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7648832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76488330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be9d94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (3193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df87e35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df87e32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df87e3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df87dcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df87dcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df87db08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df87a5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df87a5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f89b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df87a5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (3194 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (3195 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569bf69ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569bf699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569bf69d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f761d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f761d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f761d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f761d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569bf632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569bf632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569bf6178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569bf2c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569bf2c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f761d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f761d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f761d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569bf2c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (3196 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, al # | ... # `---data was truncated (10240/12389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ec689ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ec6899e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ec689d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4963333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f496338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4963333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f496331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ec6832bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ec6832a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ec68178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ec64c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ec64c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f496331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f496331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f496331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ec64c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (3197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fd491eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fd491be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fd491f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b9e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b9e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b9e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b9e0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fd48b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fd48b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fd48998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fd4548e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fd4548b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b9e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b9e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b9e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fd4548a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (3198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608c5202eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608c51ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608c520362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6a4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6a438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6a4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6a431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608c5198bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608c5198a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608c517d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608c4e2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608c4e2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe6a431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6a431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6a431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608c4e2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (3199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056425ee44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056425ee41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056425ee4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ff2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ff2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ff2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ff2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056425eddabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056425eddaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056425edbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056425ea6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056425ea6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ff2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ff2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ff2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056425ea6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (3200 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl. # | ... # `---data was truncated (10240/11504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566468c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566468bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566468c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82ccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82ccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82ccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82ccb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556646856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556646856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055664683b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566464eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566464eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82ccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82ccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82ccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566464eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (3201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9f9f25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9f9f22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9f9f2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb45ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb45aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb45ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb45ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9f9ebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9f9ebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9f9ea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9f9b4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9f9b4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb45ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb45ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb45ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9f9b4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (3202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643e8bf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643e8bf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643e8bf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa467d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa467d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa467d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa467ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643e8b89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643e8b89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643e8b6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643e881de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643e881db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa467ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa467cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa467cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643e881da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (3203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4aeb17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4aeb14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4aeb1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9427b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9427b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9427b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9427b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4aeaadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4aeaada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4aea928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4ae741e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4ae741b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9427b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9427b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9427b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4ae741a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (3204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.a # | ... # `---data was truncated (10240/38299) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bb8539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bb8536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bb853a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdec2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdec215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdec2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdec20ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bb84cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bb84cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bb84b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bb8163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bb8163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdec20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdec20ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdec20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bb8163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/aapcs-bitfield.c (3205 of 27910) ******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-eabi" # | # | %struct.st6 = type { i16, i8, i8 } # | %struct.st7b = type { i8, [3 x i8], %struct.st7a } # | %struct.st7a = type { i8, i8, [2 x i8] } # | %struct.st11 = type <{ i8, i16, i8 }> # | %struct.st13 = type <{ i8, i32 }> # | %struct.st16 = type { i32, i16, i32, i16 } # | %struct.st17 = type <{ i32, i8 }> # | %struct.zero_bitfield = type { i8, i8, [2 x i8] } # | %struct.zero_bitfield_ok = type { i16, i32 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st0_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st0_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st1_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.ashr = ashr i16 %bf.load, 10 # | %conv = sext i16 %bf.ashr to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st1_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, 1023 # | %bf.set = or i16 %bf.clear, 1024 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st2_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 9 # | %bf.ashr = ashr i32 %bf.shl, 25 # | %bf.cast = trunc i32 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st2_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -8323073 # | %bf.set = or i32 %bf.clear, 65536 # | store i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st3_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st3_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store volatile i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st4_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 2 # | %bf.ashr = ashr i16 %bf.shl, 11 # | %bf.cast = trunc i16 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -15873 # | %bf.set = or i16 %bf.clear, 512 # | store volatile i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -512 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st5_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 11 # | %bf.ashr = ashr i32 %bf.shl, 27 # | %bf.cast = trunc i32 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st5_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -2031617 # | %bf.set = or i32 %bf.clear, 65536 # | store volatile i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st6_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %x = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 4 # | %bf.ashr = ashr i16 %bf.shl, 4 # | %bf.cast = sext i16 %bf.ashr to i32 # | store i32 %bf.cast, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | %2 = load volatile i8, ptr %b, align 2 # | %conv = sext i8 %2 to i32 # | %3 = load i32, ptr %x, align 4 # | %add = add nsw i32 %3, %conv # | store i32 %add, ptr %x, align 4 # | %4 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2 # | %bf.load1 = load volatile i8, ptr %c, align 1 # | %bf.shl2 = shl i8 %bf.load1, 3 # | %bf.ashr3 = ashr i8 %bf.shl2, 3 # | %bf.cast4 = sext i8 %bf.ashr3 to i32 # | %5 = load i32, ptr %x, align 4 # | %add5 = add nsw i32 %5, %bf.cast4 # | store i32 %add5, ptr %x, align 4 # | %6 = load i32, ptr %x, align 4 # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st6_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -4096 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | store i8 2, ptr %b, align 2 # | %2 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2 # | %bf.load1 = load i8, ptr %c, align 1 # | %bf.clear2 = and i8 %bf.load1, -32 # | %bf.set3 = or i8 %bf.clear2, 3 # | store i8 %bf.set3, ptr %c, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st7_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %r = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | %1 = load i8, ptr %x, align 4 # | %conv = sext i8 %1 to i32 # | store i32 %conv, ptr %r, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | %3 = load volatile i8, ptr %a, align 4 # | %conv1 = sext i8 %3 to i32 # | %4 = load i32, ptr %r, align 4 # | %add = add nsw i32 %4, %conv1 # | store i32 %add, ptr %r, align 4 # | %5 = load ptr, ptr %m.addr, align 4 # | %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.shl = shl i8 %bf.load, 3 # | %bf.ashr = ashr i8 %bf.shl, 3 # | %bf.cast = sext i8 %bf.ashr to i32 # | %6 = load i32, ptr %r, align 4 # | %add3 = add nsw i32 %6, %bf.cast # | store i32 %add3, ptr %r, align 4 # | %7 = load i32, ptr %r, align 4 # | ret i32 %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st7_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | store i8 1, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | store volatile i8 2, ptr %a, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.clear = and i8 %bf.load, -32 # | %bf.set = or i8 %bf.clear, 3 # | store volatile i8 %bf.set, ptr %b, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | store i16 -1, ptr %0, align 4 # | ret i32 65535 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @read_st9(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 4 # | %bf.cast = sext i8 %bf.load to i32 # | r # | ... # `---data was truncated (10240/24998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c893c7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c893c7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c893c7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8111733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f811178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8111733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f811171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c893c13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c893c13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c893bf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8938a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8938a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f811171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f811171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f811171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8938a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (3206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (3207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef79806eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef79803e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef7980762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a15b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a15b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a15b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a15b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef7979cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef7979ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef797818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef79430e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef79430b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a15b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a15b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a15b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef79430a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (3208 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (3209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1d7ee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1d7edee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1d7ee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed33649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed336a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed33649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed33631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1d7e77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1d7e77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1d7e5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1d7b0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1d7b0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed33632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed336330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed336330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1d7b0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (3210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align # | ... # `---data was truncated (10240/39226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056078cfeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056078cfebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056078cfef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa6a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa6a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa6a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa6a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056078cf84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056078cf84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056078cf698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056078cc18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056078cc18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa6a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa6a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa6a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056078cc18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (3211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (3212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/34589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dedbe6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dedbe69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dedbe6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44cd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44cd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44cd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44cd231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dedbe02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dedbe02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dedbde78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dedba96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dedba96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44cd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44cd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44cd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dedba96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (3213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d90853eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d90850e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d9085462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa791f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa791f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa791f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa791eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d907e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d907e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d907ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d9047de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d9047db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa791eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa791eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa791eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d9047da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (3214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635eccebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635ecce8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635eccec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcef0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcef078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcef0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcef071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635ecc81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635ecc81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635ecc668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635ec915e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635ec915b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcef071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcef071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcef071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635ec915a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (3215 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (3216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b43e0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b43e0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b43e0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10d6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10d6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10d6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10d6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b43da3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b43da3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b43d888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b43a37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b43a37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10d6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10d6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10d6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b43a37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (3217 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8e8773eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8e8770e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8e877462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2df6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2df638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2df6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2df631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8e8709bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8e8709a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8e86ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8e839de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8e839db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2df631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2df631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2df631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8e839da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (3218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (3219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca # | ... # `---data was truncated (10240/12137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c074b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c074b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c074b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd25d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd25d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd25d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd25d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c0744cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c0744ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c074318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c070e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c070e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd25d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd25d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd25d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c070e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (3220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557582ed4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557582ed1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557582ed562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f842c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f842c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f842c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f842c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557582e6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557582e6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557582e4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557582afee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557582afeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f842c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f842c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f842c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557582afea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (3221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde # | ... # `---data was truncated (10240/31748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2a5bd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2a5bcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2a5bd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81bb105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81bb15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81bb105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81bb0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2a5b66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2a5b66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2a5b4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2a57fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2a57fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81bb0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81bb0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81bb0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2a57faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (3222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b93d909eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b93d906e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b93d90a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b93d89fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b93d89fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b93d8848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b93d533e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b93d533b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b93d533a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (3223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caaf7c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055caaf7c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055caaf7c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb024133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb02418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb024133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb02411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caaf759bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055caaf759a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055caaf73e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055caaf3ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055caaf3edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb02411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb02411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb02411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caaf3eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (3224 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d34eaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d34eabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d34eaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f755501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75550725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f755501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7555003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d34e44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d34e44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d34e298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d34ad8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d34ad8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7555004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75550050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75550050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d34ad8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (3225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b52ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b52eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b52ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc54df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc54df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b52e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b52e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b52e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b52ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b52ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc54df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b52ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (3226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056040e420eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056040e41de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056040e42162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3dae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3daea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3dae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3dae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056040e3b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056040e3b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056040e39b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056040e04ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056040e04ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3dae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3dae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3dae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056040e04aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (3227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cb1a22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cb1a1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cb1a2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc47d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc47d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc47d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc47d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cb19b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cb19b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cb199d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cb164ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cb164cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc47d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc47d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc47d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cb164ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (3228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret # | ... # `---data was truncated (10240/29371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c86ca3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c86ca3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c86ca3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd161c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd161ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd161c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd161c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c86c9d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c86c9d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c86c9b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c86c667e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c86c667b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd161c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd161c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd161c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c86c667a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (3229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d44c7ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d44c7dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d44c7de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad70249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad702a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad70249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad70231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d44c773bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d44c773a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d44c7588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d44c407e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d44c407b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad70232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad702330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad702330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d44c407a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (3230 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 # | ... # `---data was truncated (10240/39417) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005651695c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005651695c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005651695c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae5e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae5e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae5e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae5e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056516955ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056516955ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651695438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651691f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651691f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae5e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae5e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae5e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651691f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (3231 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055769be0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055769be08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055769be0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48aed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48aed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48aed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48aed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055769bda1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055769bda1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055769bd868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055769ba35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055769ba35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f48aed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48aed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48aed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055769ba35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (3232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/22074) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558ca90beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558ca908e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558ca90c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25aa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558ca8a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558ca8a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558ca8868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558ca535e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558ca535b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558ca535a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (3233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (3234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc8f9a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc8f9a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc8f9a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7e671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc8f93bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc8f93ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc8f9208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc8f5cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc8f5cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7e671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc8f5cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (3235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f819b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f819b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f819b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0732533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f073258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0732533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f073251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f81949bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f81949a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f8192e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f815dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f815ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f073251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f073251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f073251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f815dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (3236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | # | ... # `---data was truncated (10240/26460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f465247eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f465244e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f46524862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ad4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ad48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ad4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ad4831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4651ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4651dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4651c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f464e71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f464e71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ad4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ad48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ad48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f464e71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (3237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055596d4adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055596d4aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055596d4ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4424133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f442418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4424133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f442411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055596d443bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055596d443a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055596d4288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055596d0d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055596d0d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f442411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f442411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f442411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055596d0d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (3238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621ad787eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621ad784e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621ad78862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc175533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc17558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc175533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc17551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621ad71dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621ad71da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621ad7028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621ad3b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621ad3b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc17551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc17551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc17551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621ad3b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (3239 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636500f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636500f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636500f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2975733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f297578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2975733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f297571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056365008ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056365008ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636500738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056364fd22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056364fd22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f297571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f297571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f297571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056364fd22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (3240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640f54d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640f54d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640f54d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ffde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ffdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ffde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ffde31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640f5469bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640f5469a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640f544e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640f50fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640f50fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ffde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ffde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ffde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640f50fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (3241 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ae8164eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ae8161e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ae816562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1394c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1394ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1394c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1394c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ae80fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ae80faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ae80df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ae7d8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ae7d8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1394c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1394c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1394c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ae7d8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (3242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629f7b78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629f7b75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629f7b7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3c2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629f7b0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629f7b0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629f7af38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629f77a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629f77a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3c2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629f77a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (3243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cae7373eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cae7370e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cae737462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5a4d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5a4d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5a4d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5a4ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cae7309bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cae7309a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cae72ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cae6f9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cae6f9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5a4ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5a4cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5a4cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cae6f9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (3244 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560578008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560578005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056057800962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ca8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ca838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ca8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ca831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560577f9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560577f9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560577f838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560577c32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560577c32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ca831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ca831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ca831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560577c32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/sse.c (3245 of 27910) ******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558035c8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558035c8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558035c9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f342bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f342bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f342bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f342bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558035c25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558035c25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558035c0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580358b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580358b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f342bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f342bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f342bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580358b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (3246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594ea0ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594ea0cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594ea0cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3824933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f382498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3824933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f382491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594ea064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594ea064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594ea0498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594e9cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594e9cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f382491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f382491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f382491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594e9cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (3247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055736abf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055736abf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055736abf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe48cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe48cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe48cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe48cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055736ab89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055736ab89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055736ab6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055736a81de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055736a81db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe48cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe48cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe48cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055736a81da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (3248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de1cdd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de1cdcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de1cdd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f132a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f132a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f132a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f132a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de1cd66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de1cd66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de1cd4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de1c9fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de1c9fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f132a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f132a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f132a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de1c9faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (3249 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 # | ... # `---data was truncated (10240/28361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607010bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607010bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607010c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd27d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd27d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd27d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd27d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560701055bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560701055a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056070103a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560700ce9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560700ce9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd27d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd27d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd27d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560700ce9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (3250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7398c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7398bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7398c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70a071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c739858bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c739858a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c73983d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7394ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7394ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70a071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7394eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (3251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b34e202eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b34e1ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b34e20362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7724733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f772478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7724733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f772471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b34e198bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b34e198a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b34e17d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b34de2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b34de2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f772471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f772471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f772471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b34de2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (3252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (3253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562dd643eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562dd643be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562dd643f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21a2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21a20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21a2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21a2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dd63d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562dd63d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562dd63b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562dd6068e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562dd6068b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21a2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21a20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21a20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dd6068a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (3254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562918750eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056291874de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056291875162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dc7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7dc7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dc7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dc7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629186e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629186e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629186cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056291837ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056291837ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7dc7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dc7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dc7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056291837aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (3255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563642faeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563642fabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563642faf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7baa505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7baa55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7baa505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7baa4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563642f44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563642f44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563642f298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563642bd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563642bd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7baa4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7baa4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7baa4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563642bd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3256 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-none-elf" # | # | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any # | # | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any # | # | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any # | # | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10 # | ret i32 %2 # | } # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{i32 1, !5} # | !5 = !{!"aarch64.mem_hint", i32 0} # | !6 = !{i32 1, !7} # | !7 = !{!"aarch64.mem_hint", i32 1} # | !8 = !{i32 0, !9} # | !9 = !{!"aarch64.mem_hint", i32 3} # | !10 = !{i32 0, !11} # | !11 = !{!"aarch64.mem_hint", i32 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601b7f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601b7f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601b7f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601b7f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601b7f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601b7f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601b7bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601b7bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601b7bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (3257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598d2d1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598d2d1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598d2d1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71a3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71a32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71a3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71a3231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598d2cb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598d2cb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598d2c998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598d2948e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598d2948b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71a3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71a32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71a32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598d2948a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (3258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a29a49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a29a46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a29a4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb05fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb05faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb05fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb05fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a299dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a299dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a299c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a29673e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a29673b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb05fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb05fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb05fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a29673a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (3259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586d4108eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586d4105e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586d410962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc01333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc0138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc01333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc0131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586d409ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586d409ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586d40838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586d3d32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586d3d32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc0131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc0131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc0131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586d3d32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (3260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558056a83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558056a80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558056a8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbefa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbefa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbefa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbefa231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558056a19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558056a19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580569fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580566ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580566adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbefa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbefa2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbefa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580566ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (3261 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7b90b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7b90b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7b90b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fede4a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fede4a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fede4a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fede4a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7b904abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7b904aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7b902f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7b8cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7b8cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fede4a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fede4a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fede4a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7b8cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (3262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585e16f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585e16ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585e16f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff16d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff16d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff16d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff16d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585e1686bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585e1686a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585e166b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585e131ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585e131ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff16d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff16d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff16d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585e131aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (3263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a7c859eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a7c856e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a7c85a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f153ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f153ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f153ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f153ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a7c7efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a7c7efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a7c7d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a7c483e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a7c483b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f153ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f153ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f153ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a7c483a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (3264 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b30509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b30506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b3050a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb95d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb95d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb95d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb95d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b3049fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b3049fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b304848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b30133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b30133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb95d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb95d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb95d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b30133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (3265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/18867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616c3bdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616c3bd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616c3bdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b8dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b8dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b8dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b8dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616c3b72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616c3b72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616c3b578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616c3806e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616c3806b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b8dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b8dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b8dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616c3806a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3266 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555776d4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555776d4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555776d5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6d611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555776ce5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555776ce5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555776cca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555776979e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555776979b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6d611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555776979a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (3267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bb59deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bb59dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bb59df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32f8631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bb5974bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bb5974a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bb59598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bb5608e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bb5608b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32f86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bb5608a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (3268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (3269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2f07c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2f07bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2f07c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffacd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffacd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffacd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffacd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2f0758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2f0758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2f073d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2f03ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2f03ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffacd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffacd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffacd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2f03eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (3270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (3271 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/11849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e27667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e27664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e2766862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8dd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e275fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e275fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e275e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e27291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e27291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e27291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (3272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650ed65deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005650ed65ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005650ed65e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ff7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ff718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ff7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ff711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650ed5f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005650ed5f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650ed5d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005650ed287e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005650ed287b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ff711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ff711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ff711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650ed287a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (3273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598de1adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598de1aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598de1ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25a7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25a775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25a7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25a76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598de143bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598de143a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598de1288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598dddd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598dddd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25a76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25a76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25a76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598dddd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (3274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b6e783eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b6e780e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b6e78462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8684133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f868418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8684133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f868411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b6e719bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b6e719a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b6e6fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b6e3ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b6e3adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f868411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f868411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f868411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b6e3ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (3275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (3276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (3277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629b493aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629b4937e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629b493b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f8ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f8caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f8ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f8ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629b48d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629b48d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629b48b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629b4564e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629b4564b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f8ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f8ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f8ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629b4564a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (3278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vtdiscard() #0 { # | entry: # | call void @llvm.riscv.sf.vtdiscard() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtdiscard() #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564935b9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564935b9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564935ba062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70e5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70e558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70e5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70e551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564935b35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564935b35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564935b1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649357c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649357c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70e551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70e551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70e551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649357c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (3279 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | %1 = fpext bfloat %0 to float # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | %1 = fptrunc float %0 to bfloat # | ret bfloat %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055638c3e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055638c3e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055638c3e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3245933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f324598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3245933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f324591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638c37bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055638c37ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055638c3608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055638c00fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055638c00fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f324591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f324591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f324591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055638c00fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (3280 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/18895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d665abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d665a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d665ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0daa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0daa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0daa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0daa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d66541bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d66541a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d665268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d661d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d661d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0daa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0daa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0daa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d661d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (3281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.a # | ... # `---data was truncated (10240/41678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a6b9afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a6b9ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a6b9b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3d5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3d52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3d5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3d5231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a6b945bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a6b945a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a6b92a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a6b5d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a6b5d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff3d5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3d52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3d52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a6b5d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (3282 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask. # | ... # `---data was truncated (10240/28162) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d877e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d877e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d877e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7e5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d877daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d877daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d877d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d877a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d877a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d877a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (3283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (3284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (3285 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559d72f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559d72eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559d72f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6973d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6973d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6973d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6973d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559d7287bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559d7287a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559d726c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559d6f1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559d6f1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6973d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6973d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6973d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559d6f1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (3286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056226e1b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056226e1aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056226e1b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4851705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f485175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4851705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48516ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056226e147bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056226e147a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056226e12c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056226dddbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056226dddbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f48516eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48516ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48516ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056226dddba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (3287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630bd34ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630bd349e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630bd34d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feed7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feed74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feed7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feed7431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630bd2e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630bd2e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630bd2c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630bcf76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630bcf76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feed7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feed74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feed74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630bcf76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (3288 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e95e9e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e95e9dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e95e9e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb31a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb31a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb31a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb31a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e95e977bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e95e977a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e95e95c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e95e60be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e95e60bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb31a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb31a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb31a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e95e60ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (3289 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc393e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc393dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc393e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f738c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f738c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f738c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f738c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc39378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc39378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc3935d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc3900ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc3900cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f738c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f738c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f738c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc3900ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (3290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8207d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8207d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8207d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6af8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6af8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6af8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6af8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b82076cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b82076ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8207518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b820400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b820400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6af8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6af8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6af8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b820400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (3291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629425fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629425f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629425fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29bee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562942592bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562942592a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629425778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562942226e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562942226b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29bee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562942226a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (3292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d9f8c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d9f8c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d9f8c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbfb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbfb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbfb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbfb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d9f85abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d9f85aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d9f83f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d9f4eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d9f4eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbfb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbfb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbfb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d9f4eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (3293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556334d2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556334d29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556334d2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfc0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfc075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfc0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfc06ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556334cc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556334cc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556334ca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556334956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556334956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfc06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfc06ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfc06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556334956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (3294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d88d4ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d88d4cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d88d4cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9ee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9ee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9ee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9ee51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d88d464bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d88d464a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d88d4498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d88d0f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d88d0f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9ee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9ee51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9ee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d88d0f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (3295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e45823eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e45820e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e4582462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f621ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f621aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f621ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f621ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e457b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e457b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e4579e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e4544de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e4544db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f621ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f621ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f621ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e4544da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (3296 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # | #0 0x0000564fc0655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fc0652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fc065662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f956ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f956caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f956ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f956ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fc05ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fc05eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fc05d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fc027fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fc027fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f956ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f956ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f956ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fc027fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20.. 30.. 40 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (3607 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8b8f75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8b8f72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8b8f7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadb7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadb7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadb7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadb7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8b8f0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8b8f0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8b8ef08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8b8b9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8b8b9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadb7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadb7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadb7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8b8b9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. ******************** Failed Tests (3297): Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c Clang :: CodeGen/2005-09-24-AsmUserPrefix.c Clang :: CodeGen/2008-07-17-no-emit-on-error.c Clang :: CodeGen/AArch64/atomic-hint-template.cpp Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c Clang :: CodeGen/AArch64/fp8-cast.c Clang :: CodeGen/AArch64/fp8-extract.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c Clang :: CodeGen/AArch64/neon-2velem.c Clang :: CodeGen/AArch64/neon-3v.c Clang :: CodeGen/AArch64/neon-dot-product.c Clang :: CodeGen/AArch64/neon-extract.c Clang :: CodeGen/AArch64/neon-fma.c Clang :: CodeGen/AArch64/neon-fp16fml.c Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/neon-intrinsics.c Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c Clang :: CodeGen/AArch64/neon-misc-constrained.c Clang :: CodeGen/AArch64/neon-misc.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c Clang :: CodeGen/AArch64/neon-shifts.c Clang :: CodeGen/AArch64/neon-tbl.c Clang :: CodeGen/AArch64/neon-vcmla.c Clang :: CodeGen/AArch64/neon-vcombine.c Clang :: CodeGen/AArch64/neon-vget-hilo.c Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c Clang :: CodeGen/AArch64/neon/add.c Clang :: CodeGen/AArch64/neon/bf16-getset.c Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c Clang :: CodeGen/AArch64/neon/f16-getset.c Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiply.c Clang :: CodeGen/AArch64/neon/getset.c Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c Clang :: CodeGen/AArch64/neon/intrinsics.c Clang :: CodeGen/AArch64/neon/load.c Clang :: CodeGen/AArch64/neon/perm.c Clang :: CodeGen/AArch64/neon/rounding-v8.5.c Clang :: CodeGen/AArch64/neon/rounding.c Clang :: CodeGen/AArch64/neon/store.c Clang :: CodeGen/AArch64/neon/subtraction.c Clang :: CodeGen/AArch64/neon/vpaddl.c Clang :: CodeGen/AArch64/neon/widen.c Clang :: CodeGen/AArch64/poly128.c Clang :: CodeGen/AArch64/poly64.c Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c Clang :: CodeGen/AArch64/sve-vector-arith-ops.c Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vector-compare-ops.c Clang :: CodeGen/AArch64/sve-vector-shift-ops.c Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c Clang :: CodeGen/AArch64/sve-vls-arith-ops.c Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vls-compare-ops.c Clang :: CodeGen/AArch64/sve-vls-shift-ops.c Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c Clang :: CodeGen/AArch64/sve/addv.c Clang :: CodeGen/AArch64/sve/andv.c Clang :: CodeGen/AArch64/sve/dup.c Clang :: CodeGen/AArch64/sve/eorv.c Clang :: CodeGen/AArch64/sve/len.c Clang :: CodeGen/AArch64/sve/maxnmv.c Clang :: CodeGen/AArch64/sve/maxv.c Clang :: CodeGen/AArch64/sve/minnmv.c Clang :: CodeGen/AArch64/sve/minv.c Clang :: CodeGen/AArch64/sve/nand.c Clang :: CodeGen/AArch64/sve/nor.c Clang :: CodeGen/AArch64/sve/orn.c Clang :: CodeGen/AArch64/sve/orv.c Clang :: CodeGen/AArch64/sve/pfalse.c Clang :: CodeGen/AArch64/sve/recpe.c Clang :: CodeGen/AArch64/sve/recps.c Clang :: CodeGen/AArch64/sve/rsqrte.c Clang :: CodeGen/AArch64/sve/rsqrts.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/builtin-cpu-is.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c Clang :: CodeGen/RISCV/riscv-xcvalu.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c Clang :: CodeGen/RISCV/rvp-intrinsics.c Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/SystemZ/zvector.c Clang :: CodeGen/WebAssembly/builtins-table-externref.c Clang :: CodeGen/WebAssembly/builtins-table-funcref.c Clang :: CodeGen/X86/avx-cmp-builtins.c Clang :: CodeGen/X86/avx-shuffle-builtins.c Clang :: CodeGen/X86/bfloat16-convert-half.c Clang :: CodeGen/X86/sse.c Clang :: CodeGen/aapcs-bitfield.c Clang :: CodeGen/arm-bf16-convert-intrinsics.c Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c Clang :: CodeGen/arm-bf16-params-returns.c Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c Clang :: CodeGen/arm-cde-gpr.c Clang :: CodeGen/arm-cde-reinterpret.c Clang :: CodeGen/arm-cde-vec.c Clang :: CodeGen/arm-cde-vfp.c Clang :: CodeGen/arm-crc32.c Clang :: CodeGen/arm-mfp8.c Clang :: CodeGen/arm-mve-intrinsics/absneg.c Clang :: CodeGen/arm-mve-intrinsics/admin.c Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c Clang :: CodeGen/arm-mve-intrinsics/compare.c Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp Clang :: CodeGen/arm-mve-intrinsics/dup.c Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c Clang :: CodeGen/arm-mve-intrinsics/idup.c Clang :: CodeGen/arm-mve-intrinsics/load-store.c Clang :: CodeGen/arm-mve-intrinsics/predicates.c Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c Clang :: CodeGen/arm-mve-intrinsics/ternary.c Clang :: CodeGen/arm-mve-intrinsics/vabavq.c Clang :: CodeGen/arm-mve-intrinsics/vabdq.c Clang :: CodeGen/arm-mve-intrinsics/vadc.c Clang :: CodeGen/arm-mve-intrinsics/vaddq.c Clang :: CodeGen/arm-mve-intrinsics/vaddv.c Clang :: CodeGen/arm-mve-intrinsics/vandq.c Clang :: CodeGen/arm-mve-intrinsics/vbicq.c Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vclz.c Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c Clang :: CodeGen/arm-mve-intrinsics/vcvt.c Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c Clang :: CodeGen/arm-mve-intrinsics/veorq.c Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c Clang :: CodeGen/arm-mve-intrinsics/vld24.c Clang :: CodeGen/arm-mve-intrinsics/vldr.c Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c Clang :: CodeGen/arm-mve-intrinsics/vminaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c Clang :: CodeGen/arm-mve-intrinsics/vminq.c Clang :: CodeGen/arm-mve-intrinsics/vminvq.c Clang :: CodeGen/arm-mve-intrinsics/vmldav.c Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c Clang :: CodeGen/arm-mve-intrinsics/vmovl.c Clang :: CodeGen/arm-mve-intrinsics/vmovn.c Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vmulq.c Clang :: CodeGen/arm-mve-intrinsics/vornq.c Clang :: CodeGen/arm-mve-intrinsics/vorrq.c Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c Clang :: CodeGen/arm-mve-intrinsics/vrev.c Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vrnd.c Clang :: CodeGen/arm-mve-intrinsics/vshlc.c Clang :: CodeGen/arm-mve-intrinsics/vsubq.c Clang :: CodeGen/arm-neon-directed-rounding-constrained.c Clang :: CodeGen/arm-neon-directed-rounding.c Clang :: CodeGen/arm-neon-dot-product.c Clang :: CodeGen/arm-neon-endianness.c Clang :: CodeGen/arm-neon-fma.c Clang :: CodeGen/arm-neon-numeric-maxmin.c Clang :: CodeGen/arm-neon-shifts.c Clang :: CodeGen/arm-neon-vcadd.c Clang :: CodeGen/arm-neon-vcvtX.c Clang :: CodeGen/arm-neon-vget.c Clang :: CodeGen/arm-neon-vld.c Clang :: CodeGen/arm-neon-vst.c Clang :: CodeGen/arm-poly-add.c Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c Clang :: CodeGen/arm-vector_type-params-returns.c Clang :: CodeGen/arm64-crc32.c Clang :: CodeGen/arm64-lanes.c Clang :: CodeGen/arm64_vcopy.c Clang :: CodeGen/arm64_vcreate.c Clang :: CodeGen/arm64_vdupq_n_f64.c Clang :: CodeGen/arm_acle.c Clang :: CodeGen/arm_acle_swp.c Clang :: CodeGen/arm_neon_intrinsics.c Clang :: CodeGen/attr-counted-by-issue200014.c Clang :: CodeGen/builtin-align.c Clang :: CodeGen/builtins-arm-exclusive.c Clang :: CodeGen/builtins-arm.c Clang :: CodeGen/builtins-arm64.c Clang :: CodeGen/builtins-loongarch.c Clang :: CodeGen/builtins-riscv.c Clang :: CodeGen/cx-complex-range-real.c Clang :: CodeGen/cx-complex-range.c Clang :: CodeGen/distributed-thin-lto/backend-skip.ll Clang :: CodeGen/distributed-thin-lto/basic.ll Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll Clang :: CodeGen/distributed-thin-lto/cfi.ll Clang :: CodeGen/distributed-thin-lto/newpm.ll Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll Clang :: CodeGen/linker-diagnostic.ll Clang :: CodeGen/memcmp-inline-builtin-to-asm.c Clang :: CodeGen/mozilla-ms-inline-asm.c Clang :: CodeGen/packed-structure.c Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll Clang :: CodeGen/thinlto-funcattr-prop.ll Clang :: CodeGen/thinlto-multi-module.ll Clang :: CodeGen/thinlto-opaque-typed-mix.ll Clang :: CodeGen/thinlto_backend.ll Clang :: CodeGen/thinlto_backend_local_name_conflict.ll Clang :: CodeGen/thinlto_embed_bitcode.ll Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp Clang :: CodeGenCXX/attr-musttail.cpp Clang :: CodeGenCXX/ctor-globalopt.cpp Clang :: CodeGenCXX/inline-then-fold-variadics.cpp Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll Clang :: CodeGenCXX/virtual-base-ctor.cpp Clang :: CodeGenCoroutines/coro-gro4.cpp Clang :: CodeGenCoroutines/pr65054.cpp Clang :: CodeGenHIP/offload-pgo-sections.hip Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl Clang :: Modules/pr93497.cppm Testing Time: 158.62s Total Discovered Tests: 55926 Skipped : 37 (0.07%) Unsupported : 1675 (3.00%) Passed : 50888 (90.99%) Expectedly Failed: 29 (0.05%) Failed : 3297 (5.90%) FAILED: gen/clang/test/run-lit python3 bin/llvm-lit -sv ../../clang/test ninja: build stopped: subcommand failed. Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.